WO2013070806A1

WO2013070806A1 - Voltage switchable dielectric material formations and supporting impedance elements for esd protection

Info

Publication number: WO2013070806A1
Application number: PCT/US2012/063999
Authority: WO
Inventors: Joan Vrtis; Daniel Vasquez; Robert Fleming; Lex Kosowsky
Original assignee: Shocking Technologies, Inc.
Priority date: 2011-11-07
Filing date: 2012-11-07
Publication date: 2013-05-16
Also published as: TWI510148B; TW201334640A

Abstract

Embodiments disclosed herein generally relate to voltage switchable dielectric (VSD) materials and supporting impedance elements, and to structures, methods and devices employing voltage switchable dielectric materials and supporting impedance elements to achieve protection against ESD events, wherein the VSD materials and/or supporting impedance elements are incorporated in first level and/or second level packages, and wherein the first level package may be a die attached to a substrate and the second level package may be a circuit board to which the first level package is attached.

Description

Voltage Switchable Dielectric Material Formations

and Supporting Impedance Elements for ESD Protection

FIELD OF THE INVENTION

[0001] Embodiments disclosed herein generally relate to voltage switchable dielectric (VSD) materials and supporting impedance elements, and to structures, methods and devices employing voltage switchable dielectric materials and supporting impedance elements to achieve protection against ESD events, wherein the VSD materials and/or supporting impedance elements are incorporated in first level and/or second level packages, and wherein the first level package may be a die attached to a substrate and the second level package may be a circuit board to which the first level package is attached.

BACKGROUND OF THE INVENTION

[0002] Electronic devices are often fabricated by assembling and connecting various electronic components.

Many components, particularly semiconductors, are sensitive to spurious electrical events that apply excessive voltage to the devices in what is termed an overvoltage condition. Examples of sources of overvoltage conditions include electrostatic discharge (ESD), back electromotive force (EMF), lightning, solar wind, switched electromagnetic induction loads such as electric motors and electromagnets, switched heavy resistive loads, large current changes, electromagnetic pulses, and the like. Overvoltage conditions may result in a high voltage at a device containing active and/or passive electronic components or circuit elements, such as a semiconductor IC chip, which may cause large current flow through or within the components. The large current flow may effectively destroy or otherwise negatively impact the functionality of such active or passive components or circuit elements.

[0003] ESD events may occur during normal operation of an electronic device (e.g., while a user is handling a mobile phone), during the manufacturing of an electronic device or substrate (e.g., during the manufacturing of a PCB or during the assembly of an LED display), or during any other stage of handling an electronic device, electronic component or substrate (e.g., during transportation, installation, interconnection, etc.).

[0004] Some chips include "on-chip" protection against some overvoltage events (e.g., a mild ESD event) that may be expected during packaging of the chip or operation of the respective electronic device (e.g., protection against Human Body Model events).

[0005] A chip may be packaged (e.g., embedded in a protective chip packaging or otherwise attached to a chip substrate). A packaged chip may be connected to additional (e.g., ex-chip) overvoltage protection devices, that protect the packaged chip against more severe (e.g., higher voltage) overvoltage events. Inasmuch as the on-chip and off-chip overvoltage protection devices are in electrical communication, the off-chip overvoltage protection device may be required to "protect" the on-chip overvoltage protection device. Examples of specifications for ESD testing include IEC 61000-4-2 and JESD22-A114E.

[0006] A printed circuit board, printed wiring board, or similar substrate (also referred to as PCB) may be used to assemble, support, and connect electronic components. A PCB typically includes a substrate of dielectric material and one or more conductive leads to provide electrical conductivity among various attached components, chips, and the like. Typically, a pattern of metallic leads is plated (e.g., using printing technology such as silk-screening) onto the dielectric substrate to provide electrical connectivity. Alternatively a metallic layer (e.g., a layer of Cu, Ag, Au) is applied to the substrate and subsequently portions of the metallic layer are removed (e.g., etched) resulting in the desired pattern. Multiple layers of conductive patterns and/or dielectric materials may be disposed on a PCB. The layers may be connected using vias. Printed circuit boards including 14 or more layers are not uncommon.

[0007] A PCB is typically used for supporting and connecting various integrated electronic components, such as chips, packages, and other integrated devices. The PCB may also support and connect discrete components, such as resistors, capacitors, inductors, and the like, and provide connections between integrated and discrete components. The conductive patterns and/or layers in the PCB and other components or areas within electronic devices sometimes provide paths for conducting overvoltage events that could damage or otherwise negatively impact components.

[0008] Various structures, methods and devices exist in the prior art for providing overvoltage protection to electronic devices (e.g., discrete surge suppression components surface mounted to PCBs), but they generally exhibit a variety of limitations in manufacturability, performance, operational

characteristics and cost. There is a need for improved overvoltage protection structures, methods and devices.

SUMMARY OF THE INVENTION

[0009] Embodiments disclosed herein generally relate to structures, methods and devices employing voltage switchable dielectric materials and impedances to achieve protection against ESD and other overvoltage events.

INCORPORATION BY REFERENCE

[0010] All publications, patents, and patent applications mentioned in this specification, if any, are herein incorporated by reference to the same extent as if each individual publication, patent, or patent application was specifically and individually indicated to be incorporated by reference. To the extent that any inconsistency or conflict may exist between information disclosed in this patent and information disclosed in any publication, patent, or patent application incorporated by reference in this patent, the information disclosed in this patent will take precedence and prevail.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying figures, which together with the detailed description below are incorporated in and form part of the specification, serve to further illustrate various embodiments and to explain various principles and advantages all in accordance with example embodiments of the present inventions.

[0012] FIG. 1 shows a horizontal switching VSDM formation that may be used for ESD protection of

electronic components, in accordance with an embodiment.

[0013] FIG. 2 shows a horizontal switching VSDM formation that may be used for ESD protection of

electronic components, in accordance with an embodiment.

[0014] FIG. 3 illustrates a PCB and associated directional references used in connection with various

embodiments.

[0015] FIG. 4A shows a vertical switching formation VSDM formation that may be used for ESD protection of electronic components, in accordance with an embodiment.

[0016] FIG. 4B shows a vertical switching formation VSDM formation that may be used for ESD protection of electronic components, in accordance with an embodiment.

[0017] FIG. 5 shows a VSDM formation that may be used for ESD protection of electronic components in connection with an embedded circuit element having a non-negligible impedance, in accordance with an embodiment.

[0018] FIG. 6 shows a graph with sample response voltage envelopes for a VSDM formation, in accordance with an embodiment.

[0019] FIG. 7 shows a circuit configuration that uses a VSDM component in combination with an

impedance element to protect an electronic component against ESD events, in accordance with an embodiment.

[0020] FIG. 8 shows another circuit configuration that uses a VSDM component in combination with an impedance element to protect an electronic component against ESD events, in accordance with an embodiment.

[0021] FIG. 9 shows another circuit configuration that uses a VSDM component in combination with an impedance element to protect an electronic component against ESD events, in accordance with an embodiment.

[0022] FIG. 10 shows another circuit configuration that uses a VSDM component in combination with an impedance element to protect an electronic component against ESD events, in accordance with an embodiment. [0023] FIG. 11 shows another circuit configuration that uses a VSDM component in combination with an impedance element to protect an electronic component against ESD events, in accordance with an embodiment.

[0024] FIG. 12A shows another circuit configuration that uses a VSDM component in combination with an impedance element to protect an electronic component against ESD events, in accordance with an embodiment.

[0025] FIG. 12B shows another circuit configuration that uses a VSDM component in combination with an impedance element to protect a die against ESD events, in accordance with an embodiment.

[0026] FIG. 13 shows another circuit configuration that uses a VSDM component in combination with an impedance element to protect an electronic component against ESD events, in accordance with an embodiment.

[0027] FIG. 14 shows another circuit configuration that uses a VSDM component in combination with an impedance element to protect an electronic component against ESD events, in accordance configured as a an embodiment.

[0028] FIG. 15 shows another circuit configuration that uses a VSDM component in combination with an impedance element to protect an electronic component against ESD events, in accordance with an embodiment.

DETAILED DESCRIPTION

[0029] While the specification concludes with claims defining aspects of the invention that are regarded as novel, the invention will be better understood from the following description in conjunction with the drawing figures, in which like reference numerals are carried forward.

[0030] 1. General Overview of VSD Materials and VSDM Structures.

[0031] Protection against ESD and other overvoltage events of a substrate device, electronic component and/or electronic device in accordance with various embodiments of the present invention may include incorporating a voltage switchable dielectric material ("VSD material" or "VSDM") in the respective substrate and/or device. While those skilled in the art will recognize that overvoltage events encompass multiple events, ESD (electrostatic discharge) may be used herein to generally describe an overvoltage event.

[0032] In one embodiment, the VSD material is embedded in the device as a layer or other structure that is adapted to conduct at least a portion of an ESD signal through the device to a ground or to another predefined point.

[0033] In one embodiment, a circuit element such as a filter is disposed between a vertical switching VSDM formation and an electronic component to reduce or prevent high frequency voltage components generated by an ESD event from reaching the electronic component. The circuit element may be embedded in a substrate device as a layer, a structure, or a via, or may be attached to a substrate as a surface mounted component.

[0034] A VSD material in accordance with various embodiments of the present invention is a material that exhibits nonlinear resistance as a function of voltage. While a VSD material exhibits nonlinear resistance, not all materials that exhibit nonlinear resistance are VSD materials. For example, a material for which resistance changes as a function of temperature but does not substantially change as a function of voltage would not be construed as a VSD material for purposes of embodiments of the present invention. In various embodiments, VSD materials exhibit nonlinear resistance variation as a function of voltage and additional operating parameters such as current, energy field density, light or other electromagnetic radiation input, and/or other similar parameters.

[0035] The variation of the resistance as a function of voltage exhibited by a VSD material includes a

transition from a state of high resistance to a state of low resistance. This transition occurs at about a specific voltage value, which may be variously referred to as a "characteristic voltage,"

"characteristic voltage level," "switching voltage," or "switching voltage level." The characteristic voltage may differ for various formulations of VSD material, but is relatively stable for a given formulation. The characteristic voltage for a particular formulation may be a function of voltage coupled with additional parameters such as temperature and/or incident electromagnetic energy at various wavelengths including optical, infrared, UV, or microwave.

[0036] For a given VSD material composition, the characteristic voltage may be defined in terms of a

corresponding "characteristic electric field" or "characteristic field" expressed in terms of voltage per unit of length (e.g., Volts per mil (V/mil), Volts per micrometer (V/um), etc.).

[0037] Unless otherwise expressly indicated, the term "structure of VSD material," "VSD material

structure" or "VSDM structure" is intended to refer to any volume of VSD material with specific physical dimensions that can perform an electrical switching function. Examples of a structure of VSD material include a layer of VSD material (whether disposed on a substrate or cured as a standalone layer), a volume of VSD material bounded between two or more electrodes and/or

semiconductor structures, or any other element or configuration of VSD material that can switch between substantially nonconductive and substantially conductive states in response to a sufficiently large voltage variation.

[0038] In one implementation, a VSDM structure may be produced by bounding a volume of a first VSD material with a first characteristic voltage between two other volumes of VSD materials with characteristic voltages that differ from the first characteristic voltages (the characteristic voltages of the two other volumes of VSD material may or may not be equal to each other).

[0039] In one implementation, a VSDM structure may be produced by bounding a volume of a VSD

material with a first characteristic voltage between (a) a volume of VSD material with a different characteristic voltage, and (b) one or more electrodes and/or semiconductor structures. [0040] An example of a VSDM structure is a layer of VSD material disposed on a copper foil (but excluding the copper foil). A compound formation that comprises both the layer of VSD material and the copper foil may be denoted a "formation of VSDM." More complex formations of VSDM are discussed below.

[0041] Another example of a VSDM structure is a coating, sheet or other layout of VSD material disposed as a horizontal layer in a PCB and bounded between two adjacent horizontal layers of the PCB (i.e., a horizontal layer above the VSDM structure, and a horizontal layer below the VSDM structure). A compound formation that comprises both this VSDM structure and the bounding two adjacent horizontal layers would be an example of a formation of VSDM.

[0042] Another example of a VSDM structure is a volume of VSD material disposed in a horizontal layer within a PCB and bounded between four structures disposed within the same horizontal layer of the PCB (e.g., four etched channels that delineate a rectangular VSDM structure) and between two electrodes disposed in the two adjacent horizontal layers (e.g., a conductive layer above and an insulative layer below). A compound formation that comprises both this VSDM structure and the bounding four structures and two electrodes would be an example of a formation of VSDM.

[0043] For a structure of VSD material with a known distance between two points where a voltage is

applied (e.g., when a voltage is applied across the thickness of a layer of VSD material or across another gap of a VSDM structure), the characteristic voltage may be defined as specific voltage value (e.g., the characteristic voltage for this VSDM structure may be specified as a particular value in Volts).

[0044] Consequently, the characteristic voltage of a VSDM structure may be defined in terms of a

characteristic electric field expressed as a voltage value per unit length, or as a characteristic voltage expressed as a specific voltage value when the VSD material is considered as a specific volume with certain known dimensional characteristics (e.g., a VSDM structure with a specific thickness across which voltage switching may occur). In various contexts, the descriptions in this patent may refer to characteristic fields or characteristic voltages of VSD materials in connection with various embodiments, and in each case the corresponding characteristic fields (in terms of Volts per unit length) or characteristic voltages (in terms of Volts) may be obtained through an appropriate conversion by taking into account the dimensional characteristics of the respective structures of VSD material. For example, for a uniform characteristic electric field produced within a VSDM structure, the characteristic voltage of that VSDM structure may be obtained by multiplying the characteristic field of that VSD material (in V/mil) by the corresponding gap across which switching will take place (in mils)). In a more general sense, the characteristic field is a function of the electrode gap but other factors may play a role such as actual conduction path, cross-sectional area, and VSD material thickness. In some embodiments, for some formulations of VSD materials and physical

characteristics of the gaps across which switching may take place, the characteristic voltage of the VSD material across such gaps may not be directly or linearly correlated with the size of the respective gaps (e.g., in such embodiments, the respective characteristic voltages may be evaluated through direct measurements or through more complex simulations or approximations).

[0045] In various embodiments, the characteristic voltage of a VSDM structure disposed between two electrodes contacting the VSD material decreases as the distance between the electrodes decreases. The distance between the electrodes across which the VSD material may switch between substantially conductive and substantially nonconductive states in response to voltage variations that are sufficiently large could be denoted a "thickness," "effective thickness," "gap," "switching gap," or "effective gap." The effective gap for a VSDM structure could be considered to be horizontal if the two electrodes are disposed in a substantially horizontal plane and/or if the voltage switching takes place predominantly in a horizontal direction, or could be considered to be vertical if the two electrodes are disposed in different vertical planes and/or if the voltage switching takes place predominantly in a vertical direction.

[0046] If for a given VSD material composition the characteristic field of the VSD material is defined in terms of Volts per mil (V/mil) (or otherwise in terms of Volts per unit length), the characteristic voltage for a layer or structure of VSD material with a specific thickness may be determined as a specific voltage value. For example, if the size of a gap across which a VSD material may switch is denoted T (e.g., the gap 150 between the electrodes 120 and 122 in the embodiment of FIG. 1 or the gap 542 across the thickness of the layer of VSD material 540 in the embodiment of FIG. 5) and the characteristic field of the VSD material expressed in Volts per mil is denoted E_CH, the corresponding characteristic voltage value expressed in Volts may be denoted VCH and may be expressed as follows:

[0047] VCH (V) = ECH (V/mil) * T (mil) (Eq. 1)

[0048] The formula in Eq. 1 generally holds true if the value of the characteristic field ECH is assumed to be constant, or may be approximated as constant across the respective thickness T.

[0049] In general, however, the characteristic field ECH may not be constant across the respective gap of the VSD material, and may have a value that varies across the thickness of the VSDM structure. To the extent that the characteristic field ECH is not constant over the switching gap of a VSD formation, the characteristic voltage VCH could be obtained through modeling, through direct or indirect measurements, through approximations, or in any other way that permits establishing a sufficiently accurate relationship between the characteristic field and characteristic voltage.

[0050] From Eq. 1 , it can be seen that by reducing the size of a switching gap of a VSD material, the

characteristic voltage of the respective VSDM structure is correspondingly reduced. [0051] In general, the characteristic voltage of a VSDM structure may be a function of the amount, cross- sectional area, volume, depth, thickness, width and/or length of the VSDM structure that is disposed between the two points where the voltage is applied, and possibly also a function of the relative shape, geometry, density variation, and other analogous variables relating to the VSDM structure.

[0052] A VSD material is substantially non-conductive (i.e., substantially insulative) at voltages below the respective characteristic voltage level, in which case it behaves substantially as an insulator or dielectric. This state may be referred to as a substantially nonconductive or insulative state.

Voltages below the characteristic voltage level of a VSD material may be referred to as low voltages (at least relative to voltages above the characteristic voltage level). In such operating regimes below the characteristic voltage level, a VSD material provided in embodiments of the current invention may also be construed as having attributes of a semiconductor, similar to semiconductor materials that are suitable to serve as substrates in semiconductor manufacturing processes. A VSD material in accordance with various embodiments may behave substantially as an insulator for both positive and negative voltages when the magnitude of the voltage is below the characteristic voltage level.

[0053] At voltages higher than its characteristic voltage level, a VSD material in accordance with various embodiments of the present invention behaves substantially as a conductor. This may be referred to as a substantially conductive state. Voltage above the characteristic voltage level may be referred to as high voltage. The VSD material is conductive or substantially conductive for both positive and negative voltages when the magnitude of the voltage is above the characteristic voltage level. The characteristic voltage may be either positive or negative, depending on the polarity of the voltage being applied. When a VSD material becomes substantially conductive in response to a voltage that exceeds its characteristic voltage, the VSD material could be said to "switch on." When a VSD material becomes substantially non-conductive after removing a voltage that exceeds its

characteristic voltage, the VSD material could be said to "switch off." When a VSD material switches on or off, the VSD material could be simply said to "switch."

[0054] In an ideal model, the operation of a VSD material provided in various embodiments of the present invention is approximated as having infinite resistance at voltages below the characteristic voltage, and low resistance at voltages above the characteristic voltage. In normal operating conditions, however, such VSD materials typically have high, but finite resistance at voltages below the characteristic voltage, and low, but nonzero resistance at voltages above the characteristic voltage. As an example, for a particular VSD material, the ratio of the resistance at low voltage to the resistance at high voltage may be expected to approach a large value (e.g., in the range of 10³, 10⁶, 10⁹, 10¹², or higher). In an ideal model, this ratio may be approximated as infinite, or otherwise very high.

[0055] The VSD material provided in various embodiments of the present invention exhibits high

repeatability (i.e., reversibility) in its operation in both the low voltage regimes and the high voltage regimes. In some embodiments, the VSD material behaves substantially as an insulator or dielectric (i.e., is substantially nonconductive and exhibits a very high or substantially infinite electric resistance) at voltages below the characteristic voltage level. The VSD material then switches to become substantially conductive when operated at voltages above the characteristic voltage level, then becomes again substantially an insulator or dielectric at voltages below the characteristic voltage. The VSD material can continue to alternate between these two operational states if the input voltage levels transition between voltages below the characteristic voltage and above the

characteristic voltage. While transitioning between these two operational states, a VSD material may experience a certain level of hysteresis, which may alter to a certain extent the characteristic voltage level, the switching response time, or other operational characteristics of the VSD material.

[0056] The transition between the first (lower) voltage regime when the VSD material is substantially

insulative and the second (higher) voltage regime when the VSD material is substantially conductive in accordance with embodiments of the current invention is substantially predictable and is expected to be generally confined to a limited envelope of signal amplitudes and a limited range of switching times. In an ideal model, the time that it takes a VSD material to transition from a state of substantial insulation to a state of substantial conductance in response to an input step function signal that rises above the characteristic voltage may be approximated to be on the order of nanoseconds or less. That is, the transition may be approximated, at least in relative terms, to be substantially

instantaneous. Similarly, in an ideal model, the time that it takes a VSD material to transition from a state of substantial conductance to a state of substantial non-conductance in response to an input step function signal that drops below the characteristic voltage may be approximated as zero. This reverse transition may also be approximated to be substantially instantaneous. Under normal operating conditions, however, both of these transition times for VSD materials are non-zero. In general, such transition times are small, and are preferably as small as possible (e.g., in the range of about 10^"6 seconds, 10^~9 seconds, 10^~12 seconds, or smaller). Further details of the formulations and characteristics of VSD materials are disclosed in U.S. patent number 7,872,251, issued on January 18, 201 1 to Kosowsky, et al, and titled "Formulations for Voltage Switchable Dielectric Material Having a Stepped Voltage Response and Methods for Making the Same," which is hereby incorporated by reference in its entirety.

[0057] When in a substantially conductive state, a VSD material in accordance with various embodiments may direct an electrical signal to ground or to another predetermined point within the respective circuit, substrate or electronic device to protect an electronic component. In various embodiments, the predetermined point is a ground, virtual ground, shield, safety ground, and the like. Examples of electronic components that may be operated with and/or protected by VSD materials in accordance with various embodiments of the present invention include (a) circuit element, circuit structure, surface mounted electric component (e.g., resistors, capacitors, inductors), PCB or other circuit board, electronic device, electronic subsystem, electronic system, (b) any other electric, magnetic, microelectromechanical structure (MEMS) or similar element, structure, component, system and/or device, (c) any other unit that processes or transmits data and operates using electric signals or may be damaged by electric signals, and (d) any combination of the foregoing identified in (a), (b) and/or (c) above.

[0058] In general, a VSD material may have a limited ability to conduct current or otherwise operate in the presence of high signal voltages, current intensities, and energy or power levels before being damaged, possibly irreversibly damaged. Additionally, a VSD material may also be damaged if an electric signal that is normally within operating specifications persists for too long (e.g., the VSD material may heat up while conducting such signals and eventually break down). For example, a VSD material may be able to function normally when exposed to an input signal with a voltage level of 10 KV that lasts less than 100 nanoseconds, but may be damaged if that signal continues to be applied for more than a few milliseconds. The ability of a VSD material to tolerate high levels of voltage, current, power or energy before becoming damaged may depend on various factors, such as the particular composition of the VSD material, the specific characteristics of a corresponding VSDM structure (e.g., a VSDM structure with larger physical dimensions may be able to conduct higher current densities), the corresponding circuit architecture, the presence of other ESD protective components, and the characteristics of the device in which the VSD material is incorporated.

[0059] VSD materials in accordance with various embodiments are polymer composites, and may include particulate materials such as metals, semiconductors, ceramics, and the like. Examples of various compositions of VSD materials that may be used in accordance with various embodiments are described in, for example, US Patent Application Number 12/953,309 filed on November 23, 2010 and titled "Formulations for Voltage Switchable Dielectric Materials Having a Stepped Voltage Response and Methods for Making the Same," , US Patent Application Number 12/832,040 filed on July 7, 2010 and titled "Light-Emitting Diode Device For Voltage Switchable Dielectric Material Having High Aspect Ratio Particles," and US Patent Application Number 12/717,102 filed on March 3, 2010 and titled "Voltage Switchable Dielectric Material Having High Aspect Ratio Particles," and United States Patent 7,981,325 issued on July 19,2011 and titled "Electronic Device For Voltage Switchable Dielectric Material Having High Aspect Ratio Particles."

[0060] VSD materials in accordance with various embodiments may include a matrix material and one or more types of organic and/or inorganic particles dispersed within the matrix material.

[0061] Examples of matrix materials incorporated in VSD materials in accordance with various

embodiments may include organic polymers, such as silicone polymer, phenolic resin, epoxy (e.g., EPON Resin 828, a difunctional bisphenol A/epichlorohydrin derived liquid epoxy resin), polyurethane, poly(meth) acrylate, polyamide, polyester, polycarbonate, polyacrylamides, polyimide, polyethylene, polypropylene, polyphenylene oxide, polysulphone, ceramer (a solgel/polymer composite), and polyphenylene sulfone. Other examples of such matrix materials include inorganic polymers, such as siloxane, and polyphosphazines.

[0062] Examples of particles incorporated in VSD materials in accordance with various embodiments may include conductive and/or semiconductive materials, including copper, aluminum, nickel, silver, gold, titanium, stainless steel, chrome, tungsten, other metal alloys and oxides, T, Si, NiO, SiC, ZnO, BN, C (including in the form of diamond, nanotubes, and/or fullerenes), ZnS, B12O₃, Fe203, CeC^, T1O2, CuO, WO₃, A1N, and compounds of indium diselenide. In some embodiments, T1O2 can be undoped or doped, for example with WO₃, where doping may include a surface coating. Such particles may have a shape ranging from spherical to highly elongated, including high aspect ratio particles, including carbon nanotubes (single walled and/or multi-walled), fullerenes, metal nanorods, or metal nanowires. Examples of materials that form nanorods and/or nanowires include boron nitride, antimony tin oxide, titanium dioxide, zinc oxide, silver, copper, tin, and gold.

[0063] The aspect ratio of some particles incorporated in VSD materials in accordance with various

embodiments may have aspect ratios in excess of 3 : 1, 10: 1, 100: 1, and 1000: 1. Materials with higher aspect ratios are sometimes called "High Aspect Ratio" particles or "HAR" particles. Carbon nanotubes are examples of super HAR particles, with aspect ratios of an order of 1000: 1 and more. Materials with lesser aspect ratios that may be incorporated in VSD materials in various

embodiments include carbon black (L/D of any order of 10: 1) particles, and carbon fiber (L/D of an order of 100: 1) particles.

[0064] The particles incorporated in VSD materials in accordance with various embodiments may have various sizes, including some nanoscale particles characterized by a smallest dimension equal to 500 nm or smaller, or even smaller (e.g., particles for which a smallest dimension is less than 100 nm or 50 nm).

[0065] The particles incorporated in VSD materials in accordance with various embodiments may include an organic material. Incorporating organic materials within a VSD material may provide to the VSD material improved coefficients of thermal expansion and thermal conductivity, better dielectric constant, enhanced fracture toughness, better compression strength, and improved ability to adhere to metals. Examples of organic semiconductors that may be incorporated in VSD materials in various embodiments include forms of carbon such as electrically semiconducting carbon nanotubes and fullerenes (e.g., C60 and C70). Fullerenes and nanotubes can be modified, in some embodiments, to be functionalized to include a covalently bonded chemical group or moiety. Other examples of organic semiconductors that may be incorporated in VSD materials in various embodiments include poly-3-hexylthiophene, polythiophene, polyacteylene, poly (3,4-ethylenedioxythiophene), poly(styrenesulfonate), pentacene, (8-hydroxyquinolinolato) aluminum (III), and N,N'-di- [(naphthalenyl)-N,N'diphenyl]-l, l '-biphenyl-4,4'-diamine [NPD]. Additionally, organic semiconductors can be derived from the monomers, oligomers, and polymers of thiophene, analine, phenylene, vinylene, fluorene, naphthalene, pyrrole, acetylene, carbazole, pyrrolidone, cyano materials, anthracene, pentacene, rubrene, perylene, and oxadizole. Some of these organic materials may be photo-active organic materials, such as polythiophene.

[0066] In reference to distribution of particles within a VSD material polymeric composition, distributing particles "substantially uniformly" means that on the average the respective particles are distributed uniformly and/or randomly within the material, but it is certainly possible that in limited subportions of the polymeric composition nonuniform and/or non-random agglomerations of such particles may occur. Indeed, even after extensive mixing, there will normally be a nonzero statistical probability with which such agglomerations of particles may occur within limited volumes within the VSD material, and this could happen though all phases of the VSD material, including when the VSD material is in a liquid or semi-liquid form before application to a substrate, after it is disposed on a substrate (for example through coating), and/or after it is cured (whether on a substrate or otherwise). Overall, however, when considering the whole quantity of VSD material (or a sufficiently large subportion of such VSD material) the respective particles may be deemed to be distributed uniformly and/or randomly within the mixture, and in modeling the behavior of the respective VSD material, the particles may be modeled as being distributed uniformly and/or randomly.

[0067] 2. Exemplary Horizontal Switching VSDM Formations.

[0068] FIG. 1 shows a horizontal switching VSDM formation 100 comprising VSD material that may be used for ESD protection of electronic components, in accordance with an embodiment. In the embodiment of FIG. 1, electrodes 120 and 122 are in electrical contact with vias 130 and

respectively 132.

[0069] In general, the term "electrode" may be or may include any conductive structure. Examples of such electrodes or conductive structures include a pad, lead, trace, via (e.g., a through hole, a blind via, or a buried via), wire, conductive film, signal layer, conductive layer, conductive PCB layer (e.g., a conductive pre-preg or filler layer), or any other connector that is designed to be conductive and to provide electrical interconnection functionality in any substrate (e.g., such substrates could include any PCB or semiconductor packaging).

[0070] In various implementations, one or both electrodes 120 and 122 may be omitted as long as an

electrical connection can be established to via 130 and/or via 132. Electrode 120 and/or 122 may be manufactured out of copper or any other suitable conductive material. Electrode 120 and/or 122 may be manufactured through deposition, screen printing, adhesion, or any other bonding approach, whether mechanical, chemical, or otherwise.

[0071] In various embodiments, the electrodes 120 and 122 may be covered by an encapsulating material or formation, such as an insulating layer. In FIG. 1, the electrodes 120 and 122 are illustrated as being embedded in an insulating layer 170. [0072] Via 130 and 132 are conductive structures that may penetrate fully or partially, or may completely cross the layer of VSD material 140. Via 130 and/or 132 could be a through hole, a blind via, a buried via, a trace, or any other conductive structure that is designed to be conductive and facilitate signal propagation in an electronic device. Via 130 and/or 132 may be manufactured out of copper or any other suitable conductive material. Via 130 and/or 132 may be manufactured through deposition, screen printing, adhesion, or any other bonding approach, whether mechanical, chemical or otherwise. Via 130 and/or 132 may be solid (e.g., a solid metallic structure), hollow (e.g., a conductive curved or cylindrical formation), or may be hollow and partially or fully filled with a suitable conductive material (e.g., a hollow conductive curved or cylindrical formation that is filled partially with a conductive material).

[0073] In one embodiment, instead of being strictly conductive, via 130 and/or 132 are filled partially or completely with VSD material. In such an embodiment, via 130 and/or via 132 may serve as either a vertical or a horizontal switching formation, in the sense that the respective via would normally act as a substantially insulative structure, but may become substantially conductive in response to a voltage that exceeds the characteristic voltage of the respective VSD material. In such an embodiment, the switching could take place either vertically along the respective via, or horizontally across the respective via.

[0074] In the embodiment of FIG. 1, the layer of VSD material 140 is disposed on a substrate 160. The substrate 160 may be a conductive substrate (e.g., a layer, sheet or foil of copper or other conductive material), or an insulative substrate (e.g., a PCB pre-preg layer). In one embodiment, the substrate 160 may be a substrate with variable conductivity, such as a layer of VSD material.

[0075] In the embodiment of FIG. 1, a voltage source may be connected so that it produces a voltage

differential between electrodes 120 and 122. The voltage source 1 10 is shown in FIG. 1 as a standalone voltage source, which could also be a current source, or any other source of electrical energy. Such an arrangement may be encountered in a testing setup, or in a specific architectural layout where the VSD material is intended to be activated intentionally by increasing the voltage generated by the voltage source 1 10. The voltage source 110 is illustrated in FIG. 1 as connected to via 130, which is in electrical contact with electrode 120, and a ground is illustrated as connected to via 132, which is in electrical contact with electrode 122. In various alternative applications and

embodiments, the voltage source 110 may be applied to via 132 and the ground may be applied to via 130.

[0076] In a more general sense, however, the voltage that is applied between the electrodes 120 and 122 may be any voltage signal or other electrical signal, including a voltage that is generated by an ESD event, as illustrated by the ESD pulse 1 12 shown in the embodiment of FIG. 1. In normal operating circumstances that are usually experienced by end user devices, such as mobile phones, the ESD pulse 1 12 may be expected to have a high voltage magnitude (e.g., in excess of a few hundred Volts, and possibly a few thousand Volts) and a short time duration (e.g., anywhere between nanoseconds and microseconds). Despite the short time duration, the electrical current generated by the ESD pulse 1 12 may be expected to reach large amplitudes, possibly in excess of 10 Amperes. If the structure of the embodiment of FIG. 1 is used for ESD protection, either electrode 120 or electrode 122 may be connected directly or indirectly to a ground plane (or another predetermined point within the circuit or device being protected), and if the ESD pulse 112 reaches the other electrode, the ESD pulse 1 12 may be guided to ground or to that predetermined point through the electrode connected to the ground or predetermined point.

[0077] If the voltage applied by the voltage source 1 10 (or alternatively by the ESD pulse 1 12) does not exceed the characteristic voltage of the VSD material 140, the VSD material 140 remains substantially nonconductive, and no significant current is conducted between the electrodes 120 and 122 through the VSD material 140 (except, possibly, for a certain amount of leakage current, which the VSD material 140 is normally designed to minimize so as not to impact the performance of the electronic device in which the structure of 100 may be deployed).

[0078] To graphically illustrate that the voltage source 1 10 and the ESD pulse 1 12 may be present in the alternative and are used for purposes of general description, the connecting lines between each of them and the electrodes 120 and 122 are shown with a dashed line. In general, any voltage source, ESD signal, or other electrical source, overvoltage signal, or voltage potential may be applied between the two electrodes 120 and 122. Either of the two electrodes may also be connected to ground, or to a point with another reference voltage level. The polarity of the voltage source 1 10 may be in either direction between the electrodes 120 and 122. Analogously,

[0079] If the voltage applied by the voltage source 1 10 (or alternatively by the ESD pulse 1 12) exceeds the characteristic voltage of the VSD material 140, the VSD material 140 switches and becomes substantially conductive, and a significant amount of current is conducted between the electrodes 120 and 122 through the VSD material 140.

[0080] In the embodiment of FIG. 1, the VSD material 140 can be said to switch in a "horizontal" direction or "lateral" direction. This horizontal or lateral direction is defined relative to the substrate 160, because the flow of electric current through the VSD material 140 takes place between via 130 and via 132, predominantly in a direction substantially parallel with the main plane of the substrate 160. In one embodiment, the substrate 160 is a layer in a PCB, in which case horizontal switching means that the flow of electric current through the VSD material 140 takes place predominantly in a direction substantially parallel with the main surface of the PCB to which most of the components and electrical elements are mounted (or surfaces, in the case of a PCB for which components are attached on both sides).

[0081] In various embodiments, the VSD material 140 is designed to accommodate flow of electrical

current in both directions between the electrodes 120 and 122, depending on the polarity of the voltage applied between the electrodes 120 and 122. In the embodiment of FIG. 1, the horizontal switching direction of the VSD material 140 is indicated by arrows 142. Because the substrate 160 (e.g., a PCB or a PCB core) is actually a three dimensional structure, with a larger 2D plane (i.e., the plane defined by the surface or surfaces of a PCB to which components are attached) and a smaller height dimension, the horizontal flow of current between electrodes 120 and 122 could be taking place in any direction that is substantially parallel with the larger 2D plane. Alternatively stated, while the embodiment of FIG. 1 appears to indicate that horizontal switching implies a left-to-right or right-to-left flow of current, in reality, considering the 3D dimensions of an actual substrate, such as a device packaging or PCB, the flow of current could take place in any direction that is substantially parallel with a 2D plane formed by the main surfaces of the substrate 160.

[0082] With reference to the embodiment of FIG. 3, horizontal switching means that current would flow in any direction that is substantially parallel with the X-Y plane shown in FIG. 3. Realizing that flow of current through a medium generally involves a 3D flow of charges, horizontal switching does not imply that all charges must flow only in a strict horizontal and planar direction. Instead, references to horizontal switching or to switching that occurs in a horizontal direction imply that the movement of charges is predominantly taking place along a plane that is substantially parallel with the main 2D plane of the substrate, but it is certainly possible and expected that at least a portion of the current flow would exhibit a certain amount of vertical movement. The vertical movement of charges may be easier to detect if a simulation or analysis were performed at a micro-level. Nevertheless, in general, horizontal switching means that at least two conductive structures, such as vias 130 and 132, are disposed in a substantially vertical dimension relative to the substrate, and that current flow occurs between the two vias predominantly in a direction substantially parallel with the main 2D plane of the substrate.

[0083] In the embodiment of FIG. 1, the distance between electrodes 120 and 122 defines a gap of VSD material 140. This gap is denoted as gap 150 in FIG. 1 and has a thickness T. In general, the horizontal gap for a horizontal switching VSDM formation is determined by the shortest electrical path across a structure of VSD material, and in FIG. 1 , this shortest electrical path is determined by the edges of the electrodes 120 and 122 at the interface with the VSD material 132. If in an embodiment the electrodes 120 and 122 do not extend towards each other such the gap 150 shown in FIG. 1 is smaller than the distance between the vias 130 and 132, the VSD material 140 could instead switch in the horizontal gap between the vias 130 and 132.

[0084] For commercial implementations, T may take a range of values, depending on the formulation of the VSD material 140, and depending on the characteristic voltage and other physical or operational properties desired for the VSD material 140. Specific exemplary values for the thickness T that could be considered for implementation in manufacturing processes include 4 mils, 3 mils, 2 mils, 1.5 mils, 1 mil, 0.5 mils, 0.2 mils, and smaller. In general, smaller values for T are expected to provide lower characteristic voltages for the VSDM structure 140.

[0085] In one embodiment, the characteristic field of VSD material 140 is defined in Volts/mil. In that embodiment, by defining a specific gap size for gap 150, the characteristic voltage for the structure of VSD material 140 disposed between via 130 and via 132 can then be determined in actual Volts.

[0086] In one embodiment, the structure shown in the embodiment of FIG. 1 includes a rectangular

structure (e.g., the layer of VSD material 140 may be built as a rectangular structure). In one embodiment, the structure shown in the embodiment of FIG. 1 includes a curved structure (e.g., the layer of VSD material 140 may be built as a curved or substantially -cylindrical formation).

[0087] FIG. 2 shows a horizontal switching VSDM formation 200 comprising VSD material 240 disposed between two conductive planes (e.g., copper planes), denoted conductive plane 230 and conductive plane 232, which may be used for ESD protection of electronic components, in accordance with an embodiment. The VSDM structure 200 is generally equivalent with the structure 100 from the embodiment of FIG. 1, but illustrates how various aspects show in FIG. 1 could be implemented in a curved architecture. The conductive plane 230 and conductive plane 232 are substantially concentric conductive structures separated by a volume of VSD material, in accordance with one embodiment. For simplicity, the substrate and electrodes are not shown in the embodiment of FIG. 2.

[0088] In one embodiment, the structure 200 shown in FIG. 2 represents a cross sectional view of a structure implemented in a PCB. With reference to the embodiment of FIG. 3, the annulus shown in FIG. 2 between the conductive planes 230 and 232 would be disposed substantially parallel with the X-Y plane shown in FIG. 3. In a 3D perspective, the conductive planes 230 and 232 extend in a vertical direction, which for a PCB would be substantially parallel with the Z-axis shown in the embodiment of FIG. 3.

[0089] In the embodiment of FIG 2, a voltage source 210 or an ESD signal 212 could produce a voltage between the conductive planes230 and 232. If this voltage exceeds the characteristic voltage of the VSD material 240, the VSD material would switch on, and the VSD material would change from being substantially nonconductive to becoming substantially conductive. In that case, significant current would flow between the conductive planes230 and 232. For a concentric structure as shown in FIG. 2, the current flow would take place predominantly in a radial direction illustrated by the lines 242. With reference to the embodiment of FIG. 3, horizontal switching for the structure shown in FIG. 2 means that current would flow between the conductive planes 230 and 232 predominantly along a plane that is substantially parallel with the X-Y plane shown in FIG. 3. Again, as discussed in connection with the embodiment of FIG. 1, horizontal switching does not mean that current would be strictly limited to flows along planes substantially parallel with the main 2D dimension of a substrate. Instead, it is expected that given the 3D aspects of the vias, VSDM structures, and micro- level effects, a certain amount of current flow would occur in a vertical dimension. Nevertheless, horizontal switching means that current flow would indeed take place predominantly in a direction parallel with the main 2D plane of a substrate, such that useful electrical functionality may be achieved using current flowing in a horizontal direction through the VSD material 240.

[0090] In one embodiment, the characteristic field of VSD material 240 is defined in Volts/mil. In that embodiment, by defining a specific gap size for gap 250, the characteristic voltage for the structure of VSD material 240 disposed between vias 230 and 232 can then be determined in actual Volts. In one embodiment, the characteristic voltage of the VSD material 250 is correlated with the size of the gap 250, and can be determined with a degree of certainty as a value in Volts.

[0091] The size of the gap 250 is denoted as T in the embodiment of FIG. 2. For commercial

implementations, T may take a range of values, depending on the formulation of the VSD material 240, and depending on the characteristic voltage and other physical or operational properties desired for the VSD material 240. Specific exemplary values for the thickness T that could be considered for implementation in manufacturing processes include 4 mils, 3 mils, 2 mils, 1.5 mils, 1 mil, 0.5 mils, 0.2 mils, and smaller. In general, smaller values for T are expected to provide lower characteristic voltages for the VSDM structure 140.

[0092] FIG. 3 illustrates a PCB and associated directional references used in connection with various

embodiments. The PCB 300 shown in FIG. 3 has a main horizontal plane defined by the X and Y axes, and a vertical dimension defined by the Z-axis. This reference coordinate system is defined independently of the actual orientation of the PCB in the physical space, such that rotation of the PCB in space does not change the horizontal plane and vertical dimension conventions defined here. This reference system may be discussed in more detail in this patent with respect to a PCB, such as the PCB 300 shown in FIG. 3, but applies analogously to any other substrate.

[0093] In general, a "substrate device" that may be protected by a VSDM formation against ESD or other overvoltage events, or into which a VSDM formation may be incorporated, means any solid medium to which a substance or structure is applied or otherwise attached. For simplicity, a substrate device may sometimes be denoted a "substrate."

[0094] In some embodiments, the term substrate may refer to a slice of semiconductor material such as silicon, metal oxide or gallium arsenide ( GaAs ) that serves as the foundation for the construction of components such as transistors and integrated circuits (IC s). In the manufacture of an IC, the substrate material is cut or formed into wafers, on which the individual electronic components are etched, deposited or fabricated.

[0095] In some embodiments, the term substrate may refer to a first (1st) level package. A first level

package may comprise one or more materials, disposed in one or more layers. Examples of materials that may be included in a first level package include any metal, ceramic, glass, silicon, polymeric material (e.g., FR4, FR5, BT), or any combination of the foregoing. A first level package may also comprise electronic circuitry that serves as the foundation for connecting single or multiple integrated circuits (e.g., examples of such multiple integrated circuits include a die, chip or device) using an interconnecting material. Examples of such interconnecting materials include solder, metal plating, wire or tab bonding, or other interconnection materials. An interconnecting material may adhere to a metal pad patterned onto the substrate which connects the integrated circuits to the substrate. In such configurations, the interconnection between an integrated circuit and the substrate is referred to as first (1st) level interconnect, and the substrate is then commonly referred to as 1st level package, or 1st level interconnect package, or 1st level substrate package. A first level package can also be referred to as a printed wiring board (PWB) or printed circuit board (PCB). A 1st level interconnect package, in various applications, may have metal pads patterned on the top side or bottom side which are used to interconnect the 1st level package to a second (2nd) level package.

[0096] In some embodiments, the term substrate may refer to a second (2nd) level package. A second level package may have the same structure, architecture and functionality as described above for a first level package, but is disposed as a different layer in a multi-layer stack that also includes a first layer package.

[0097] In various embodiments, examples of substrates may include a PCB, any single layer or set of

multiple layers of a PCB, the package of a semiconductor device (e.g., ball grid array (BGA), a land grid array (LGA), a pin grid array), an LED substrate, an integrated circuit (IC) substrate, an interposer or any other platform that connects two or more electronic components, devices or substrates (where such connection may be vertical and/or horizontal), any other stacked packaging or die format (e.g., an interposer, a wafer-level package, a package-in-package, a system-in-package, or any other stacked combination of at least two packages, dies or substrates), or any other substrate to which a VSDM formation can be attached or within which a VSDM formation may be incorporated.

[0098] Using this reference coordinate system, the horizontal switching direction defined by the lines 142 in the embodiment FIG. 2 and by the lines 242 in the embodiment of FIG. 3 would be preponderantly along a plane that is substantially parallel with the main 2D plane of the PCB 300, which is defined by the X-Y plane shown in FIG. 3.

[0099] 3. Exemplary Vertical Switching VSDM Formations.

[00100] FIG. 4A shows a vertical switching VSDM formation 400 that is adapted to achieve vertical

switching using VSD material and that may be integrated in a substrate device, such as a PCB, a flexible circuit, or the packaging of a semiconductor chip, in accordance with an embodiment. A VSDM formation stackup adapted to perform vertical switching, which comprises multiple layers (including at least one layer of VSD material and/or at least one VSDM structure), may sometimes be referred to as a "vertical switching VSD material formation," or "vertical switching VSDM formation." The vertical switching VSDM formation 400 may be a cross sectional view showing various layers within a PCB, of a semiconductor package, or of another substrate device.

[00101] Certain vertical switching VSDM formations were disclosed in United States patent application 12/417,589, filed on April 2, 2009 by Shocking Technologies, Inc., and in United States patent application 61/537,490, filed on September 21, 201 1 by Shocking Technologies, Inc. The

12/417,589 and 61/537,490 applications are each incorporated herein by reference in their entirety.

[00102] The formation 400 shown in FIG. 4A comprises two substrate layers 460 and 462, which are

insulating layers incorporated in the PCB, a layer of VSD material 440, a conductive structure 430, and a conductive layer 432.

[00103] The conductive structure 430 may be a via (e.g., a laser drilled via), a pad, a trace, or any other structure that is designed to be conductive and to facilitate propagation of electric signals.

[00104] The conductive layer 432 may be a signal layer or a ground layer integrated in a PCB. In one embodiment, the conductive layer 432 is a conductive substrate on which the VSD material 440 was initially disposed (e.g., a copper foil on which the VSD material 440 was coated and cured).

[00105] The VSDM formation 400 shown in FIG. 4A is disposed along the vertical dimension of a PCB, as indicated by the Z axis. With reference to the embodiment of FIG. 3, the Z axis shown in FIG. 4A is the same as the Z-axis shown in FIG. 3.

[00106] By analogy to the discussion of horizontal switching in connection with the embodiments of FIG. 1 and FIG. 2, vertical switching means that flow of current takes place in a direction substantially parallel with the vertical direction of a substrate.

[00107] With reference to the embodiment of FIG. 3, vertical switching for the structure shown in the embodiment of FIG. 4A means that if the VSD material 440 is switched on to become substantially conductive in response to a voltage that exceeds its characteristic voltage, current would flow between conductive structure 430 and the conductive layer 432 predominantly in a direction that is substantially parallel with the Z-axis shown in FIG. 3. Again, as discussed in connection with the embodiments of FIG. 1 and FIG 2 with respect to horizontal switching, vertical switching does not mean that current would be strictly limited to flows in a direction substantially parallel with the Z- axis (or vertical axis) of a substrate. Instead, it is expected that given the 3D physical aspects of conductors, 3D structure of PCB layouts, 3D physical characteristics and shape of the VSDM structure, and micro-level effects within the VSD material itself (e.g., current propagation within and/or between particles dispersed within the VSD material), a certain amount of current flow could occur in a horizontal dimension, at least in localized volumes within the VSD material.

Nevertheless, vertical switching means that current flow would take place predominantly in a direction substantially parallel with the Z-axis (or vertical axis) of a PCB board or other substrate, such that useful electrical functionality may be achieved using current flowing in a vertical direction through the VSD material 440. [00108] In one implementation, the VSDM formation 400 further comprises a layered interconnect 434, which is disposed in contact with the conductive structure 430 and the VSD material 440. The layered interconnect 434 is a conductive feature that may be added in various embodiments to increase the cross-sectional conduction area at a boundary between conductive structures and VSDM formations, such as the boundary between the conductive structure 430 and the VSD material 440 shown in FIG. 4A. Addition of a layered interconnect at such a boundary may enhance the capacity of the respective conductive structures to carry higher currents, especially if the boundary has small physical features that may otherwise result in concentration of currents or electrical fields. This may be more desirable, for example, if the conductive structure 430has a smaller cross-sectional area at the point where it contacts the VSD material 440.

[00109] In general, a layered interconnect disposed between a conductive feature and a structure of VSD material, such as the layered interconnect 434 shown in FIG. 4A, may provide enhanced current flow between the conductive structure and the VSD material, improved mechanical properties for the interface between the conductive structure and the VSD material (e.g., increased adhesion or bonding, better thermal coefficient matching, etc.), improved electrical connection between the conductive structure and the VSD material, and other similar advantages.

[00110] In various embodiments, the layered interconnect 434 may be disposed to fully or partially separate the conductive structure 430 from the VSD material 440, or may be disposed at another boundary of the conductive structure 430 to provide an additional electrical path between the conductive structure 430 and the VSD material 440 (e.g., vertically).

[00111] In one embodiment, the layered interconnect 434 physically separates the conductive structure 430 and the VSD material 440. To manufacture such an embodiment, the layered interconnect 434 could be formed on top of the VSD material 440, and the conductive structure 430 could then be formed above the layered interconnect 434, avoiding the complete penetration of the layered interconnect 434 by the conductive structure 430.

[00112] In one embodiment, the layered interconnect 434 is in physical contact with the VSD material 440, and the layered interconnect 434 encapsulates a portion of the conductive structure 430 at the interface with the VSD material 440. To manufacture such an embodiment, the layered interconnect 434 could be formed on top of the VSD material 440, and the conductive structure 430 could then be formed above the layered interconnect 434, penetrating the layered interconnect 434 to establish direct physical contact between the conductive structure 430 and the VSD material 440 (e.g., by laser drilling a hole through the layered interconnect 434 all the way to the VSD material 440 and then filling that hole up with conductive material to produce a conductive via).

[00113] FIG. 4B shows a VSDM formation 490 comprising a VSD material layer 498 that may be

integrated in a PCB or in another substrate and is adapted to achieve vertical switching, in accordance with an embodiment. In one embodiment, the VSDM formation VSDM formation 490 shown in FIG. 4B includes the structural components of structure 430 shown in FIG. 4A and a number of additional features and layers.

[00114] The VSDM formation 490 shown in FIG. 4B comprises a number of substrate layers that are

generally insulative (or dielectric), illustrated as pre-preg filler 480, core 482, pre-preg filler 484, core 486, and pre-preg filler 488.

[00115] The VSDM formation 490 shown in FIG. 4B also comprises a number of conductive signal layers, denoted as conductive layers LI through L6, and numbered as conductive layers 470, 472, 474, 476,

478, and 479. These signal layers may conduct electrical signals within the PCB board, or to or from components and circuit elements attached to the PCB, or may act as ground or other voltage reference points.

[00116] The VSDM formation 490 shown in FIG. 4B also comprises two conductive structures, denoted as conductive structures 450 and 452. Either or both of the conductive structures 450 and 452 may be a via, a pad, a trace, or any other structure that is designed to be conductive and to facilitate propagation of electric signals. The VSDM formation 490 shown in FIG. 4B is disposed along the vertical dimension of a PCB, as indicated by the Z axis. With reference to the embodiment of FIG. 3, the Z axis shown in FIG. 4A is the same as the Z-axis shown in FIG. 3.

[00117] In the embodiment of FIG. 4B, a layered interconnect 499 is disposed at the interface between the conductive structure 452 and the VSD material 498. In various implementations, the layered interconnect 499 may be similar to the layered interconnect 434 from the embodiment of FIG. 4A. The layered interconnect 499 may provide various advantages for the interface between the conductive structure 452 and the VSD material 498, including those discussed in connection with the layered interconnect 434 from the embodiment of FIG. 4A.

[00118] If the VSD material layer 498 is exposed to a voltage between the conductive structure 452 and conductive layer 474 that exceeds its characteristic voltage, the VSD material comprised in the VSD material layer 498 will switch on, and will become substantially conductive. In that case, current would flow predominantly in a vertical direction, between the conductive structure 452 and conductive layer 474. If this happens, the VSD material layer 498 has switched vertically.

[00119] In one embodiment, analogously with the discussion provided in connection with the embodiments of FIG. 1 and FIG. 2, the characteristic voltage of the VSD material layer 498 when measured in Volts is correlated with the gap size of the VSD material. For the embodiment of FIG. 4B, this gap size would be substantially equal to the distance between the conductive structure 452 and the conductive layer 474, which also happens to be substantially the thickness of the VSD material layer 498. While the exact formula that relates gap size to characteristic voltage for a VSD material may vary depending on a number of variables (e.g., the exact VSD material formulation, the complete volume of the VSDM structure or layer, the actual shape of the VSDM structure through which switching is achieved, the impedance of any circuit elements that are connected to the VSD material, etc.), for VSD material formulations used in various embodiments a smaller gap of VSD material generally results in a smaller characteristic voltage. Smaller characteristic voltages may be preferable for certain applications (e.g., for applications where the VSD material would be expected to switch in response to lower voltages).

[00120] As a general design consideration, however, reducing the size of the gap of a VSD material must balance the risk that the VSDM structure becomes too small, and consequently loses some or all of its desirable operating characteristics (e.g., a VSDM structure that is too thin may exhibit decreased repeatability consistency when exposed to similar trigger voltages in rapid succession, may experience decreased capacity to dissipate heat, or may be subject to a higher risk of shorting or burnout).

[00121] The decision on whether to implement a horizontal switching VSDM formation or a vertical switching VSDM formation in any particular application depends on a number of design, manufacturing and application considerations.

[00122] For example, to achieve a particular characteristic voltage for a VSDM structure, the particular design and dimensions under consideration may suggest whether the appropriate switching gap size can be achieved more conveniently using a vertical switching or a horizontal switching VSDM formation.

[00123] Manufacturing considerations may also impact the decision. For example, in certain

manufacturing environments, it may be easier to control gap sizes for vertical switching formations (e.g., the thickness of a coating of VSD material disposed as a horizontal layer within a substrate may be accurately controlled by employing advanced coating technology coupled with adequate inspection, metrology and monitoring processes) compared to horizontal switching formations (e.g., gap 150 from the embodiment of FIG. 1 and gap 250 from the embodiment of FIG. 2). From a manufacturing perspective, one selection criterion could be to assess which of the horizontal and vertical formations would provide lower statistical variations in characteristic voltages and/or operational robustness across the same substrate and/or across multiple substrates.

[00124] From an application perspective, horizontal switching and vertical switching VSDM formations may be compared to assess which technology could result in better device performance, enhanced ESD protection, improved vertical and/or horizontal utilization of substrate space, device components and/or substrate routing resources, enhanced device reliability, and other similar improved device metrics.

[00125] Another criterion that could be used when selecting between vertical switching and horizontal switching VSDM formations is the ability to conduct larger amounts of power. For example, in some embodiments, a vertical switching VSDM formation may be produced with a larger cross- sectional area across which current flows when the VSD material becomes substantially conductive. A larger cross-sectional area will normally be able to carry higher currents, therefore resulting in better performance characteristics and endurance for the respective VSDM structure. For example, the cross-sectional switching area of the VSD material 140 from the embodiment of FIG. 1 is proportional with the thickness of the VSD material layer measured in the vertical direction, which may be smaller. In contrast, the cross-sectional switching area of the VSD material 540 from the embodiment of FIG. 5 is proportional with the surface area of the electrode 520 and/or 524 as determined in the X-Y plane, which will tend to produce a comparatively larger cross-sectional area.

[00126] To dispose a layer of VSD material on a substrate, such as the VSD material 140 on the substrate 160 in the embodiment of FIG 1 or the VSD material 440 on the conductive layer 432 in the embodiment of FIG 4A, the VSD material may be coated and cured on the substrate. As an example, with reference to the embodiment of FIG. 4A, to dispose a layer of the VSD material 440 on the conductive layer 432, the VSD material may be coated and cured on a conductive sheet of material (e.g., copper), and then the resulting cured VSDM formation could in introduced as a compound layer within a PCB, with the conductive sheet of material becoming conductive layer 432 and the layer of VSD material becoming the VSD material 440. The rest of the features shown in FIG. 4A may be formed through various manufacturing steps during the manufacturing process.

[00127] Unless otherwise expressly indicated, the terms "VSD material formation," "VSDM formation," "formation of VSD material," "formation of VSDM," "VSD material stackup," or "VSDM stackup" are intended to refer to any combination, arrangement or other structure that includes (a) at least one VSDM structure, and (b) one or more of the following: (i) an insulative element (e.g., a pre-preg or other insulative layer or structure in a PCB, an insulative layer or structure in a semiconductor package, etc.), (ii) an electrode (e.g., a conductive via in a PCB or a conductive connector in a semiconductor package), (iii) a semiconductor element (e.g., a structure build out of a semiconductor material, and/or (iv) a different VSDM structure. An example of a VSDM formation in a simpler configuration is the combination of (a) a VSDM structure (e.g., a layer of VSD material) disposed on a copper foil, and (b) the foil itself.

[00128] Other examples of VSDM formations in more complex configurations are the horizontal and

vertical switching VSDM formations disclosed in this patent in connection with various

embodiments, including the horizontal switching VSDM formation 100 of the embodiment of FIG. 1, the horizontal switching VSDM formation 200 of the embodiment of FIG. 2, the VSDM formation 400 of the embodiment of FIG. 4A, the VSDM formation 490 of the embodiment of FIG. 4B, and the VSDM formation 500 of the embodiment of FIG. 5.

[00129] Coating and curing a VSDM structure on a substrate (e.g., coating and curing a layer of VSD

material on a copper foil), may be achieved through a sequence of steps. For example, to dispose the VSD material 140 from the embodiment of FIG. 1 on a conductive sheet that can eventually become the substrate 160, or to dispose the VSD material 440 from the embodiment of FIG. 4A on a conductive sheet that can eventually become the conductive layer 432, a sequence of steps such as the following steps may be used:

[00130] (1) dispense the VSD material onto the substrate while the VSD material is in a liquid or semi-liquid state (e.g., because of the particles and higher molecular weight materials mixed within the VSD material, the viscosity of the VSD material would tend to be higher than the viscosity of a purer low molecular weight liquid such as water, and would therefore tend to flow slower);

[00131] (2) spread the VSD material in a layer on the substrate while maintaining the thickness of the

VSD material within desired ranges and tolerances across the surface of the substrate;

[00132] (3) monitor, inspect and/or test the thickness of the layer of the VSD material across larger surfaces of the coated substrate to ensure that the thickness of the VSD material is indeed maintained within desired ranges and tolerances;

[00133] (4) cure the VSD material by exposing it to heat (e.g., by running the VSD material coated on the substrate through an oven where the temperature is controlled and/or varied within appropriate ranges);

[00134] (5) remove solvent or other materials to the extent such solvent or other materials may have been used in earlier manufacturing steps and are designed to be removed at this time to facilitate subsequent processing; and

[00135] (6) monitor, inspect and/or test the resulting VSDM formation comprising the cured layer of

VSD material disposed on the substrate to ensure that the cured layer of VSD material exhibits expected characteristics and tolerances in terms of thickness, consistency, defect density, switching voltage, physical resiliency, adhesion, flexibility or other physical attributes, thermal endurance or other thermal attributes, and/or other relevant parameters.

[00136] In addition to coating, other methods could be used to dispose on a substrate a VSDM structure, such as a layer of VSD material. Such other methods include deposition, screen printing, die coating, comma coating, lamination, mechanical adhesion (e.g., by pre-curing the VSD material in a layer and then attaching it to the substrate), or through any other bonding approach, whether mechanical, chemical, or otherwise. Regardless of the approach used, the resulting VSDM formation would comprise a layer of VSD material disposed on top of a substrate (whether conductive or not), with the VSD material in a cured state and capable of performing its voltage switching function.

[00137] In one embodiment, instead of producing a VSDM formation comprising a layer of VSD material cured on a substrate ahead of time and then integrating the VSDM formation into a PCB, the VSD material may be coated onto a layer of the PCB during the actual manufacturing process of a PCB. With reference to FIG. 4B, for example, the conductive layer L3 474 may be attached to the pre-preg filler 484 during the manufacturing of the VSDM formation 490, and then a layer of VSD material 498 may be disposed and cured on the conductive layer L3 474. The layered interconnect 434 may then be formed (e.g., screen printed) on top of the VSD material 498. The core 482 may then be attached to the layer of VSD material 498, with the conductive structure 452 being subsequently formed within the core 482 or having been already produced within the core 482 before attachment.

[00138] 4. Switching VSDM Formations and Embedded Circuit Elements.

[00139] FIG. 5 shows a VSDM formation 500 that may be used for ESD protection of electronic

components in connection with an embedded circuit element having a non-negligible impedance, in accordance with an embodiment. As further discussed below with respect to various embodiments, both horizontal switching VSDM formations and vertical switching VSDM formations may operate in connection with embedded circuit elements to provide ESD protection.

[00140] The switching VSDM formation 500 shown in the embodiment of FIG. 5 is a vertical switching VSDM formation may be integrated in any electronic device that includes a substrate device to provide protection against ESD and other overvoltage events. Examples of substrate devices in which the VSDM formation 500 may be integrated in various embodiments include a PCB and the packaging of a semiconductor chip. FIG. 5 shows a cross section of the VSDM formation in a vertical direction of a substrate device.

[00141] The vertical switching VSDM formation 500 of FIG. 5 comprises a layer of VSD material 540, with a vertical thickness T across gap 542. In various embodiments, multiple layers of VSD material may be utilized. For commercial implementations, T may take a range of values, depending on the formulation of the VSD material 540, and depending on the characteristic voltage and other physical or operational properties desired for the VSD material 540. Specific exemplary values for the thickness T that could be considered for implementation in manufacturing processes include 2 mils, 1.5 mils, 1 mil, 0.5 mils, 0.2 mils, and smaller. In general, smaller values for T may be expected to provide lower characteristic voltages for the VSDM structure 540.

[00142] The VSDM formation 500 of FIG. 5 comprises a set of electrodes 520 and 524, which are disposed in contact with the VSD material layer 540. A conductive layer 570 is disposed adjacent to a pre- preg layer 530. The pre-preg layer 530 is disposed between the conductive layer 570 and the layer of VSD material 540. A layered interconnect 580 is disposed in contact with the layer of VSD material 540. In one embodiment, the layered interconnect 580 is formed within the pre-preg layer 530, as shown in FIG. 5. In one embodiment, the layered interconnect 580 may be disposed as a distinct layer (i.e., not formed within the pre-preg layer 530) that separates the pre-preg layer 530 from the VSD material 540. The pre-preg layer 530 could be a layer in a substrate device, such as a PCB, a flexible circuit, or the packaging of a semiconductor device.

[00143] In various embodiments, a "layered interconnect" is any conductive structure that may be used as part of, or in connection with a switching VSDM formation to transmit voltage and/or current along an electrical path that includes one or more VSDM structures. In some embodiments, a layered interconnect is disposed to provide conduction in a horizontal direction (e.g., within a horizontal layer). In some embodiments, a layered interconnect is disposed to provide conduction in a vertical direction (e.g., across one or more horizontal layers, and/or between two or more horizontal layers). In some embodiments, a layered interconnect is disposed to provide conduction both horizontally and vertically, and/or obliquely.

[00144] In various implementations, layered interconnects, such as layered interconnect 580 532 from FIG.

5, may be produced using any suitable process, including through screen printing, stencil printing, deposition, adhesion, lamination using heat and/or pressure, through any other physical attachment (e.g., gluing or bonding), or by pre-building the layered interconnect into a substrate (e.g., disposing the layered interconnect as a layer, structure, conductive core or pre-preg within a PCB or as a layer or conductive structure within a semiconductor package). In one embodiment, the substrate attached to a layer of VSD material (e.g. the copper foil used as a substrate for a layer of VSD material) may act as a layered interconnect to provide horizontal conductivity within a PCB or other substrate. In general, a layered interconnect suitable for use in connection with various horizontal or vertical switching VSDM formation embodiments may be produced through any mechanical, chemical, or other suitable deposition processes.

[00145] In various embodiments, layered interconnects may have a range of impedances. For example, in some implementations, it may be desirable to have a layered interconnect with negligible impedance (e.g., a highly conductive film that has very low resistance and does not introduce any significant voltage drop). As another example a layered interconnect may be intentionally constructed to have a higher impedance and introduce a specific voltage drop when current flows through it (e.g., a layer interconnect may be designed to be an embedded circuit element, or may include an embedded circuit element). An example of a layered interconnect with a resistance that would normally not be considered negligible would be a conductive film with a resistance between 25 and 1000 Ohms. In one embodiment, a layered interconnect may be constructed to be, or may be modeled to operate as an embedded component in an electronic device or substrate device, such as the embedded impedance 596 from the embodiment of FIG. 5.

[00146] A layered interconnect that has a non-negligible electrical resistivity may be manufactured in

connection with various embodiments using a carbon filled epoxy, or as a nickel-chromium alloy deposited on copper (e.g., a thin film resistive layer thermally deposited on copper foil).

[00147] In various embodiments, a layered interconnect may be manufactured out of a material or

combination of materials with a high dielectric constant, which would provide the layered interconnect with a higher capacitance.

[00148] In various embodiments, a layered interconnect may be made out of any material or combination of materials that can conduct current and that is fit for use in connection with a substrate application. [00149] An example of a material that may be used to make a layered interconnect in connection with present embodimens is a Z-axis conductive tape manufactured by 3M Corporation and marketed under the trade name "3M™ Z-Axis Electrically Conductive Tape 9703." When disposed as a substantially horizontal layer, a Z-axis conductive tape exhibits anisotropic vertical conductivity along the Z-axis such that it is substantially conductive when propagating current along the Z-axis, but substantially insulative horizontally.

[00150] Other examples of materials that may be used to make a layered interconnect in connection with present embodiments, such as layered interconnect 580, are silver paste, copper paste, nickel paste, other metallic types of paste, a silver coated copper layer, a carbon layer, a ferroic material or a compound that includes ferrites, a conductive epoxy or polymer, or any other material layer, structure or connector capable of conducting current. In general, unless a layered interconnect has anisotropic conductivity, the layered interconnect may be used in connection with vertical switching VSDM formations in various embodiments to conduct current in horizontal, vertical and/or oblique directions, depending on the particular architecture of the respective embodiment.

[00151] In various embodiments, a layered interconnect or other electrode suitable for use as part of various horizontal or vertical switching VSDM formations may be produced through electroplating using a layer of VSD material as a seed layer. A method for producing various devices, such as an LED device, by electroplating with VSD materials was described in US Patent 7,825,491 titled "Light- emitting device using voltage switchable dielectric material," which is incorporated hereby by reference in its entirety. In such embodiments, a layer of VSD material is disposed on a substrate. The layer of VSD material may be selectively covered with a pattern of a different material (e.g., a material that is substantially nonconductive). While the layer of VSD material is rendered substantially conductive by application of a voltage that exceeds the characteristic voltage of the VSD material, an ion deposition process may take place to form conductive structures (e.g., a layered interconnect such as the layered interconnect 580 from the embodiment of FIG. 5) within the exposed areas of the VSD material. Various known deposition processes may be performed to deposit ionic media into at least some of the exposed areas defined by the pattern of the exposed VSD material.

[00152] In the embodiment of FIG. 5, a via 550 crosses the pre-preg layer 530 and is in electrical contact with the layered interconnect 580, and establishes electric contact between the conductive layer 570 and the layered interconnect 580.

[00153] In the embodiment of FIG. 5, electrode 520 and electrode 524 are connected to a ground. In some embodiments, one or both electrodes could be connected to a different point in an electric circuit, including possibly to a voltage source, to a circuit element or component, or to another reference voltage potential towards which an ESD pulse or other voltage may be directed. [00154] If a voltage that exceeds the characteristic voltage of the VSDM structure 540 is applied by an ESD pulse 512 (or by a voltage source) at the conductive layer 570, the VSD material 540 becomes substantially conductive. Current flow across the VSD material 540 will take place predominantly in a vertical direction between the layered interconnect 580 and the electrode 520 and/or the electrode 524.

[00155] As a result, the VSDM formation 500 shown in the embodiment of FIG. 5 will switch vertically, with current flow taking place through the VSDM structure 540 predominantly in a direction substantially parallel with the Z-axis (or vertical axis) of the respective substrate. The general electrical path followed by current flowing through the VSDM formation 500 in response to the ESD signal 512 is shown in FIG. 5 as ESD discharge path 590.

[00156] The embodiment of FIG. 5 further shows a circuit element denoted as embedded impedance 596.

In various embodiments, this circuit element may be incorporated partially or completely within the VSDM formation 500, or may be in communication with the VSDM formation 500 (e.g., it may be embedded in the same PCB as the VSDM formation 500, or may be surface-attached to a PCB in which the VSDM formation 500 is incorporated).

[00157] In the embodiment of FIG. 5, the embedded impedance 596 is shown as a circuit element that is embedded at least partially within the VSDM formation 500. In particular, FIG. 5 shows the embedded impedance 596 as being embedded at least partially within the pre-preg layer 530. In alternative or complementary embodiments, the embedded impedance 596 may be disposed in other locations within a substrate or within the VSDM formation 500. For example, the embedded impedance 596 may be disposed within the VSDM structure 540, within another PCB layer, or within another substrate such as a semiconductor package.

[00158] In one embodiment, the embedded impedance 596 is not embedded within the VSDM formation 500, as shown in FIG. 5, but is embedded in the same substrate (e.g., same PCB) in which the VSDM formation 500 is incorporated. In one embodiment, the embedded impedance 596 and/or the electronic component 589 may be surface-attached to the same substrate in which the VSDM formation 500 is incorporated. In one embodiment, the embedded impedance 596 and/or the electronic component 598 may be incorporated in a different electronic device that is in electrical contact with the substrate in which the VSDM formation 500 is incorporated (e.g., the VSDM formation 500 may be incorporated in a connector that is attached to an electronic device that comprises the embedded impedance 596 and/or the electronic component 598). In one embodiment, the VSDM formation 500 and the embedded impedance 596 are comprised in the packaging of the electronic component 598, or are otherwise attached to or incorporated into a substrate that is in physical contact or in electrical communication with the electronic component 598.

[00159] In various embodiments, the embedded impedance 596 consists of one or more circuit elements, or comprises one or more circuit elements. In various embodiments, the embedded circuit element impedance 596 may include one or more resistors, one or more inductors, one or more capacitors, one or more ferroic circuit elements (e.g., an embedded ferroic circuit element that may or may not comprise VSD material), one or more filters (e.g., various combinations of one or more low-pass, band-pass and high-pass filters or filter stages), any other passive or active circuit elements or electronic components, any layered interconnect with a negligible impedance, any layered interconnect with a non-negligible impedance (e.g., a layer of high dielectric material), any electrode or other conductive structure with a non-negligible impedance, and/or any combination of the foregoing.

[00160] The embedded impedance 596 may be used in connection with the VSDM structure 540 to provide partial or full ESD protection for an electronic component, such as the electronic component 598 shown in FIG. 5. In FIG. 5, the electronic component 598 is shown as connected to the embedded impedance through an electrode 528. The embedded impedance 596 is also in electrical contact with the conductive layer 570. In the absence of the VSD material 540, an ESD pulse or other large voltage that is applied at the conductive layer 570 would result in propagation of a large voltage and/or current through the embedded impedance 596 to the electronic component 598. In the presence of the VSD material 540, however, the VSDM formation 500 switches on in response to a large voltage that exceeds the characteristic voltage of the VSDM structure 540, and then diverts to ground through the electrode 520 and/or electrode 524 at least part of the ESD pulse that would have otherwise reached the electronic component 598. Consequently, the vertical switching structure 500 employs the embedded impedance 596 to protect the electronic component 598 from a potentially damaging ESD pulse or other overvoltage event present at the conductive layer 570.

[00161] In various embodiments, a horizontal switching VSDM formation, such as the VSDM formation 100 of FIG. 1 or the VSDM formation 200 of FIG. 2, may similarly be employed to provide ESD protection to an electronic component or electronic device using an embedded circuit element, such as embedded impedance 596. For example, for the horizontal switching VSDM formation 100 from the embodiment of FIG. 1, an embedded circuit element such as embedded impedance 596 may be disposed between the electrode 120 and an electronic component to be protected against ESD events generated by the ESD pulse 1 12 (e.g., the embedded circuit element may be disposed within the insulating layer 170 of FIG. 1, in electrical contact with the electrode 120).

[00162] The architecture and operation of an electric circuit that may be used in connection with the VSDM structure 540 as part of the vertically switching structure 500 to provide partial or full ESD protection for an electronic component, such as the electronic component 598 shown in FIG. 5, is disclosed in detail in US. Application Serial No. 13/096,860, filed April 28, 201 1, and titled "Embedded Protection Against Spurious Electrical Events," which is hereby incorporated by reference in its entirety. Horizontal and vertical switching VSDM structures as disclosed and/or claimed in this patent may be used in connection with the embodiments disclosed and/or claimed in the US. Application Serial No. 13/096,860 to provide enhanced protection against ESD and other overvoltage events for electronic components.

[00163] In various embodiments, the electronic component 598 may be any one or more of the following: a semiconductor chip or another integrated circuit (IC) (e.g., a microprocessor, controller, memory chip, RF circuit, baseband processor, a system on a chip (SOC), a flip chip, etc.), a light emitting diode (LED), an LED array, an LCD, LED, OLED or any other type of display, a MEMS chip or structure, or any other component or circuit element that is incorporated in an electronic device or is used to display information generated by an electronic device.

[00164] In one embodiment, the embedded impedance 596 may be implemented using a ferroic circuit element that includes a conductive structure embedded at least partially within a ferroic material. A ferroic circuit element comprising ferroic VSD material and suitable for such embedded

implementations was disclosed in United States patent application 13/115,068, filed on May 24, 2011, which is incorporated herein in its entirety by reference. In various embodiments, the embedded impedance 596 may be implemented as an embedded ferroic inductor, embedded ferroic VSD material inductor, embedded ferroic capacitor, embedded ferroic VSD material capacitor, or as any other embedded ferroic circuit element or embedded ferroic VSD material circuit element.

[00165] In one embodiment, a VSDM formation is adapted to achieve both vertical and horizontal

switching using VSD material. A VSDM formation that is adapted to perform both vertical and horizontal switching using VSD material is denoted a "bidirectional switching VSDM formation" or a "dual switching VSDM formation." To achieve such dual switching functionality, a VSDM formation may incorporate one or more horizontal gaps and one or more vertical gaps, and the switching could take place across a horizontal or vertical gap depending on the geometry of the VSDM formation, characteristics of the VSD material, and location where the ESD pulse is applied. In various embodiments, a dual switching VSDM formation may operate as a horizontal switching VSDM formation, vertical switching VSDM formation, and/or dual switching VSDM formation. In various embodiments, a dual switching VSDM formation may be produced by defining in a horizontal switching VSDM formation a vertical gap across which vertical switching may take place, or by defining in a vertical switching VSDM formation a horizontal gap across which horizontal switching may take place.

[00166] For example, the VSDM formation from the embodiment of FIG. 5 has been described as a vertical switching VSDM formation, where the switching takes place across gap 542 between the layered interconnect 580 and electrode 520 and/or electrode 524. In an alternative embodiment, if the distance between the electrodes 520 and 524 is small enough, a horizontal gap would be defined between the electrodes 520 and 524, and horizontal switching could take place across this horizontal gap. For example, if electrode 524 is kept grounded, if the gap between electrodes 520 and 524 is sufficiently small (e.g., 4 mils, 3 mils, 2 mils, 1.5 mils, 1 mil, 0.5 mils, 0.2 mils, or smaller), and if an ESD pulse is applied to electrode 520, the VSD material 540 would switch horizontally across the horizontal gap formed by the electrodes 520 and 524. In that configuration, the VSDM structure 500 from the embodiment of FIG. 5 could be implemented as a dual switching VSDM formation.

[00167] Further details about the architecture and operation of dual switching VSDM formations were discussed in United States patent application 61/537,490, filed on September 21, 201 1 by Shocking Technologies, Inc.

[00168] For convenience, the term "switching VSDM formation" may be used to encompass all types of VSDM formations that employ VSD materials for ESD protection through an electrical switching mechanism, including horizontal switching VSDM formations, vertical switching VSDM formations, and dual switching VSDM formations.

[00169] 5. Overview of Electrical Response of Switching VSDM Formations.

[00170] FIG. 6 shows a graph 600 with sample response voltage envelopes for a vertical switching VSDM formation, such as the VSDM formation 500 sown in FIG. 5. Response voltage envelopes for other switching VSDM formations, including for horizontal VSDM formations, may exhibit variations in shape and magnitude compared to the ones shown in graph 600, but will generally follow the principle that by switching on, a properly designed and implemented VSDM formation will suppress an input ESD signal by generating an attenuated response signal.

[00171] The voltage response curves 620 shown in FIG. 6 were obtained by measuring the voltage across a VSDM structure disposed as a layer with a vertical gap of 2 mils while repeatedly applying an input voltage in the form of a transmission line pulse ("TLP"). For example, in the embodiment of FIG. 5, this measurement could be achieved by measuring the voltage at the conductive layer 570 relative to the electrode 520 and/or electrode 524, with the ESD pulse 512 being produced by a TLP.

[00172] In one embodiment, the measurement of the response voltage of a VSDM formation in response to a TLP may be processed using a TLP generator and an oscilloscope as follows:

[00173] (1) a TLP generator sends a pulse down a coaxial cable transmission line towards an

electrode of the VSDM formation, which has a gap with a corresponding characteristic voltage;

[00174] (2) an oscilloscope captures the TLP as it travels towards the target electrode of the VSDM formation;

[00175] (3) the TLP arrives at the target electrode of the VSDM formation. A portion of the energy from the TLP is reflected back as an echo;

[00176] (4) the oscilloscope captures the reflection echo; and

[00177] (5) a computer may be used to process the TLP and the reflection signal to evaluate the

characteristic voltage of the VSDM formation across the respective gap.

[00178] The response curves 620 shown in the portion 602 of the graph are displayed over a longer time scale. The response curves 622 shown in the portion 604 of the graph are the response curves 620 displayed over a shorter time scale of 16 nanoseconds. The TLP voltage input is shown as signal 610, and respectively signal 612.

[00179] As shown from the graph 600, as the input signal 610 increases, the voltage across the VSDM

structure tracks the input voltage initially, but starts to diverge as the VSD material starts to conduct increasingly more current. At some point, the VSD material switches to become substantially conductive, and the response signal stabilizes at a value below 200 V despite the fact that the input signal 610 continues to increase. The characteristic voltage of the VSD material layer can be estimated from the graph 600 to be between 150 V and 220 V.

[00180] 6. Overview of the Operation of an Impedance Element.

[00181] The architecture and operation of exemplary circuits that may utilize switching VSDM formations as described and/or claimed in this patent for ESD protection are disclosed in US. Application Serial No. 13/096,860 and in Application Serial No. 13/115,068.

[00182] FIG. 7 shows a circuit configuration that uses a VSDM component 704 in combination with an impedance element 720 to protect an electronic component 730 against ESD events, in accordance with an embodiment. The circuit configuration shown in the embodiment of FIG. 7 is architecturally and operationally similar to some of the exemplary circuits discussed in US Applications 13/096,860 and 13/1 15,068 (e.g., the circuit discussed in connection with the embodiment of FIG. 2 in US Applications 13/096,860).

[00183] In general, the term "VSDM component" encompasses any switching VSDM formation that may be adapted to provide ESD protection, including the horizontal switching VSDM formations, vertical switching VSDM formations and dual switching VSDM formations discussed in this patent in connection with various embodiments. The term "VSDM component" may be more convenient when considering the operation and functionality of a switching VSDM formation as perceived from a system design, simulation and/or manufacturing standpoint. A VSDM component may be described, emulated, simulated and modeled like other components (whether embedded or discrete) in an electric circuit.

[00184] In the embodiment of FIG. 7, the VSDM component 704 may be incorporated inside a substrate or may otherwise be connected to a substrate, including as discussed above in connection with the embodiments of FIGs. 1, 2, 4A, 4B and 5. Examples of such substrates, as previously described, include any PCB, any single layer or set of multiple layers of a PCB, the package of a semiconductor device, an LED substrate, an integrated circuit (IC) substrate, an interposer or any other platform that connects two or more electronic components, devices or substrates (where such connection may be vertical and/or horizontal), any other stacked packaging or die format (e.g., an interposer, a wafer- level package, a package-in-package, a system-in-package, or any other stacked combination of at least two packages, dies or substrates), or any other substrate to which a VSDM formation can be attached or within which a VSDM formation may be incorporated.

[00185] In the embodiment of FIG. 7, the VSDM component 704 is shown as being connected to a ground.

This ground could be a ground plane inside a substrate, or any other conductive structure that is connected directly or indirectly to a ground signal level. In an alternative implementation, the VSDM component 704 may be connected to a different point in an electric circuit or inside an electronic device (e.g., to any predetermined net, potential or other reference or point to which an ESD pulse may be directed in whole or in part or from which an electrical signal may be received). In various embodiments, the VSDM component 704 is connected to a ground, virtual ground, a shield, a safety ground, a package shell, a conductive line, a direct or indirect connection to a component, a point along any other electrical path, or any combination of the foregoing. The connection of the VSDM component 704 to a ground or to another reference point may be made directly, or through one or more circuit elements.

[00186] In the embodiment of FIG. 7, an impedance element 720 is disposed between the VSDM

component 704 and an electronic component 730 to be protected against ESD events. In one embodiment, the impedance 720 is the same, or is similar to the embedded impedance 596 discussed in connection with the embodiment of FIG. 5.

[00187] In one embodiment, the impedance element 720 is a resistor, in which case the impedance H of the impedance element 720 is substantially resistive and does not include any significant capacitive or inductive components. In other embodiments, the impedance element 720 could have a more complex impedance profile, as further discussed below and in US Applications 13/096,860 and 13/115,068.

[00188] In various embodiments, an impedance element, such as impedance element 720, consists of one or more circuit elements, performs the function of one or more circuit elements, or comprises one or more circuit elements. In various embodiments, the impedance element 720 may include one or more resistors, one or more inductors, one or more capacitors, one or more ferroic circuit elements (e.g., an embedded ferroic circuit element that may or may not comprise VSD material), one or more diodes, one or more transistors, one or more filters (e.g., various combinations of one or more low- pass, band-pass and high-pass filters or filter stages), any other passive or active circuit elements or electronic components, any layered interconnect with a negligible impedance, any layered interconnect with a non-negligible impedance (e.g., a layer of high dielectric material), any electrode or other conductive structure with a non-negligible impedance, and/or any combination of the foregoing.

[00189] In various embodiments, an impedance element, such as impedance element 720, may be

embedded in a VSDM component (such as VSDM component 704), or may be embedded in the same substrate in which the VSDM component 704 is incorporated. In one embodiment, an impedance element, such as impedance element 720, may be surface-attached to the same substrate in which the VSDM component 704 is incorporated. In one embodiment, an impedance element, such as impedance element 720, may be incorporated in a different electronic device that is in electrical contact with the substrate in which the VSDM component 704 is incorporated (e.g., the VSDM component 704 may be incorporated in a connector that is attached to an electronic device that comprises the impedance element). In one embodiment, an impedance element, such as impedance element 720, is comprised in the packaging of the electronic component 730, or is otherwise attached to or incorporated into a substrate that is in physical contact or in electrical communication with the electronic component 730.

[00190] From an operational standpoint, in the embodiment of FIG. 7, the impedance element 720 is

designed to help protect the electronic component 730 by attenuating or otherwise modifying in whole or in part a signal that propagates towards the electronic component 730 in response to the ESD pulse 712. Upon occurrence of the ESD pulse 712, the VSDM component 704 switches to a substantially conductive state and redirects at least a first portion of the ESD pulse 712 to the ground shown in FIG. 7 (or to another point), therefore attenuating the signal produced in response to ESD pulse 712 that would otherwise propagate to the electronic component 730. In this configuration, an attenuated second portion of the ESD pulse 712 may reach the impedance element 720, rather than the full ESD pulse 712. By redirecting at least a portion of the ESD pulse 712 to the ground, the VSDM component 704 prevents that redirected portion of the ESD pulse 712 from reaching the electronic component 730, thus, providing at least partial ESD protection to the electronic component 730.

[00191] In the embodiment of FIG. 7, the signal that is still transmitted towards the electronic component 730 in response to the ESD pulse 712 is intercepted by the impedance element 720. The impedance element 720 may be designed to further attenuate this signal (e.g., reduce its voltage and/or current amplitude), or to otherwise modify it (e.g., alter its frequency spectrum). As a result, the electronic component 730 receives a smaller portion of the ESD pulse 712 and is protected against ESD damage.

[00192] In some embodiments, the signal that is transmitted to the electronic component 730 experiences a voltage drop across the impedance element 720. By controlling this voltage drop (e.g., through appropriate design specifications), the voltage and current received at the electronic component 730 may be decreased to non-damaging or otherwise predetermined levels.

[00193] In general, the impedance element 720 may be designed to have a transfer function that attenuates or suppresses some or all of the electrical or frequency characteristics of the signal propagating towards the electronic component 730. Examples of such characteristics that can be attenuated or suppressed by the electronic component 730 in accordance with embodiments include voltage, current, frequency and/or bandwidth (e.g., an expected frequency spectrum), time value, and/or pulse shape.

[00194] In the embodiment of FIG. 7, the impedance element 720 may be configured to temporarily block the ESD pulse 712 while the VSDM component 704 switches to its substantially conductive state. In some embodiments, the ESD pulse 712 has a leading edge that rises rapidly. While the VSDM component 704 may be configured to switch fast, the response time of VSD materials is generally subject to a nonzero time delay. The leading edge of some ESD pulses may rise faster than the response time of the VSDM component 704. Consequently, the voltage generated by the ESD pulse 712 could momentarily exceed the damage threshold of the electronic component 730. The impedance element 720 may include circuit elements, such as a low pass filter, configured to block high frequency components included in fast rising pulses. In various embodiments, the impedance element 720 blocks a rising pulse when it is at a voltage level that is less than the characteristic voltage of the VSDM component 704. To achieve this, the impedance element 720 may be configured to suppress the ESD pulse in whole or in part at least temporarily before the VSDM component 704 begins switching. As a result, the impedance element 720 could block one or more characteristics or components of the ESD pulse 712 (e.g., the rising edge of a pulse in the ESD pulse 712) during the time it takes for the VSDM component 704 to switch from its substantially insulating state to its substantially conductive state.

[00195] In various embodiments, an impedance element, such as impedance element 720, includes a

voltage or current amplitude and/or frequency filter. For example, the impedance element 720 may be configured as a high pass filter, a low pass filter, or a band pass filter. The impedance element 720 may transmit a first voltage or current (e.g., associated with normal operation of electronic component 730) with no, or substantially no, distortion or attenuation, and may block in whole or in part a second voltage or current associated with abnormal events (e.g., an ESD event). For example, the impedance element 720 may be configured as a low pass filter to transmit to the electronic component 730 a signal at normal or design frequencies. Upon occurrence of an ESD pulse 712 including high frequency components, the impedance element 720 may block in whole or in part the high frequency components of the ESD pulse 712. The full or partial blocking of the ESD pulse 712 may provide the VSDM component 704 sufficient time to respond to the high voltage regime and switch to a substantially conductive state before the electronic component 730 may be damaged.

[00196] The impedance of the impedance element 720 may be selected to pass to the electronic component 730 signals at voltages that would not normally damage electronic component 730 (e.g., voltages below 40 volts, below 24 volts, below 12 volts, below 5 volts, and/or below 3 volts, depending upon the respective chip or device specifications). The impedance of the impedance element 720 may be further selected to block ESD pulse 712 at high and/or potentially damaging voltages (e.g., above 10 volts, above 100 volts, above 1000 volts, above lOkV, or even higher) depending upon the chip or device specifications of the electronic component 730 and/or frequency components of the ESD pulse 712.

[00197] In one embodiment, the impedance element 720 may be implemented using a ferroic circuit

element that includes a conductive structure embedded at least partially within a ferroic material. A ferroic circuit element comprising ferroic VSD material and suitable for such implementations was disclosed in United States patent application 13/115,068. In various embodiments, the impedance element 720 may be implemented as an embedded ferroic inductor, embedded ferroic VSD material inductor, embedded ferroic capacitor, embedded ferroic VSD material capacitor, or as any other embedded ferroic circuit element or embedded ferroic VSD material circuit element.

[00198] 7. Component-based Impedance Configurations Supporting VSDM Formations.

[00199] FIG. 8 shows a circuit configuration that uses a VSDM component 804 in combination with an impedance element 820 to protect an electronic component 830 against ESD events, in accordance with an embodiment. In the embodiment of FIG. 8, the VSDM component 804 is shown as being incorporated in a substrate 890.

[00200] In one embodiment, the configuration shown in FIG. 8 is similar in operation and general

architecture with the configuration discussed in connection with the embodiment of FIG. 7, and the impedance element 820 from FIG. 8 corresponds to the impedance element 720 from FIG. 7. A difference, however, is that the impedance element 720 from the embodiment of FIG. 7 was shown as being disposed outside the electronic component 730. In the embodiment of FIG. 8, however, the impedance element 820 is disposed inside the electronic component 830.

[00201] The electronic component 830 includes one or more circuits, modules and/or subsystems used for data processing, memory, mixed signal, and logic combined with memory, including NAND, NOR and DRAM memory, digital baseband or applications processing, microprocessing and

microcontrolling, which are generally represented in FIG. 8 as on-chip circuitry 832. On-chip circuitry 832 could perform any type of functionality found in electronic components, including wireline or wireless data transmission and reception, signal processing, signaling, logic functions and data processing, and so on. In general, some or all of the on-chip circuitry 832 is sensitive to ESD events and should be protected against ESD or other overvoltage conditions.

[00202] In general, some electronic components may incorporate an internal ESD protection stage, which includes circuitry intended to provide ESD protection for the respective electronic components. In FIG. 8, such an ESD protection stage is illustrated as ESD stage 834. The ESD stage 834 is an optional internal subsystem included in the electronic component 830, and is illustrated in FIG. 8 with a dotted perimeter. The ESD stage 834 is shown as connected with the impedance element 820 and with the on-chip circuitry 832. [00203] Even if an electronic component includes an ESD protection stage, the respective component may still benefit from protection using an external VSDM component. As discussed in connection with the embodiment of FIG. 7, the ESD performance of a VSDM component may be enhanced by using an impedance element, such as impedance element 720. Since the impedance element 720 is disposed outside the electronic component 730 in the embodiment of FIG. 7, the design, characteristics and position of the impedance element 720 may be determined without altering the design of the electronic component being protected against ESD events. Consequently, an advantage of the architectural approach in the embodiment of FIG. 7 is that the design of the electronic component 730 is not impacted in any way, and all design and manufacturing decisions regarding the design, characteristics and placement of the impedance element 720 may be made at the substrate or system level.

[00204] In the embodiment, of FIG. 8, however, the impedance element 820 is built into the electronic component 830. An advantage of this approach is that if the design of an electronic component can be changed by adding such an impedance circuit element internally with acceptable impact on the cost and operation of the electronic component, the electronic components could be manufactured in large volume to incorporate the impedance elements, therefore eliminating or reducing the need to integrate impedance elements in the substrates (e.g., level one or level two packaging such as ball grid array and PCBs, respectively) to which such electronic components are eventually attached.

[00205] In general, an impedance element that is incorporated in an electronic component and that may be used in connection with a VSDM component integrated in a substrate to protect the electronic component against ESD pulses or other overvoltage conditions may be denoted a "component-based impedance element" or "chip-based impedance element."

[00206] Analogously, an impedance element that is incorporated in substrate and that may be used in

connection with a VSDM component to protect an electronic component against ESD pulses or other overvoltage conditions may be denoted a "substrate-based impedance element."

[00207] In one embodiment, an electronic device could utilize both a component-based impedance element and an off-chip impedance element incorporated in a substrate (denoted "substrate-based impedance element") to which the electronic component is attached. For example, if the internal impedance element 820 incorporated in the electronic device 830 from the embodiment of FIG. 8 is later found to be too small for the VSDM component 804 in a particular circuit configuration, an additional substrate-based impedance element could be incorporated into the substrate to which the VSDM component 804 is attached (e.g., could be introduced in the same position shown for the impedance element 720 in the embodiment of FIG. 7). This approach could allow a designer to utilize component-based and substrate-based impedance elements in an additive manner (e.g., adding the values of resistors if both impedance elements are implemented as resistors), or in a complementary manner (e.g., if the substrate-based impedance element is a capacitor and the component-based impedance element is a resistor).

[00208] The component-based impedance element approach illustrated in the embodiment of FIG. 8

provides a device and/or systems designer with an additional dimension for optimizing costs and designs of electronic devices: impedance elements could be incorporated in substrates, in electronic components attached to substrates, or in both substrates and the electronic components.

[00209] In various embodiments, component-based impedance elements, such as impedance element 820, may be disposed on each pin of the electronic component, including data I/O pins, power and grounding pins, signaling pins, etc. This could maximize the probability that the electronic component can be protected by substrate-based VSDM components and may minimize the cost and design complexity at the substrate level by avoiding or reducing the need to implement substrate- based impedance elements.

[00210] In some embodiments, component-based impedance elements, such as impedance element 820, may be disposed only on select pins of the electronic component (e.g., only on some data I/O pins or only on some signaling pins). This could minimize the cost and design impact on the electronic component, but may correspondingly increase the cost and design complexity at the substrate level by increasing the need to implement substrate-based impedance elements for various VSDM components.

[00211] To design a component-based impedance element, such as the impedance element 820 from the embodiment of FIG. 8, a number of considerations could be taken into account in various embodiments, including the following:

[00212] a. The optimal impedance type, characteristics and value needed to support the operation of the VSDM component 804 (e.g., the specific value of a resistor (in Ohms) to be used, the frequency transfer function of a filtering stage, etc.). In one implementation, the specific operational characteristics of one or more VSDM components implemented in substrates (e.g., characteristic voltage, switching time, etc.) and other relevant design parameters (e.g., any additional impedance that may exist on the connections between the VSDM components and the electronic component) are known, and the component-based impedance element could be designed to specifically take into account these substrate-related and/or off-chip characteristics and parameters. In one

implementation, a designer could assume certain standardized values for such substrate-related and/or off-chip characteristics and parameters (e.g., such values could be specified as design parameters in a device-level or substrate-level datasheet or design guide), and may consequently design the component-based impedance elements using those standardized values.

[00213] b. The acceptable design impact on the electronic component 830, including any impact on cost, space for circuitry, routing of signals, performance, power consumption, and other similar design parameters customarily used in the industry. [00214] c. The tradeoffs in terms of total device cost, design complexity and performance by comparing component-based and substrate-based impedance elements.

[00215] From a manufacturing standpoint, the same standard manufacturing techniques used to

manufacture the rest of the circuitry, modules and subsystems of the electronic component 830 could also be used to manufacture the impedance element 820 inside the electronic component 830 from FIG. 8. In general, the impedance element 820 can be designed as part of the design for the electronic component 830, and can then be manufactured and tested as part of the manufacturing and qualification process for the electronic component 830.

[00216] FIG. 9 shows another circuit configuration that uses a VSDM component 904 in combination with an impedance element 920 to protect an electronic component 930 against ESD events, in accordance with an embodiment. In the embodiment of FIG. 9, the electronic component 930 represents a class of leadframe electronic components and interconnects. FIG. 9 also shows a circuit configuration that uses a VSDM component 904 in combination with an impedance element 922 to protect an electronic component 932 against ESD events, in accordance with an embodiment. The electronic component 932 represents a wirebond class of electronic components and embodiments. In various other embodiments, any other type of electronic device, packaging and interconnect can be adapted to incorporate one or more impedance elements (such as impedance elements 920 and 922) in the interconnecting layer that couples the electronic device to a substrate. Other classes of electronic components can be similarly protected using configurations similar to those illustrated in FIG. 9.

[00217] In the embodiment of FIG. 9, the VSDM component 904 is incorporated in a substrate 990.

[00218] In one embodiment, an impedance element, such as the impedance elements 920 and/or 922, is incorporated in a pad or in the patterned pad structure disposed within an electronic component, such as the electronic components 930 and 932.

[00219] In existing applications, an interconnect or plurality of interconnects (e.g., a set of pins) of

electronic components are generally manufactured out of highly conductive materials, and a design goal is to minimize the impedance of such pins. The embodiment of FIG. 9, however, intentionally introduces an impedance element in one, some, or all connecting elements or other portion of the interconnecting layer of an electronic component to enhance the ESD protection provided to that electronic component by one or more off-chip VSDM components.

[00220] The architecture shown in the embodiment of FIG. 9 is similar to the configuration from the

embodiment of FIG. 8, with the impedance element 920 or 922 from FIG. 9 corresponding to the impedance element 820 from FIG. 8. A difference, however, is that the impedance element 920 or 922 from FIG. 9 is disposed as part of a pin, lead or other interfacing connector of the electronic component, instead of being incorporated inside the electronic component. [00221] Since the impedance element 920 or respectively 922 is built into the electronic component 930 or respectively 932, the impedance elements 920 and 922 may still be considered to be a component- based impedance elements, similar to the impedance element 820 from the embodiment of FIG. 8. Consequently, the discussion above regarding the impedance element 820 in connection with the embodiment of FIG. 8 would also apply in general to the impedance elements 920 and 922 from the embodiment of FIG. 9, including with respect to possible positioning and design.

[00222] For clarification, while two different electronic components are shown in FIG. 9 having chip-based impedance elements (i.e., electronic component 930 comprising chip-based impedance element 920, and respectively electronic component 932 comprising chip-based impedance element 922), each of these configurations are intended to represent independent embodiments that can be used either together, in a single electronic device and connected to a single VSDM component, or can be used separately, connected to different VSDM components (either in the same electronic device or in different electronic devices).

[00223] In various embodiments, an embedded impedance incorporated in a pin, pad, pad structure, lead, bondwire, or other interfacing connector of an electronic component may consist of the whole pin, lead, bondwire or connector (e.g., a bondwire connector of a chip may be manufactured completely out of a resistive material), or may be built as a portion of such pin, lead, bondwire or connector (e.g., a portion of the bondwire of a chip may include a volume of material or feature with non- negligible impedance, while the rest of the bondwire is made out of highly conductive material with a negligible impedance).

[00224] In one embodiment, to manufacture the impedance element 920 or 922 as part of an interconnect element (e.g., a pin, pad, pad structure, lead, bondwire or other interfacing connector of an electronic component), the respective interconnect element is manufactured in whole or in part out of a material that has a non-negligible impedance. For example, the interconnect element could be manufactured out of a resistive material, partially-conductive polymer, a metal film resistor (e.g., a film coated with nickel chromium), a metal oxide film, any other conductive material modified to exhibit higher resistance (e.g., a doped material or an alloy with lower conductivity), a carbon-composition resistive material (e.g., a composition of carbon and ceramic materials), a carbon film, a thin film resistor (e.g., manufactured using sputtering), a thick film resistor (e.g., manufactured using screen or stencil printing), or any other material characterized by a non-negligible impedance that can be adequately controlled or predicted for design purposes.

[00225] In one embodiment, to manufacture the impedance element 920 as part of an interconnect element (e.g., a pin, pad, pad structure, lead, bondwire or other interfacing connector of an electronic component), the respective interconnect element is modified so that it exhibits a non-negligible impedance. For example, the cross sectional area, volume or shape of a bondwire can be modified so that it exhibits a higher impedance (e.g., by making a notch or series of notches in a bondwire, the resistance of the bondwire could be increased). In various embodiments, modifications of the shape of a pin, lead, bondwire or other interfacing connector of an electronic component also take into account secondary effects, such as RF emissions from a pin used to transmit data at data rates.

[00226] FIG. 10 shows another circuit configuration that uses a VSDM component 1004 in combination with an impedance element 1020 to protect an electronic component 1030 against ESD events, in accordance with an embodiment. In the embodiment of FIG. 10, the VSDM component 1004 is incorporated in a substrate 1090.

[00227] The architecture shown in the embodiment of FIG. 10 is similar to the configuration from the embodiment of FIG. 9, with the impedance element 1020 from FIG. 10 corresponding to the impedance element 920 from FIG. 9. A difference, however, is that the impedance element 1020 from FIG. 9 is disposed as part of a redistribution layer 1080, instead of being incorporated in a pin, lead or other interfacing connector of the electronic component.

[00228] A redistribution layer (sometimes denoted as "RDL") is an interconnection layer or a set of routing connections that can be added to electronic components (e.g., integrated circuits with small features and higher density of I/O lines) to facilitate the interconnection between such electronic components and a substrate or other components. In current industry applications, electronic components are often connected to a substrate (e.g., to a PCB) using a set of bumps, illustrated in FIG. 10 as bump 1080. The number of bumps used for each electronic component generally increases as the density of connections needed for the component increases. A redistribution layer is sometimes used when the internal connector spacing inside an electronic component is smaller than the spacing between bumps, in which case a redistribution layer can be used to fan out the internal connectors to match the available bump configuration on the connecting substrate. Another application for redistribution layers is to route the internal connector lines from a die inside an electronic component to particular bumps, if a specific pinout or signal distribution is required or desirable for the electronic component. A redistribution layer normally comprises one or more layers, runners, traces or other connecting elements that permit signal routing in accordance with applicable specifications. A description of redistribution layers may be found in a document titled "Bumping Design Guide" released by FlipChip International LLC, revised on May 2009, and this document is hereby incorporated by reference in its entirety.

[00229] In the embodiment of FIG. 10, the electronic component 1030 comprises one or more dies,

illustrated as die 1032, and the redistribution layer 1080. The die 1032 is connected to the substrate 1090 through the redistribution layer 1080 and a set of bumps. The set of bumps are illustrated by bump 1080.

[00230] The redistribution layer 1080 comprises one or more conductive layers, runners, traces, lines or other connecting elements that can route signals between the die 1032 and the bumps, including to bump 1080. The bump 1080 and the other bumps are in electrical contact with the substrate 1090, so that data can be transmitted in either or both directions between the die 1032 and the substrate 1090.

[00231] In various embodiments, one, more, or all of the layers, runners, traces, lines or other connecting elements of a redistribution layer, such as the redistribution layer 1080, consist of, or incorporate an impedance element, such as impedance element 1020. For example, in the redistribution layer 1080 shown in FIG. 10, a layer denoted RDL layer 1082 comprises an impedance element 1020. In various embodiments, the RDL layer 1082 may be a layer, runner, trace, line or other connecting element that is in direct or indirect electrical contact with the die 1032 and with the bump 1080. In one embodiment, the impedance element 1020 may consist of a discrete circuit element built within the RDL layer 1082 (e.g., a resistor may be built within the RDL layer 1082, while the rest of the RDL layer 1082 is substantially conductive). In one embodiment, the RDL layer 1082 may itself be made out of a material with a non-negligible impedance, such that the RDL layer 1082 itself may be (in whole or in part) the impedance element 1020.

[00232] In the embodiment of FIG. 10, the VSDM component 1004 is in electrical contact with the bump 1080. The bump 1080 is in electrical contact with the die 1032, through the impedance element 1020. Consequently, the general architecture of the arrangement in the embodiment of FIG. 10 is similar to the circuit structure discussed in connection with the embodiment of FIG. 7, with the impedance element 1020 from FIG. 10 corresponding to the impedance element 720 from FIG. 7.

[00233] The embodiment of FIG. 10 will consequently operate similarly to the circuit discussed in

connection with the embodiment of FIG. 7: when the ESD pulse 1012 generates a larger voltage and/or current, the VSDM component 1004 and the impedance element 1020 are adapted to cooperatively protect the die 1032. Analogous to the discussion above in connection with the embodiment of FIG. 7, when the voltage generated by ESD pulse 1012 in the embodiment of FIG. 10 exceeds the characteristic voltage of the VSDM component 1004, the VSDM component 1004 becomes substantially conductive and diverts at least a portion of the ESD pulse 1012 to ground, while the impedance element 1020 comprised in the RDL layer 1082 attenuates or otherwise modifies in whole or in part at least a portion of the voltage and/or current propagating towards the die 1032. As a result, the configuration shown in the embodiment of FIG. 10 utilizes a component- based impedance element to protect the electronic component 1030 against ESD damage.

[00234] In one embodiment, to manufacture the impedance element 1020, the RDL layer 1082 is

manufactured in whole or in part out of a material that has a non-negligible impedance. Examples of such suitable materials include a resistive material, a partially-conductive polymer, a metal film resistor (e.g., a film coated with nickel chromium), a metal oxide film, any other conductive material modified to exhibit higher resistance (e.g., a doped material or an alloy with lower conductivity), a carbon-composition resistive material (e.g., a composition of carbon and ceramic materials), a carbon film, a thin film resistor (e.g., manufactured using sputtering), a thick film resistor (e.g., manufactured using screen or stencil printing), or any other material characterized by a non- negligible impedance that can be adequately controlled or predicted for design purposes.

[00235] 8. Interconnect-Based Impedance Configurations Supporting VSDM Formations.

[00236] FIG. 1 1 shows another circuit configuration that uses a VSDM component 1104 in combination with an impedance element 1120 to protect an electronic component 1 130 against ESD events, in accordance with an embodiment.

[00237] In the embodiment of FIG. 11, the electronic component 1130 is connected to the substrate 1190 via a set of solder bumps (denoted simply "bumps" for convenience), including bump 1 180. The bump 1 180 is in direct or indirect electrical communication with the VSDM component 1 104. The VSDM component 1 104 is embedded in the substrate 1190.

[00238] A common type of bumps used in the industry for attaching electronic components to substrates (e.g., to PCBs) are solder bumps. Other types of bumps used in the industry to attach electronic components to substrates include thermal copper pillar bumps and copper pillar solder bumps, which are often used with electronics and optoelectronic packaging, including flip chip packaging of CPU and GPU chips, laser diodes, and semiconductor optical amplifiers (SOA).

[00239] In existing applications, bumps and other connectors that are used to attach electronic components to substrates are generally manufactured out of highly conductive materials, and a design goal is to minimize the impedance of such bumps or other connectors. The embodiment of FIG. 11 , however, intentionally introduces an impedance element in one, some, or all bumps or other connectors of an electronic component to enhance the ESD protection provided to that electronic component by one or more off-chip VSDM components.

[00240] As shown in FIG. 1 1, an impedance element 1 120 is disposed inside a bump 1180. In one

embodiment, the bump 1 180 is manufactured in whole or in part out of a material that has a non- negligible impedance. Examples of such suitable materials include a resistive material, a partially- conductive polymer, a metal film resistor (e.g., a film coated with nickel chromium), a metal oxide film, any other conductive material modified to exhibit higher resistance (e.g., a doped material or an alloy with lower conductivity), a carbon-composition resistive material (e.g., a composition of carbon and ceramic materials), a carbon film, a thin film resistor (e.g., manufactured using sputtering), a thick film resistor (e.g., manufactured using screen or stencil printing), or any other material characterized by a non-negligible impedance that can be adequately controlled or predicted for design purposes.

[00241] Because the impedance element 1 120 is disposed within a bump, which acts as an interconnecting medium that mediates communications between the electronic component 1130 and the substrate 1 190 or other electronic components, the impedance element 1120 may be denoted an "interconnect- based impedance element." In general, an impedance element disposed in an wire, connector, pad, or any other structure that performs an interconnecting function between an electronic component and a substrate, or between an electronic component and other circuit elements or electronic components, could be denoted as an interconnect-based impedance element.

[00242] In general, the architecture of the embodiment of FIG. 1 1 is similar to the embodiment of FIG. 7, with the impedance element 1 120 corresponding to the impedance element 720 from FIG. 7, and with the VSDM component 1104 corresponding to the VSDM component 704 from FIG. 7.

Functionally, the VSDM component 1104 and the VSDM component 1 104 are adapted to collaboratively protect the electronic component 1 130 in generally the same manner as described in connection with the electronic component 710 from the embodiment of FIG. 7.

[00243] In general, the architecture of the embodiment of FIG. 1 1 is also similar to the embodiment of FIG.

10, with the impedance element 1120 corresponding to the impedance element 1020 from FIG. 10, and with the VSDM component 1104 corresponding to the VSDM component 1004 from FIG. 10. A difference, however, is that the impedance element 1 120 is disposed inside the bump or is the pillar material with a solder cap 1180, as opposed to being incorporated in a redistribution layer.

Functionally, the VSDM component 1104 and the VSDM component 1 104 are adapted to collaboratively protect the electronic component 1 130 in generally the same manner as described in connection with the electronic component 1030 and die 1032 from the embodiment of FIG. 10.

[00244] FIG. 12A shows another circuit configuration that uses a VSDM component 1204 in combination with an impedance element 1220 to protect an electronic component 1230 against ESD events, in accordance with an embodiment.

[00245] In the embodiment of FIG. 12A, the electronic component 1230 is connected to the substrate 1290 via a set of bumps, including bump 1280. Each bump attaches to the substrate 1290 through a connector, pad, or another connecting structure, illustrated in FIG. 12A as connector/pad 1282. The electronic component 1230 is in direct or indirect electrical communication with the VSDM component 1204 through the bump 1220 and the connector/pad 1282. The VSDM component 1204 is embedded in the substrate 1290.

[00246] In existing applications connectors, pads, and other conductive structures that are used to attach electronic components to substrates are generally manufactured out of highly conductive materials, and a design goal is to minimize the impedance of such connectors, pads, and other conductive structures. The embodiment of FIG. 12A, however, intentionally introduces an impedance element in one, some, or all such connectors, pads, or other conductive structures that connect an electronic component to a substrate, therefore enhancing the ESD protection provided to that electronic component by one or more off-chip VSDM components.

[00247] As shown in FIG. 12A, an impedance element 1220 is disposed inside a connector, pad, or other conductive structure that is designed to facilitate connection of an electronic component to a substrate, illustrated as connector/pad 1282. In one embodiment, the connector/pad 1282 is manufactured in whole or in part out of a material that has a non-negligible impedance. Examples of such suitable materials include a resistive material, a partially-conductive polymer, a metal film resistor (e.g., a film coated with nickel chromium), a metal oxide film, any other conductive material modified to exhibit higher resistance (e.g., a doped material or an alloy with lower conductivity), a carbon-composition resistive material (e.g., a composition of carbon and ceramic materials), a carbon film, a thin film resistor (e.g., manufactured using sputtering), a thick film resistor (e.g.,

manufactured using screen or stencil printing), or any other material characterized by a non- negligible impedance that can be adequately controlled or predicted for design purposes.

[00248] Because the impedance element 1220 is disposed within a connector, pad, or other conductive structure that interconnects the electronic component 1230 and the substrate 1290 or other electronic components, the impedance element 1220 may be considered to be an interconnect-based impedance element.

[00249] In general, the architecture of the embodiment of FIG. 12A is similar to the embodiment of FIG. 10 or 1 1, with the impedance element 1220 and VSDM component 1204 corresponding to the impedance element 1 120 and respectively VSDM component 1 104 from FIG. 11. Functionally, the impedance element 1220 and the VSDM component 1204 are adapted to collaboratively protect the electronic component 1230 against ESD events in generally the same manner as described in connection with the impedance element 1 120 and the VSDM component 1104 protecting the electronic component 1 110 in the embodiment of FIG. 1 1.

[00250] FIG. 12B shows another circuit configuration that uses a VSDM component 1206 in combination with an impedance element 1222 to protect a die 1234 against ESD events, in accordance with an embodiment.

[00251] In the embodiment of FIG. 12B, the die 1234 is connected an interposer 1298. The connection between the die 1234 and the interposer 1298 is illustrated in FIG. 12B as wirebond 1286, but in general may be achieved through any interconnect element (e.g., pins, wirebonds, bumps, or other conductive connectors). The die 1234 is in direct or indirect electrical communication with the VSDM component 1206 through the wirebond 1286. The VSDM component 1206 is embedded in the interposer 1298. In an alternative embodiment, the VSDM component 1206 could be disposed within a substrate to which the interposer is attached (e.g., to the PCB 1292 shown in FIG. 12B).

[00252] In general, an interposer is an interconnecting device that comprises a set of pins, leads, wires (e.g., wirebonds), conductive planes, or other connectors that are adapted to facilitate electrical interface routing between a die or an electronic component and a substrate (in which case the interposer could be considered a first level package, and the substrate to which the interposer is connected (e.g., a PCB) could be considered a second level package), or between two or more electronic components. An interposer may be used, for example, to spread a denser set of I/O lines of an electronic component to a wider connection pitch available on a substrate, or to reroute particular connection lines of an electronic component to specific connectors available on a substrate. Functionally, an interposer is similar to a redistribution layer as discussed in connection with the embodiment of FIG. 10, except that an interposer is often disposed outside an electronic component, while a redistribution layer can often be considered to be part of an electronic component (e.g., part of a wafer, chip, or die).

[00253] In existing applications, interposers and other interconnection structures that are used to attach dies to substrates are generally manufactured out of highly conductive materials, and a design goal is to minimize the impedance of such connectors, pads, and other conductive structures. The embodiment of FIG. 12B, however, intentionally introduces one or more impedance elements in an interposer or other conductive structure that connects a die to a substrate, therefore enhancing the ESD protection provided to that die by one or more VSDM components.

[00254] In the embodiment of FIG. 12B, the interposer 1298 serves as an interconnecting substrate that connects the die 1234 to another substrate, illustrated as PCB 1292. The interposer 1298 may be connected to such other substrate (e.g., to the PCB 1292) through any set of one or more suitable interconnecting elements, such as wirebonds (e.g., wirebonds 1284), bumps (e.g., bumps 1282), pins, an interposer, or any other conductive structures.

[00255] In the embodiment of FIG. 12B, the impedance element 1222 is disposed inside an interposer (i.e., the interposer 1298). In other embodiments, the impedance element 1222 may be disposed in other conductive structures that facilitate connection of a die to a substrate.

[00256] In one embodiment, to produce one or more impedance elements in an interposer (e.g., inside the interposer 1298) or inside another interconnection structure that connects a die to a substrate, such as the impedance element 1222, one or more conductive elements (e.g., pins, leads, wires (e.g., wirebonds), conductive planes, or other connectors that are adapted to facilitate electrical interface routing inside such interposer or other interconnection structure) are manufactured in whole or in part out of a material that has a non-negligible impedance. Examples of such suitable materials include a resistive material, a partially-conductive polymer, a metal film resistor (e.g., a film coated with nickel chromium), a metal oxide film, any other conductive material modified to exhibit higher resistance (e.g., a doped material or an alloy with lower conductivity), a carbon-composition resistive material (e.g., a composition of carbon and ceramic materials), a carbon film, a thin film resistor (e.g., manufactured using sputtering), a thick film resistor (e.g., manufactured using screen or stencil printing), or any other material characterized by a non-negligible impedance that can be adequately controlled or predicted for design purposes.

[00257] Because the impedance element 1222 is disposed within an interposer or other interconnection structure that connects the die 1234 and the PCB 1292, the impedance element 1222 may be considered to be an interconnect-based impedance element. [00258] The operation of the VSDM component 1206 and the impedance element 1202 to protect the die 1234 against ESD damage in response to an ESD pulse, such as ESD pulse 1214, is functionally similar to that described in connection with previous embodiments, such the embodiments of FIG. 10 and 1 1.

[00259] In one embodiment, to produce one or more impedance elements in an interposer (e.g., inside the interposer 1298) or inside another interconnection structure that connects a die to a substrate, such as the impedance element 1222, one or more conductive elements (e.g., pins, leads, wires (e.g., wirebonds), conductive planes, or other connectors that are adapted to facilitate electrical interface routing inside such interposer or other interconnection structure) are modified so that they exhibits a non-negligible impedance. For example, the cross sectional area, volume or shape of a bondwire can be modified so that it exhibits a higher impedance (e.g., by making a notch or series of notches in a bondwire, the resistance of the bondwire could be increased). In various embodiments,

modifications of the shape of a conductive element also take into account secondary effects, such as RF emissions from a pin used to transmit data at data rates..

[00260] 9. Substrate-Based Impedance Configurations Supporting VSDM Formations.

[00261] FIG. 13 shows another circuit configuration that uses a VSDM component 1304 in combination with an impedance element to protect an electronic component 1330 against ESD events, in accordance with an embodiment. The impedance element from the embodiment of FIG. 13 is configured as a horizontal switching VSDM formation, disposed within a substrate 1390.

[00262] In the embodiment of FIG. 13, the substrate 1390 comprises a substrate layer 1360, adjacent to an impedance layer 1320. The impedance layer 1320 is in contact with a conductive layer 1350. A substrate layer 1362 separates the conductive layer 1350 from a layer of VSD material 1340. A conductive layer 1352 separates the layer of VSD material 1340 from the substrate layer 1364.

[00263] A conductive structure 1372 establishes electrical contact between the conductive layer 1350 and the layer of VSD material 1340, across the substrate layer 1362. A second conductive structure 1374 defines a horizontal gap 1342 within the layer of VSD material 1340. The conductive structure 1374 is connected to a ground.

[00264] A component 1330 is attached to the substrate 1390. A conductive structure 1370 is disposed to cross the substrate layer 1360, establishing an electrical connection between the component 1390 and the impedance layer 1320.

[00265] The architecture of the arrangement shown in the embodiment of FIG. 13 establishes a

configuration similar to that discussed in connection with the embodiment of FIG. 7, with the horizontal switching VSDM formation incorporated within the substrate 1390 corresponding to the VSDM component 704 from FIG. 7, and with the impedance layer 1320 corresponding to the impedance element 720 from FIG. 7. Upon the occurrence of an ESD pulse 1312 with a sufficiently high voltage, the VSD material 1340 becomes substantially conductive across the gap 1342, redirecting at least a portion of the ESD pulse 1312 to ground. The impedance layer 1320 attenuates or otherwise modifies in whole or in part at least a portion of the voltage or current that would have otherwise propagated to the component 1330 through the conductive layer 1350 and the conductive 1370. Operationally and functionally, the configuration shown in the embodiment of FIG. 13 is similar to the operation and functionality described above in connection with the embodiment of FIG. 7.

[00266] In various embodiments, additional layers, conductive structures and other formations may be disposed within the substrate 1390 and/or the structure and layout of the substrate 1390 shown in FIG. 13 may be modified, but the functionality and operation of the embodiment of FIG. 13 can be preserved as long as the general architecture shown in the embodiment of FIG. 7 is generally maintained. Analogously, the horizontal switching VSDM formation shown in FIG. 13 may be replaced with a vertical switching formation or with a dual switching VSDM formation, as long as the general architecture shown in the embodiment of FIG. 7 is generally maintained.

[00267] In various embodiments, the impedance layer 1320 may be manufactured in whole or in part out of a material that has a non-negligible impedance. Examples of such suitable materials include a resistive material, a partially-conductive polymer, a metal film resistor (e.g., a film coated with nickel chromium), a metal oxide film, any other conductive material modified to exhibit higher resistance (e.g., a doped material or an alloy with lower conductivity), a carbon-composition resistive material (e.g., a composition of carbon and ceramic materials), a carbon film, a thin film resistor (e.g., manufactured using sputtering), a thick film resistor (e.g., manufactured using screen or stencil printing), or any other material characterized by a non-negligible impedance that can be adequately controlled or predicted for design purposes.

[00268] Because the impedance element illustrated in FIG. 13 consists of an impedance layer incorporated in a substrate (i.e., the impedance layer 1320 is incorporated in the substrate 1390), the impedance element of the embodiment of FIG. 13 may be denoted a "substrate-based impedance element." In general, an impedance element that is built, embedded, introduced or otherwise disposed within a substrate may be considered to be a substrate-based impedance element.

[00269] To design a substrate-based impedance element, such as the impedance layer 1320 from the

embodiment of FIG. 13, a number of considerations could be taken into account in various embodiments, including those generally discussed in connection with the embodiment of FIG. 8.

[00270] From a manufacturing standpoint, the same standard manufacturing techniques used to

manufacture various layers of the substrate 1390 could also be used to manufacture the impedance layer 1320 (e.g., impedance layer 1320 may be incorporated in a CCL for subsequent integration into a PCB, or may be built as a stand-alone layer in a PCB). [00271] FIG. 14 shows another circuit configuration that uses a VSDM component 1404 in combination with an impedance element to protect an electronic component 1430 against ESD events, in accordance configured as a an embodiment.

[00272] The impedance element from the embodiment of FIG. 14 is configured as an impedance trace 1420 that is disposed on an external surface of the substrate 1390 (e.g., a surface trace of a PCB), or that is incorporated in the substrate 1390 (e.g., a via, internal trace or route, or other conductive structure incorporated in a substrate). The impedance trace establishes an electrical connection between the VSDM formation 1404 and the component 1430.

[00273] The architecture of the arrangement shown in the embodiment of FIG. 14 is similar to that

discussed in connection with the embodiment of FIG. 7, with the VSDM component 1404 corresponding to the VSDM component 704 from FIG. 7, and with the impedance trace 1420 corresponding to the impedance element 720 from FIG. 7. Upon the occurrence of an ESD pulse 1412 with a sufficiently high voltage, the VSDM component 1404 becomes substantially conductive, redirecting at least a portion of the ESD pulse 1412 to ground. The impedance trace 1420 attenuates or otherwise modifies in whole or in part at least a portion of the voltage or current that would have otherwise propagated to the component 1430. Operationally and functionally, the configuration shown in the embodiment of FIG. 14 is similar to the operation and functionality described above in connection with the embodiment of FIG. 7.

[00274] In various embodiments, the impedance layer 1420 may be manufactured in whole or in part out of a material that has a non-negligible impedance. Examples of such suitable materials include a resistive material, a partially-conductive polymer, a metal film resistor (e.g., a film coated with nickel chromium), a metal oxide film, any other conductive material modified to exhibit higher resistance (e.g., a doped material or an alloy with lower conductivity), a carbon-composition resistive material (e.g., a composition of carbon and ceramic materials), a carbon film, a thin film resistor (e.g., manufactured using sputtering), a thick film resistor (e.g., manufactured using screen or stencil printing), or any other material characterized by a non-negligible impedance that can be adequately controlled or predicted for design purposes.

[00275] Because the impedance element illustrated in FIG. 14 consists of an impedance layer incorporated in a substrate (i.e., the impedance layer 1420 is incorporated in the substrate 1490), the impedance element of the embodiment of FIG. 14 may be considered to be a substrate-based impedance element. In various embodiments, one or more traces or other connectors built on the surface of a substrate and/or within a substrate may be configured to act as impedance elements to protect electronic components in whole or in part.

[00276] 10. Stacked Component Impedance Configurations Supporting VSDM Formations. [00277] FIG. 15 shows another circuit configuration that uses a VSDM component 1504 in combination with an impedance element to protect an electronic component 1530 against ESD events, in accordance with an embodiment. In the embodiment of FIG. 15, the VSDM component 1504 is incorporated in a substrate 1590.

[00278] As the density, functionality and performance of electronic components increase while the form factors of electronic devices are becoming smaller and/or thinner, the horizontal surface area available on substrates to mount electronic components becomes constrained. Consequently, the industry has been moving towards vertical integration of functionality within electronic components, including the development of multi-layered components and the stacking of multiple die or multiple packaged components in a single electronic component.

[00279] In general, a stacked electronic component (more conveniently denoted "stacked component") is any electronic component that comprises two or more dies, two or packaged electronic components, or at least one die and at least one packaged electronic components. Examples of stacked components include one or more of the following: a semiconductor chip or another integrated circuit (IC) (e.g., a microprocessor, controller, memory chip, RF circuit, baseband processor, system on a chip (SOC), a flip chip, etc.), a light emitting diode (LED), an LED array, an LCD, LED, OLED or any other type of display, a MEMS chip or structure, or any other component or circuit element that is incorporated in an electronic device or is used to display information generated by an electronic device.

[00280] In the embodiment of FIG. 15, a stacked component 1530 is connected to the substrate 1590 (e.g., the stacked component 1530 may be surface mounted to the substrate 1590). The connection between the stacked component 1530 and the substrate 1590 may be implemented in a variety of ways, including through a set of bumps shown in FIG. 15 as bumps 1550.

[00281] The stacked component 1530 is shown as comprising two individual dies or packaged components, represented as die/package A 1532 and die/package B 1534. Within the stacked component 1530, the die/package A 1532 and die/package B 1534 are connected through a set of interconnect elements such as pins, leads, wires, solders, or other conductive connectors that facilitate

transmission of data, power, ground and/or other signals. In existing applications, such pins, leads, wires, or other connectors are generally manufactured out of highly conductive materials, and a design goal is to minimize their impedance. The embodiment of FIG. 15, however, intentionally introduces an impedance element in one, some, or all interconnect elements (e.g., pins, leads, wires, solders, or other conductive connectors that facilitate transmission of data, power, ground and/or other signals) that interconnect two or more dies or packages inside a stacked electronic component to enhance the ESD protection provided to the stacked component by one or more off-chip VSDM components. [00282] The architecture shown in the embodiment of FIG. 15 is similar to the configuration from the embodiment of FIG. 8, with the impedance element 1520 from FIG. 15 corresponding to the impedance element 820 from FIG. 8. In FIG. 15, the impedance element 1520 is disposed as part of a pin, lead, wire, or other connector that mediates data or signal transmissions between two or more dies or packaged components.

[00283] Since the impedance element 1520 is designed and built inside the stacked component 1530, the impedance element 1520 may still be considered to be a component-based impedance element, similar to the impedance element 820 from the embodiment of FIG. 8. Consequently, the discussion above regarding the impedance element 820 in connection with the embodiment of FIG. 8 may also apply in general to the impedance element 1520 from the embodiment of FIG. 15, including with respect to the positioning and design.

[00284] In various embodiments, an embedded impedance incorporated in one or more interconnect

elements (e.g., pins, leads, wires, solders, or other conductive connectors that facilitate transmission of data, power, ground and/or other signals) disposed inside a stacked component may consist of the whole interconnect element (e.g., an inter-die connector may be manufactured completely out of a resistive material), or may be built as a portion of such interconnect element (e.g., a portion of an inter-die wirebond may include a volume of material or feature with non-negligible impedance, while the rest of the wirebond is made out of highly conductive material with a negligible impedance).

[00285] In one embodiment, to manufacture the impedance element 1520 inside one or more interconnect elements (e.g., pins, leads, wires, solders, or other conductive connectors that facilitate transmission of data, power, ground and/or other signals) of a stacked component, the respective interconnect element is manufactured in whole or in part out of a material that has a non-negligible impedance. For example, the interconnect element could be manufactured out of a resistive material, a partially- conductive polymer, a metal film resistor (e.g., a film coated with nickel chromium), a metal oxide film, any other conductive material modified to exhibit higher resistance (e.g., a doped material or an alloy with lower conductivity), a carbon-composition resistive material (e.g., a composition of carbon and ceramic materials), a carbon film, a thin film resistor (e.g., manufactured using sputtering), a thick film resistor (e.g., manufactured using screen or stencil printing), or any other material characterized by a non-negligible impedance that can be adequately controlled or predicted for design purposes.

[00286] In one embodiment, to manufacture the impedance element 1520 as part of one or more

interconnect elements (e.g., pins, leads, wires, solders, or other conductive connectors that facilitate transmission of data, power, ground and/or other signals), the respective interconnect element is modified so that it exhibits a non-negligible impedance. For example, the cross sectional area, volume or shape of a pin can be modified so that it exhibits a higher impedance (e.g., by making a notch or series of notches in a wirebond, the resistance of the wirebond could be increased). In various embodiments, modifications of the shape of an interconnect element disposed inside a stacked component also take into account secondary effects, such as RF emissions from a pin used to transmit data at data rates.

[00287] 11. Applications.

[00288] Various embodiments, including various switching VSDM formations and VSDM components, may be implemented in conventional rigid substrates (e.g., a rigid PCB, a rigid semiconductor packaging), in flexible circuits, flexible substrates, flexible semiconductor packaging, and other flexible devices.

[00289] For flexible applications, the formulation of VSD material provided in various embodiments may be adjusted to exhibit enhanced elastic properties. For example, as a general guidelines, reducing the metal particle content in a VSD material (e.g., by reducing or removing metal particles dispersed within the VSD material) or otherwise enhancing the flexibility of cured VSD material may reduce the brittleness of the VSD material, and therefore may make the VSD material more suitable for flexible applications.

[00290] Switching VSDM formations and VSDM components can be further adapted for implementation in flexible applications by the addition of one or more layers or structures with appropriate mechanical and/or environmental endurance attributes. For example, one or more layers or structures in a PCB, semiconductor package, connector or other substrate that incorporates a VSM formation may be manufactured out of polyimide materials, Teflon, epoxy -based materials, or other flexible hybrid materials.

[00291] Polyimide materials are generally lightweight and flexible, have higher mechanical elongation and tensile strength, and tend to have improved resilience against heat and chemical reactions. Polyimide materials are used in the electronics industry to manufacture flexible electrical cables, as an insulating or passivation layer in the manufacture of digital semiconductor and MEMS chips, as insulating films, as high-temperature adhesives, for medical tubing applications, and for other applications where flexibility, lower weight and improved environmental resilience are desired.

[00292] Another possible use of a switching VSDM formation that incorporates heat-resistant materials, such as polyimide materials, is in high-heat applications, such as LED panels or electronic applications operating in areas with higher environmental temperatures (e.g., hot climates) or in devices with limited ventilation (e.g., enclosed or embedded electronic devices or systems with limited or no cooling).

[00293] Switching VSDM formations and VSDM components as described and/or claimed in this patent, including the VSDM formation 100 of the embodiment of FIG. 1, the VSDM formation 200 of the embodiment of FIG. 2, the VSDM formation 400 of the embodiment of FIG. 4A, the VSDM formation 490 of the embodiment of FIG. 4B, the VSDM formation 500 of the embodiment of FIG. 5, and the VSDM components discussed in connection with the embodiments of FIGs. 7 through 15, may be used for ESD protection of circuit elements and components in electric circuits and devices. Examples of electronic components that may be protected by such VSDM formations include one or more of the following: a semiconductor chip or another integrated circuit (IC) (e.g., a

microprocessor, controller, memory chip, RF circuit, baseband processor, system on a chip (SOC), a flip chip, etc.), a light emitting diode (LED), an LED array, an LCD, LED, OLED or any other type of display, a MEMS chip or structure, or any other component or circuit element that is incorporated in an electronic device or is used to display information generated by an electronic device. An electronic component may consist of a single chip unit, or may comprise multiple die and/or stacked components that are packaged together or otherwise adapted to operate together.

[00294] The architecture and operation of exemplary circuits that may utilize switching VSDM formations as described and/or claimed in this patent for ESD protection are disclosed in US. Application Serial No. 13/096,860 and in Application Serial No.13/115,068.

[00295] Switching VSDM formations and VSDM components as described and/or claimed in this patent may be used for ESD protection of substrate devices. Examples of such substrate devices include a layer or set of layers of a PCB, the packaging of a semiconductor device, or any other substrate to which a VSDM formation can be attached or within which a VSDM formation may be incorporated to perform an electrical switching operation.

[00296] Switching VSDM formations and VSDM components as described and/or claimed in this patent may be used for ESD protection of electronic devices in which such VSDM formations are incorporated (e.g., through incorporation into a substrate comprised in such an electronic device), or to which such VSDM formations are connected (e.g., such VSDM formations may be incorporated into a connector or cable attached to such an electronic device, or such VSDM formations may be incorporated into a device that is connected to such an electronic device).

[00297] Examples of electronic devices that may be protected by such switching VSDM formations, or that may include substrate devices, electronic components or circuit elements that may be protected by such switching VSDM formations, include mobile phones, electronic tablets, electronic readers (e- reader), mobile computers (e.g., a laptop), desktop computers, server computers (e.g., servers, blades, multi-processor supercomputers), television sets, video displays, music players (e.g., a portable MP3 music player), personal health management devices (e.g., a pulse monitor, a cardiac monitor, a distance monitor, a temperature monitor, or any other sensor device with applications in health management), light emitting diodes (LEDs) and devices comprising LEDs, lighting modules, and any other consumer and/or industrial devices that process or otherwise store data using electrical or electromechanical signals. Other examples include satellites, military equipment, aviation instruments, and marine equipment. [00298] In various embodiments, switching VSDM formations and VSDM components as described and/or claimed in this patent may be incorporated in a connector. Such a connector may be attached to an electronic device that could benefit from protection against ESD or other overvoltage events.

Examples of such connectors include a power connector, a USB connector, an Ethernet cable connector, an HDMI connector, or any other connector that facilitates serial, parallel or other types of data, signal or power transmission. In such an embodiment, a cable attached to such an electronic device could provide both its underlying functionality (e.g., data communications) and ESD protection.

[00299] 12. Conclusion.

[00300] This specification describes in detail various embodiments and implementations of the present invention, and the present invention is open to additional embodiments and implementations, further modifications, and alternative constructions. There is no intention in this patent to limit the invention to the particular embodiments and implementations disclosed; on the contrary, this patent is intended to cover all modifications, equivalents and alternative embodiments and implementations that fall within the scope of the claims.

[00301] As used in this specification, a set means any group of one, two or more items. Analogously, a subset means, with respect to a group of N items, any set of such items consisting of N-l or less of the respective items.

[00302] As used in this specification, the terms "include," "including," "for example," "exemplary," "e.g.," and variations thereof, are not intended to be terms of limitation, but rather are intended to be followed by the words "without limitation" or by words with a similar meaning. Definitions in this specification, and all headers, titles and subtitles, are intended to be descriptive and illustrative with the goal of facilitating comprehension, but are not intended to be limiting with respect to the scope of the inventions as recited in the claims. Each such definition is intended to also capture additional equivalent items, technologies or terms that would be known or would become known to a person of average skill in this art as equivalent or otherwise interchangeable with the respective item, technology or term so defined. Unless otherwise required by the context, the verbs "may," "might," "can," or "could" indicate a possibility that the respective action, step, implementation or event may be achieved or may take place, but is not intended to establish a limiting requirement that such action, step, implementation or event must be achieved or take place, or that the respective action, step or implementation must be achieved or take place in the exact manner described.

Claims

CLAIMS WHAT IS CLAIMED IS:

1. A system for protecting an electronic component against an electrostatic discharge (ESD) pulse, the system comprising:

a voltage switchable dielectric material (VSDM) component incorporated in a substrate, the VSDM component comprising a VSDM adapted to switch from a substantially nonconductive state to a substantially conductive state in response to voltage that exceeds a characteristic voltage of the VSD material; and

a component-based impedance element incorporated in an electronic component, the electronic component attached to the substrate;

wherein the component-based impedance element is adapted to operate together with the VSDM component to protect the electronic component against the ESD pulse.

2. The system of claim 1, wherein the electronic component further comprises an ESD stage, and the component-based impedance is in direct or indirect electrical contact with the ESD stage.

3. The system of claim 1, wherein the component-based impedance is incorporated in a pin, lead or other interfacing connector of the electronic component.

4. The system of claim 1, wherein the component-based impedance is incorporated in a redistribution layer of the electronic component.

5. The system of claim 1, wherein the electronic component is a stacked component, and wherein the component-based impedance is incorporated in a pin, lead, wire, or other connector disposed inside the stacked component.

6. The system of claim 1, wherein the component-based impedance comprises a resistor, an inductor, a capacitor, a ferroic circuit element, a ferroic circuit element that comprises VSDM, a diode, a transistor, a filter, a passive circuit element, an active circuit element, or a layered interconnect with a non-negligible impedance.

7. The system of claim 1, wherein the component-based impedance comprises a resistive material, a partially-conductive polymer, a metal film resistor, a film coated with nickel chromium, a metal oxide film, a carbon-composition resistive material, a carbon film, a thin film resistor, or a thick film resistor.

8. The system of claim 1, wherein the electronic component is a semiconductor chip, an integrated circuit component, a microprocessor, a controller, a memory chip, a radio frequency circuit, a baseband processor, a system on a chip (SOC), a flip chip, a light emitting diode (LED), an LED array, an LCD display, and LED display, an OLED display, or a MEMS chip.

9. The system of claim 1, wherein the substrate and the electronic component are comprised in an electronic device, and wherein the electronic device is a mobile phone, an electronic tablet, an electronic reader, a mobile computer, a laptop, a desktop computer, a server computer, a television set, a video display, a music player, personal health management device, a light emitting diode (LEDs), a device comprising at least one LED, or a lighting module.

10. The system of claim 1, wherein the substrate is a printed circuit board (PCB), a single layer of a PCB, a structure comprising a set of multiple layers of a PCB, the package of a semiconductor device, an LED substrate, an integrated circuit (IC) substrate, or an interposer.