TWI503940B - 半導體元件及其形成方法 - Google Patents

半導體元件及其形成方法 Download PDF

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TWI503940B
TWI503940B TW101122934A TW101122934A TWI503940B TW I503940 B TWI503940 B TW I503940B TW 101122934 A TW101122934 A TW 101122934A TW 101122934 A TW101122934 A TW 101122934A TW I503940 B TWI503940 B TW I503940B
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Taiwan
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contact
package
conductive
layer
semiconductor device
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TW101122934A
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TW201332072A (zh
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Chun Cheng Lin
Chung Shi Liu
Kuei Wei Huang
Cheng Ting Chen
Wei Hung Lin
Ming Da Cheng
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Taiwan Semiconductor Mfg Co Ltd
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Description

半導體元件及其形成方法
本發明係有關於半導體元件的封裝，特別有關於調整接合高度的結構及方法。
一般而言，在層疊封裝(Package on Package；PoP)系統中，個別的半導體晶片可分別地封裝(或者在每個分開的封裝體中具有多個半導體晶片)，然後這些分開的封裝體可以疊放在一起並互相連接，使得在這些分開的封裝體中個別的半導體晶片可以被整合在一起，以執行所需的任務。這些個別的封裝體可以互相電性連接，例如使用接觸凸塊。
接觸凸塊可藉由最初在封裝體的基底上形成一層接觸材料而形成，於接觸材料層形成後，可對接觸材料層進行回焊，藉由回焊提高接觸材料的溫度，使得接觸材料至少部分地被液化，此部分的液化讓接觸材料可使用自身的表面張力而拉成球狀。
於接觸凸塊形成後，可將一個封裝體的接觸凸塊放置成與另一封裝體的接觸墊接觸。此外，還可以將接觸凸塊放置成與形成在其他封裝體上的其他類型或形式的接點接觸。待接觸凸塊與適當的位置對齊放置，可再度回焊並且再加熱接觸凸塊，使得接觸凸塊再度部分地被液化，並且讓接觸凸塊部分地流動，藉此在兩個封裝體之間形成架橋。待接觸凸塊冷卻下來並且再固化(resolidify)後，兩個封裝體之間的接觸凸塊會完全地互相接合，在接觸凸塊之間的接合會讓接觸凸塊之間產生物理性的連接，並且也會讓 接觸凸塊之間產生電性的連接，使得信號與電力從一個封裝體跨越至另一封裝體，進而讓兩個封裝體互相整合在一起並且一起執行工作。
依據一實施例，提供半導體元件，此半導體元件包括第一封裝體，第一接點位於第一封裝體的第一側上，並且第二接點也位於第一封裝體的第一側上，第一後接觸材料設置於第一接點之上，但不設置於第二接點之上。
依據另一實施例，提供半導體元件，此半導體元件包括第一接點與第二接點設置於第一封裝體的第一側上，導電柱從第一接點開始延伸，但第二接點沒有導電柱延伸。
依據又另一實施例，提供形成半導體元件的方法，此方法包括在第一封裝體上形成第一接點與第二接點，藉由在第一接點上方形成後接觸材料，以調整第一接點相對於第二接點的高度。
為了讓本發明之上述目的、特徵、及優點能更明顯易懂，以下配合所附圖式，作詳細說明如下，除非說明中特別指出，在不同圖式中相對應的數字與符號通常與其對應的部分有關聯，這些圖式的描繪是為了清楚說明與各種實施例有關的特徵，因此圖式不需按尺寸比例繪製。
以下詳細討論各種實施例之製造與使用，然而，可以理解的是，這些實施例提供了許多可應用的發明概念，其可以在各種特定背景中實施，在此所討論的特定實施例僅用於說明製造與使用本發明的特定方式，並非用於限定本 發明的範圍。
以下描述的實施例係關於在特定背景中的實施例，其稱為層疊封裝(PoP)構造的接點(contact)結構，但是這些實施例也可以應用在其他封裝構造與其他接點結構上。
參閱第1圖，其顯示第一封裝體100具有基底101，貫穿基底的導通孔(through substrate vias)103從基底101的第一側102延伸至基底101的第二側104。第一重分佈層(redistribution layer)105、第一接觸墊(contact pad)109、第二接觸墊108、第一鈍態層(passivation layer)110以及第一凸塊下金屬層(under-bump metallurgies；UBMs)112可位於基底101的第一側102上。第二重分佈層111、第三接點117、第二凸塊下金屬層(UBMs)121以及第二鈍態層119可位於基底101的第二側104上。
第一封裝體100的基底101可以是例如摻雜或未摻雜的矽基底，或者是絕緣體上的矽(silicon-on-insulator；SOI)基底之主動層，藉此對第一封裝體100提供支撐作用。然而，基底101也可以是陶瓷基底、高分子基底、中介層(interposer)、或任何其他可提供合適的保護作用之基底，以及/或所需的扇出(fan-out)基底，上述這些材料以及任何其他合適的材料都可以用在基底101。
貫穿基底的導通孔103可從基底101的第一側102延伸至基底101的第二側104，並且可藉由任何適當的方法形成貫穿基底的導通孔103。例如，在一實施例中，可藉由例如一個或多個蝕刻製程、銑削(milling)、雷射技術或類似的技術形成部分地穿過基底101的開口，以擴散阻障 層、黏著層、隔絕層或類似的層作為這些開口的內襯，並且以導電材料填充這些開口。較佳為，擴散阻障層(未繪出)包括一層或多層的TaN、Ta、TiN、Ti、CoW或類似的材料，導電材料包括銅、鎢、鋁、銀及前述之組合，或者類似的材料，藉此形成貫穿基底的導通孔103。在一實施例中，貫穿基底的導通孔103具有TaN的擴散阻障層，並且利用電化學電鍍製程填充銅，其中晶種層(seed layer)的沈積有助於導電填充材料的形成。
在另一實施例中，可先以介電材料填充開口，在研磨基底101的背面之後，可經由蝕刻製程除去介電材料，於介電材料移除之後，可使用導電材料例如銅取代介電材料，以形成貫穿基底的導通孔103。另外，也可使用其他的方法與材料形成貫穿基底的導通孔103。
第一重分佈層105可在基底101的第一側102上形成，並且與貫穿基底的導通孔103電性連接，第一重分佈層105可從貫穿基底的導通孔103開始延伸，並且在任何所需的地方放置第一接觸墊109(如後續的討論)。可使用第一重分佈層105擴大貫穿基底的導通孔103在扇出圖案(fan-out pattern)中的間距，或者縮減貫穿基底的導通孔103的間距。
可使用常見用於形成積體電路內的內連線線路(interconnect lines)的方法形成第一重分佈層105，第一重分佈層105較佳為包括至少一層由金屬形成的導電層，例如鋁、銅、鎢、鈦及前述之組合。此至少一層的導電層可藉由在晶種層上電鍍金屬，然後蝕刻除去不需要的部分而 形成，留下此至少一層的導電層，其厚度可介於約2μm與約30μm之間，較佳的寬度約為5μm。於此至少一層的導電層形成後，可在此至少一層的導電層之上形成介電材料，並且可形成貫穿介電材料的導通孔，以提供到此至少一層的導電層之電性通道。另外，也可使用其他材料與製程，例如習知的鑲嵌製程(damascene process)來形成第一重分佈層105。
在此技術領域中具有通常知識者當可瞭解，第一重分佈層105可以是單層的導電材料，或者可以是多層的導電材料，其取決於第一重分佈層105所需的特性。例如，可以在上述形成的第一重分佈層105鍍上另一導電材料，例如金或鉻，藉此對後續形成的連接器(如下所述)提供良好的黏著力，此鍍層可經由例如化學氣相沈積(CVD)製程完成。
可形成第一接觸墊109與第二接觸墊108，作為第一重分佈層105的外部接點，在一實施例中，可使用第二接觸墊108作為從第一封裝體100至第二封裝體400(在第1圖中未繪出，請參閱如下述討論的第4圖)的外部接點。此外，可使用第一接觸墊109作為從第一封裝體100至第三封裝體500(在第1圖中也未繪出，請參閱下述說明及討論的第5圖)的外部接點。
第一接觸墊109與第二接觸墊108可由導電材料形成，例如鋁，但是其他合適的材料，例如銅、鎢或類似的材料也可使用。可使用例如化學氣相沈積(CVD)製程形成第一接觸墊109與第二接觸墊108，但是其他合適的材料 與方法也可使用。一旦用於形成第一接觸墊109與第二接觸墊108的材料沈積之後，可使用例如微影遮罩與蝕刻製程形成第一接觸墊109。
於第一接觸墊109與第二接觸墊108形成之後，可形成第一鈍態層110來隔絕與保護第一接觸墊109和第二接觸墊108。在一實施例中，第一鈍態層110可由高分子例如聚亞醯胺(polyimide)形成，或者可由其他材料，例如氧化矽、氮化矽、低介電常數介電材料、超低低介電常數介電材料、前述之組合，以及類似的材料形成。第一鈍態層110的厚度可介於約2μm與約15μm之間，例如約為5μm。
於第一鈍態層110形成後，可形成第一凸塊下金屬層(UBMs)112與第一接觸墊109和第二接觸墊108接觸，在一實施例中，先形成貫穿第一鈍態層110之第一UBMs 112的開口，例如可使用微影遮罩與蝕刻製程形成此開口，當至少一部份的第一接觸墊109與第二接觸墊108暴露出來後，可形成第一凸塊下金屬層(UBMs)112與第一接觸墊109和第二接觸墊108電性接觸。第一UBMs 112可包括三層導電材料，例如一層鈦、一層銅以及一層鎳。然而，在此技術領域中具有通常知識者當可瞭解，各種材料與層的多種合適的排列，例如鉻/鉻-銅合金/銅/金的排列、鈦/鈦鎢/銅的排列、或者銅/鎳/金的排列，都適用於形成第一UBMs 112，可用在第一UBMs 112的任何合適的材料或材料層都包含在本發明之實施例的範圍內。
可在第一接觸墊109與第二接觸墊108之上形成每一 層UBM而產生第一UBMs 112，可使用鍍層製程，例如電化學電鍍形成每一層UBM，然而，也可使用其他的製程，例如濺鍍、蒸鍍或電漿增強型化學氣相沈積(PECVD)製程形成每一層UBM，其係由所需的材料決定。第一UBMs 112的厚度可介於約0.7μm與約10μm之間，例如約為5μm。一旦形成所需的鍍層後，鍍層的一部分可經由合適的微影遮罩與蝕刻製程移除，以除去不需要的材料，並留下所需形狀的第一UBMs 112，例如圓形、八邊形、方形或矩形的形狀，然而，也可以形成任何所需的形狀。
在基底101的第二側104上可形成第二重分佈層111、第三接點117、第二鈍態層119以及第二凸塊下金屬層(UBMs)121，以提供從貫穿基底的導通孔103至外部元件(第1圖中未繪出)的連接。在一實施例中，第二重分佈層111、第三接點117、第二鈍態層119以及第二凸塊下金屬層(UBMs)121可分別採用與上述之第一重分佈層105、第一接觸墊109、第一鈍態層110以及第一凸塊下金屬層(UBMs)112類似的方式與類似的材料形成，然而，第二重分佈層111、第三接點117、第二鈍態層119以及第二凸塊下金屬層(UBMs)121也可使用不同的方法與材料形成。
於第二UBMs 121在基底101的第二側104上形成後，可在第二UBMs 121上方形成第一導電連接器123，第一導電連接器123可以是接觸凸塊，並且其材料可包括錫或其他合適的材料，例如銀、無鉛的錫、或銅。在一實施例中，第一導電連接器123為錫焊料凸塊，可先經由常用的方法例如蒸鍍、電鍍、印刷、焊料轉移(solder transfer)、焊球植 入(ball placement)等方法形成錫層，錫層的厚度例如約為100μm，待錫層在結構上形成後，接著可進行回焊將錫層材料塑造成所需的凸塊形狀，藉此形成第一導電連接器123。
然而，本發明之實施例並不限於上述的接觸凸塊，任何其他合適的接觸連接器，例如銅連接器、導電柱(例如銅柱)、或者任何其他種類的連接器也可使用，所有合適的連接器都包含在本發明之實施例的範圍內。
第2圖顯示在第一UBMs 112上形成後接觸(post-contact)材料201，在一實施例中，可使用後接觸材料201來調整第一UBMs 112與第二導電連接器301(在第2圖中也未繪出，但可參閱下述說明及討論的第3圖)之間接合的高度。在一實施例中，第二導電連接器301為焊球，後接觸材料201可以是高熔點的預焊料(pre-solder)，例如SnCu、SnAg、SnAgCu、SnAu、前述之組合或類似的材料。後接觸材料201可印刷在第一UBMs 112上，但是其他製程，例如電鍍或無電電鍍也可用來形成後接觸材料201。
在一實施例中，後接觸材料201可具有第一厚度T1 ，第一厚度T1 足夠大到可以降低或消除在第一UBMs 112與第二導電連接器301之間冷接(cold joint)的可能性。在一實施例中，第一厚度T1 可介於約10μm與約200μm之間，例如約為100μm。然而，這些厚度僅為舉例說明，第一厚度T1 並不限於這些厚度範圍，任何可用於防止冷接發生的合適厚度都可使用。
第3圖顯示在後接觸材料201形成後，可在後接觸材 料201上形成第二導電連接器301。在一實施例中，第二導電連接器301可以與第一導電連接器123相似，並且可以是導電凸塊，例如焊料凸塊，並且第二導電連接器301的材料包括錫或其他合適的材料，例如銀、無鉛的錫或銅。此外，第二導電連接器301的材料也可以是SnZn、SnBi、SnIn、SnCd、前述之組合或類似的材料，並且第二導電連接器301的熔點可低於後接觸材料201的熔點。在一實施例中，第二導電連接器301可以是焊錫凸塊，可先經由常用的方法例如蒸鍍、電鍍、印刷、焊料轉移、焊球植入等方法形成錫層，錫層的厚度可約為100μm，待錫層在結構上形成後，可進行回焊將錫層材料塑造成所需的凸塊形狀，以形成第二導電連接器301。
第4圖顯示第二封裝體與第一封裝體100接合及密封，在一實施例中，第二封裝體400可以是半導體晶片的封裝體(在第4圖中並未獨立繪出)，第二封裝體400具有各種主動與被動元件(如電晶體、電阻器、電容器、電感器及類似的元件)形成在其上，以產生功能元件。此外，半導體晶片也可包括在主動與被動元件之上，交替排列的導電與介電層，藉此讓各種元件之間產生內連接與隔絕，並形成功能電路。
為了將功能電路連接至第一封裝體100，可將第一晶片封裝在第二封裝體400內，並且第二封裝體400可具有第四接點403，以連接第二封裝體400與在第一封裝體100上的第二接觸墊108。第四接點403可以由導電材料形成，例如銅，並且第四接點403可以是例如導電柱的形狀，可 使用例如微影與鍍層製程形成第四接點403。第四接點403與在第二封裝體400底下的導電層以及在第二封裝體400內的半導體晶片之主動與被動元件產生電性接觸，藉此對這些主動與被動元件提供外部接點。然而，第四接點403並不限於銅柱，任何合適類型的接點，例如鋁接觸墊、焊料凸塊、打線接合墊(wire bond pads)或類似的接點也可使用。
可使用例如接合製程將第四接點403(位於第二封裝體400上)連接至第二接觸墊108(位於第一封裝體100上)，在一實施例中，接合製程可包括將第一連接材料405，例如焊料形成或放置在第四接點403、第二接觸墊108或兩者上，然後可讓第四接點403與第二接觸墊108互相接觸(具有第一連接材料405在兩者之間)，並將第一連接材料405回焊，藉此將第二接觸墊108與第四接點403接合，並且也將第二封裝體400接合至第一封裝體100。
於第二封裝體400接合至第一封裝體100後，可使用密封材料407將此結構密封，密封材料407例如為模塑料(molding compound)、聚亞醯胺、聚苯硫醚(poly(phenylene sulfide)；PPS)、聚醚醚酮(polyether ether ketone；PEEK)、聚醚石風(poly(ether sulfone)；PES)、耐熱結晶樹脂(heat resistant crystal resin)、前述之組合或類似的材料。在一實施例中，接合後的第一封裝體100和第二封裝體400可放置在模壓腔(molding chamber)(未繪出)中，並且可將密封材料407注入或放置在模壓腔內，模壓腔將密封材料407塑造成所需的形狀，藉此將第二封裝體400密封在第一封裝 體100上，並對第二封裝體400提供支撐與保護。待密封材料407放置在適當的地方後，可將密封材料407固化，使得密封材料407變硬以提供理想的保護作用。精確的固化製程至少部份取決於密封材料407所選擇的特定材料，在一實施例中，選擇模塑料做為密封材料407，可經由例如加熱密封材料407至介於約100℃與約130℃之間的製程而發生固化，例如加熱至約125℃持續約60秒至約3000秒，例如約600秒。此外，密封材料407也可包含起始劑以及/或催化劑，藉此更準確地控制固化製程。
第5圖顯示將第三封裝體500放置並接合至第一封裝體100上，在一實施例中，第三封裝體500與第二封裝體400類似，為半導體晶片的封裝體，在其上可以有各種主動與被動元件(在第5圖中未個別繪出)形成。第三封裝體500可具有第五接點501，第五接點501可電性連接至第三封裝體500內的半導體晶片之主動與被動元件，第五接點501可由與第四接點403(參閱以上第4圖所述)類似的製程與材料形成，但是第五接點501也可以由不同的材料與不同的製程形成。
第三封裝體500可採用與上述第4圖所述之接合製程類似的方式接合至第一封裝體100，例如，接合製程可包括將第五接點501放置成與第一接觸墊109互相接觸(具有第二導電連接器301在兩者之間)，以及將第二導電連接器301回焊，藉此將第一接觸墊109接合至第五接點501，並且也將第三封裝體500接合至第一封裝體100。
第6圖顯示另一實施例，其中使用導電柱601代替後 接觸材料201來控制接合高度，在此實施例中，可先在第一鈍態層110之上形成光阻(未繪出)，光阻的厚度大於約20μm，或者甚至大於約60μm，接著將光阻圖案化，暴露出部分的第一鈍態層110，導電柱601可由此處延伸而形成，於光阻圖案化後，可使用光阻作為遮罩，移除第一鈍態層110需要移除的部分，藉此暴露出第一接觸墊109的一部份，導電柱601將與此部分接觸。
在第一鈍態層110圖案化之後，導電柱601可在第一鈍態層110與光阻兩者的開口內形成。導電柱601可由導電材料形成，例如銅，但是其他導電材料，例如鎳、金、金屬合金、前述之組合或類似的材料也可使用。此外，導電柱601可使用例如電鍍製程形成，藉由電鍍製程，電流通過第一接觸墊109的導電部分，此導電部分為導電柱601需要形成的地方，而且第一接觸墊109浸泡在溶液中，在開口內的溶液與電流所產生的沈積物例如銅，將會充填以及/或過填充(overfill)光阻與第一鈍態層110的開口，藉此形成導電柱601，在開口外面多餘的導電材料可使用例如化學機械研磨(chemical mechanical polish；CMP)除去。
在導電柱601形成之後，可經由例如灰化(ashing)製程除去光阻，其係將光阻的溫度提高，直到光阻分解並且可以被除去。在移除光阻之後，導電柱601從第一鈍態層110的表面開始延伸第一距離d1 ，第一距離d1 介於約10mm至約300mm之間，例如約為180mm。
然而，在此技術領域中具有通常知識者當可瞭解，上述形成導電柱601的製程僅用於描述一實施例，並非用於 限定本發明之實施例在此製程，在此所描述的製程僅用於說明一實施例，任何可形成導電柱601的合適製程都可使用。例如，也可使用以下的方式形成導電柱601：先形成第一鈍態層110至大於其最終厚度的一厚度，在第一鈍態層110的開口內形成導電柱601，然後將第一鈍態層110的上方部分移除，使得導電柱601從第一鈍態層110的表面開始延伸，所有合適的製程都包含在本發明之實施例的範圍內。
第7圖顯示可選擇性地在導電柱601上形成阻障層701，阻障層701可以是錫或其他導電材料，並且可藉由例如浸錫(immersion Sn；IT)製程、有機保焊劑(organic solderability preservative；OSP)製程、自組性單層薄膜(self-assembled monolayer；SAM)製程、無電鍍鎳無電鍍鈀浸金(electroless nickel electroless palladium immersion gold；ENEPIG)製程、前述之組合或類似的製程形成阻障層701，阻障層701的厚度可介於約0.1μm與約10μm之間，例如約為0.5μm。
第8圖顯示另一實施例，其中導電柱601選擇性地以導電材料801覆蓋。在一實施例中，導電材料801可以是非流動的焊料蓋(non-flow solder cap)，例如SnZn、SnBi、SnIn、SnCd或類似的材料，可藉由電鍍、無電電鍍、浸鍍(immersion plating)或類似的方式形成非流動的焊料蓋，導電材料801的厚度可介於約1μm與約100μm之間，例如約為20μm。
此外，導電材料801還可以是可流動的材料，例如焊 料。在此實施例中，導電材料801可與第一導電連接器123的材料類似，例如為藉由鍍層與回焊製程形成的錫焊料凸塊。然而，導電材料801也可以是任何合適的導電材料。
第9圖顯示將第二封裝體400與第三封裝體500放置並接合至第一封裝體100上，在一實施例中，第二封裝體400與第三封裝體500可使用類似上述第4圖與第5圖所討論的方法與製程接合至第一封裝體100上，例如在壓力下將導電材料對齊排列及回焊，以接合第二封裝體400和第三封裝體500至第一封裝體100上。然而，任何適用於接合第二封裝體400和第三封裝體500至第一封裝體100的方法也可使用。
雖然本發明已揭露較佳實施例如上，然其並非用以限定本發明，在此技術領域中具有通常知識者當可瞭解，在不脫離本發明之精神和範圍內，當可做些許更動與潤飾。例如，在不脫離本發明實施例的範圍內，可以修改形成各種結構的方法與材料。此外，在不脫離本發明實施例的範圍內，可以改變第一封裝體上接觸墊的位置，以配合第一封裝體的設計需求。因此，本發明之保護範圍當視後附之申請專利範圍所界定為準。
100‧‧‧第一封裝體
101‧‧‧基底
102‧‧‧基底的第一側
103‧‧‧貫穿基底的導通孔
104‧‧‧基底的第二側
105‧‧‧第一重分佈層
108‧‧‧第二接觸墊
109‧‧‧第一接觸墊
110‧‧‧第一鈍態層
111‧‧‧第二重分佈層
112‧‧‧第一凸塊下金屬層
117‧‧‧第三接點
119‧‧‧第二鈍態層
121‧‧‧第二凸塊下金屬層
123‧‧‧第一導電連接器
201‧‧‧後接觸材料
301‧‧‧第二導電連接器
400‧‧‧第二封裝體
403‧‧‧第四接點
405‧‧‧第一連接材料
407‧‧‧密封材料
500‧‧‧第三封裝體
501‧‧‧第五接點
601‧‧‧導電柱
701‧‧‧阻障層
801‧‧‧導電材料
T1 ‧‧‧後接觸材料的第一厚度
d1 ‧‧‧導電柱從第一鈍態層開始延伸的第一距離
第1圖係顯示依據一實施例，具有第一接點和第二接點的第一封裝體之剖面示意圖。
第2圖係顯示依據一實施例，在第一接點上形成後接觸材料之剖面示意圖。
第3圖係顯示依據一實施例，在後接觸材料上形成接 點之剖面示意圖。
第4圖係顯示依據一實施例，將第二封裝體接合至第一封裝體上之剖面示意圖。
第5圖係顯示依據一實施例，將第三封裝體接合至第一封裝體上之剖面示意圖。
第6圖係顯示依據一實施例，在接觸墊上形成導電柱之剖面示意圖。
第7圖係顯示依據一實施例，形成阻障層至導電柱上之剖面示意圖。
第8圖係顯示依據一實施例，在導電柱上形成凸塊之剖面示意圖。
第9圖係顯示依據一實施例，將第二封裝體與第三封裝體接合至第一封裝體上之剖面示意圖。
100‧‧‧第一封裝體
101‧‧‧基底
102‧‧‧基底的第一側
103‧‧‧貫穿基底的導通孔
104‧‧‧基底的第二側
105‧‧‧第一重分佈層
108‧‧‧第二接觸墊
109‧‧‧第一接觸墊
110‧‧‧第一鈍態層
111‧‧‧第二重分佈層
112‧‧‧第一凸塊下金屬層
117‧‧‧第三接點
119‧‧‧第二鈍態層
121‧‧‧第二凸塊下金屬層
123‧‧‧第一導電連接器
201‧‧‧後接觸材料
T1 ‧‧‧後接觸材料的第一厚度

Claims (10)

  1. 一種半導體元件，包括：一第一封裝體，具有一第一側；一第一接點和一第二接點，位於該第一側；以及一第一後接觸材料，設置於該第一接點之上，但不設置於該第二接點之上。
  2. 如申請專利範圍第1項所述之半導體元件，更包括一導電連接器與該第一後接觸材料接觸，以及一第二封裝體與該第二接點接合，其中相較於該第二封裝體，該導電連接器更從該第一封裝體延伸。
  3. 如申請專利範圍第1項所述之半導體元件，其中該第一後接觸材料為高熔點的預焊料，包括SnCu、SnAg、SnAgCu或SnAu。
  4. 如申請專利範圍第1項所述之半導體元件，其中該第一後接觸材料的厚度範圍介於10μm與200μm之間。
  5. 一種半導體元件，包括：一第一接點和一第二接點，設置於一第一封裝體的一第一側上；以及一導電柱，從該第一接點開始延伸，其中該第二接點上沒有一導電柱。
  6. 如申請專利範圍第5項所述之半導體元件，更包括一覆蓋物設置於該導電柱上，其中該覆蓋物包括可流動的焊料或非流動的焊料。
  7. 如申請專利範圍第5項所述之半導體元件，更包括一第二封裝體與該第二接點接合，其中該第二封裝體不與 該導電柱接合，以及複數個導通孔穿過該第一封裝體至該第一封裝體的一第二側。
  8. 一種形成半導體元件的方法，包括：在一第一封裝體上形成一第一接點和一第二接點，其中該第一接點和該第二接點設置於該第一封裝體的一第一側上；以及在該第一接點上方形成一後接觸材料，以調整該第一接點相對於該第二接點的一高度。
  9. 如申請專利範圍第8項所述之形成半導體元件的方法，更包括將一第二封裝體接合至該第二接點上，但不接合至該第一接點上，以及密封該第二封裝體。
  10. 如申請專利範圍第8項所述之形成半導體元件的方法，更包括形成一焊料凸塊在該後接觸材料上，其中該後接觸材料的熔點高於該焊料凸塊的熔點。
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Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2485579A4 (en) * 2009-10-07 2014-12-17 Rain Bird Corp IRRIGATION CONTROL ON VOLUME BUDGET BASE
US9418947B2 (en) 2012-02-27 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming connectors with a molding compound for package on package
US8836117B2 (en) * 2012-10-16 2014-09-16 Stmicroelectronics Asia Pacific Pte. Ltd. Electronic device having a contact recess and related methods
CN103035604B (zh) 2012-12-17 2014-07-16 矽力杰半导体技术(杭州)有限公司 一种倒装芯片封装结构及其制作工艺
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9379078B2 (en) * 2013-11-07 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. 3D die stacking structure with fine pitches
TWI556379B (zh) 2014-01-02 2016-11-01 矽品精密工業股份有限公司 半導體封裝件及其製法
US9583420B2 (en) 2015-01-23 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufactures
US10971476B2 (en) 2014-02-18 2021-04-06 Qualcomm Incorporated Bottom package with metal post interconnections
US9281297B2 (en) 2014-03-07 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Solution for reducing poor contact in info packages
US9449947B2 (en) 2014-07-01 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package for thermal dissipation
CN105261611B (zh) * 2015-10-15 2018-06-26 矽力杰半导体技术(杭州)有限公司 芯片的叠层封装结构及叠层封装方法
US9620465B1 (en) * 2016-01-25 2017-04-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dual-sided integrated fan-out package
US9748206B1 (en) * 2016-05-26 2017-08-29 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional stacking structure and manufacturing method thereof
US9812381B1 (en) * 2016-05-31 2017-11-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US10163798B1 (en) * 2017-12-22 2018-12-25 Intel Corporation Embedded multi-die interconnect bridge packages with lithotgraphically formed bumps and methods of assembling same
US11430724B2 (en) * 2017-12-30 2022-08-30 Intel Corporation Ultra-thin, hyper-density semiconductor packages
US10658333B2 (en) * 2018-07-31 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of fabricating the same
KR20210106588A (ko) * 2020-02-19 2021-08-31 삼성전자주식회사 반도체 패키지
TWI838968B (zh) * 2022-11-17 2024-04-11 欣興電子股份有限公司 防止擴散的基板結構和其製作方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100237495A1 (en) * 2009-03-17 2010-09-23 Stats Chippac, Ltd. Semiconductor Device and Method of Providing Z-Interconnect Conductive Pillars with Inner Polymer Core
US20120012990A1 (en) * 2010-07-16 2012-01-19 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Protective Layer Over Exposed Surfaces of Semiconductor Die

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3004074A (en) 1954-08-03 1961-10-10 Universal Oil Prod Co Condensation of polyhalocycloalkadienes with cyclooctatetraene
CA2455024A1 (en) * 2003-01-30 2004-07-30 Endicott Interconnect Technologies, Inc. Stacked chip electronic package having laminate carrier and method of making same
JP4204989B2 (ja) * 2004-01-30 2009-01-07 新光電気工業株式会社 半導体装置及びその製造方法
JP4441328B2 (ja) * 2004-05-25 2010-03-31 株式会社ルネサステクノロジ 半導体装置及びその製造方法
US8669637B2 (en) * 2005-10-29 2014-03-11 Stats Chippac Ltd. Integrated passive device system
US8836146B2 (en) * 2006-03-02 2014-09-16 Qualcomm Incorporated Chip package and method for fabricating the same
JP5003260B2 (ja) 2007-04-13 2012-08-15 日本電気株式会社 半導体装置およびその製造方法
US7911059B2 (en) * 2007-06-08 2011-03-22 SeniLEDS Optoelectronics Co., Ltd High thermal conductivity substrate for a semiconductor device
KR20090050810A (ko) * 2007-11-16 2009-05-20 삼성전자주식회사 접합 신뢰성이 향상된 적층형 반도체 패키지
US8039303B2 (en) * 2008-06-11 2011-10-18 Stats Chippac, Ltd. Method of forming stress relief layer between die and interconnect structure
US8004093B2 (en) * 2008-08-01 2011-08-23 Stats Chippac Ltd. Integrated circuit package stacking system
US8350377B2 (en) * 2008-09-25 2013-01-08 Wen-Kun Yang Semiconductor device package structure and method for the same
CN101764127B (zh) * 2008-12-23 2012-01-04 日月光封装测试(上海)有限公司 无外引脚的半导体封装体及其堆迭构造
JP2011009514A (ja) * 2009-06-26 2011-01-13 Renesas Electronics Corp 半導体装置の製造方法
US20100327419A1 (en) * 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
US8440915B2 (en) * 2009-10-30 2013-05-14 Sanyo Electric Co., Ltd. Device mounting board and semiconductor module
US8241952B2 (en) * 2010-02-25 2012-08-14 Stats Chippac, Ltd. Semiconductor device and method of forming IPD in fan-out level chip scale package
KR20120031697A (ko) * 2010-09-27 2012-04-04 삼성전자주식회사 패키지 적층 구조 및 그 제조 방법
US8304867B2 (en) * 2010-11-01 2012-11-06 Texas Instruments Incorporated Crack arrest vias for IC devices
US9111930B2 (en) * 2013-03-12 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package on-package with cavity in interposer
US8916981B2 (en) * 2013-05-10 2014-12-23 Intel Corporation Epoxy-amine underfill materials for semiconductor packages

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100237495A1 (en) * 2009-03-17 2010-09-23 Stats Chippac, Ltd. Semiconductor Device and Method of Providing Z-Interconnect Conductive Pillars with Inner Polymer Core
US20120012990A1 (en) * 2010-07-16 2012-01-19 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Protective Layer Over Exposed Surfaces of Semiconductor Die

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