TWI498955B - A method for manufacturing a semiconductor wafer with a spin - die tape and an adhesive layer - Google Patents

A method for manufacturing a semiconductor wafer with a spin - die tape and an adhesive layer Download PDF

Info

Publication number
TWI498955B
TWI498955B TW100104469A TW100104469A TWI498955B TW I498955 B TWI498955 B TW I498955B TW 100104469 A TW100104469 A TW 100104469A TW 100104469 A TW100104469 A TW 100104469A TW I498955 B TWI498955 B TW I498955B
Authority
TW
Taiwan
Prior art keywords
layer
semiconductor wafer
dicing
adhesion
starting point
Prior art date
Application number
TW100104469A
Other languages
Chinese (zh)
Other versions
TW201140676A (en
Inventor
Masatoshi Ishimaru
Original Assignee
Sekisui Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sekisui Chemical Co Ltd filed Critical Sekisui Chemical Co Ltd
Publication of TW201140676A publication Critical patent/TW201140676A/en
Application granted granted Critical
Publication of TWI498955B publication Critical patent/TWI498955B/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67132Apparatus for placing on an insulating substrate, e.g. tape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68336Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H01L2221/68386Separation by peeling
    • H01L2221/6839Separation by peeling using peeling wedge or knife or bar
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/274Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2743Manufacturing methods by blanket deposition of the material of the layer connector in solid form
    • H01L2224/27436Lamination of a preform, e.g. foil, sheet or layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Dicing (AREA)
  • Adhesive Tapes (AREA)
  • Die Bonding (AREA)

Description

切晶-黏晶帶及附帶黏著劑層之半導體晶片之製造方法Method for manufacturing dicing-bonded ribbon and semiconductor wafer with adhesive layer

本發明係關於一種用以獲得附帶黏著劑層之半導體晶片,且用以對該附帶黏著劑層之半導體晶片進行黏晶之切晶-黏晶帶、以及使用該切晶-黏晶帶之附帶黏著劑層之半導體晶片之製造方法。BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a dicing-adhesive tape for use in obtaining a semiconductor wafer with an adhesive layer and for bonding a semiconductor wafer with an adhesive layer, and the use of the dicing-adhesive tape A method of manufacturing a semiconductor wafer of an adhesive layer.

自半導體晶圓切取半導體晶片時,係使用稱為預先切晶法之切晶法。關於預先切晶法之一例,例如揭示於下述專利文獻1。When a semiconductor wafer is cut from a semiconductor wafer, a dicing method called a pre-cut method is used. An example of the pre-cutting method is disclosed, for example, in Patent Document 1 below.

於預先切晶法中,首先於半導體晶圓之表面形成切口。其次,於形成有切口之半導體晶圓之表面黏附保護片。其後,將半導體晶圓之背面研磨至切口部分為止,使半導體晶圓之厚度變薄,並分割成各個半導體晶片。於分割成各個半導體晶片之分割後半導體晶圓之表面黏附有保護片。In the pre-cutting method, a slit is first formed on the surface of the semiconductor wafer. Next, a protective sheet is adhered to the surface of the semiconductor wafer on which the slit is formed. Thereafter, the back surface of the semiconductor wafer is polished to the slit portion, and the thickness of the semiconductor wafer is thinned and divided into individual semiconductor wafers. A protective sheet is adhered to the surface of the divided semiconductor wafer divided into individual semiconductor wafers.

又,為使藉由上述預先切晶法而獲得之各個半導體晶片容易地安裝於基板上,多係於半導體晶片之背面黏附黏晶層。為獲得該附帶黏晶層之半導體晶片,係使用包含黏晶層及切晶層之切晶-黏晶帶。Further, in order to easily mount the respective semiconductor wafers obtained by the above-described pre-crystallizing method on the substrate, the adhesion layer is adhered to the back surface of the semiconductor wafer. In order to obtain the semiconductor wafer with the viscous layer, a diced-bonded ribbon comprising a viscous layer and a dicing layer is used.

作為切晶-黏晶帶之一例,於下述專利文獻2中揭示有如下切晶-黏晶帶,即,於剝離片上積層有黏晶層,並以覆蓋該黏晶層之方式,於剝離片及黏晶層上積層有切晶層。黏晶層係於切晶後連同半導體晶片一併取出,用於半導體晶片之黏晶之層。為使切晶層容易地自剝離片剝離,於切晶層之外周緣設置有突出部。As an example of the dicing-bonding ribbon, Patent Document 2 below discloses a cleavage-bonding ribbon in which a viscous layer is laminated on a release sheet and is detached so as to cover the viscous layer. A layer of dicing is deposited on the sheet and the viscous layer. The die layer is taken out after dicing together with the semiconductor wafer for the layer of the die bond of the semiconductor wafer. In order to facilitate the peeling of the dicing layer from the peeling sheet, a protruding portion is provided on the periphery of the dicing layer.

[先行技術文獻][Advanced technical literature] [專利文獻][Patent Literature]

[專利文獻1]日本專利特開2006-245467號公報[Patent Document 1] Japanese Patent Laid-Open Publication No. 2006-245467

[專利文獻2]日本專利特開2005-116790號公報[Patent Document 2] Japanese Patent Laid-Open Publication No. 2005-116790

於使用專利文獻1所記載之切晶-黏晶帶獲得附帶黏晶層之半導體晶片時,將切晶層之突出部作為剝離起點,自剝離片剝離黏晶層及切晶層,從而使黏晶層及切晶層之外周部分露出。其次,將所露出之黏晶層黏附於分割後半導體晶圓,且將所露出之切晶層之外周部分黏附於切晶環。其次,剝離黏附於分割後半導體晶圓之表面之保護片。其後,沿分割後半導體晶圓之切斷部分對黏晶層進行切晶。切晶後,自切晶層剝離並取出附帶黏晶層之半導體晶片。所取出之附帶黏晶層之半導體晶片係自黏晶層側安裝於基板上。When a semiconductor wafer with a die-bonding layer is obtained by using the dicing-bonded ribbon described in Patent Document 1, the protruding portion of the dicing layer is used as a starting point of dicing, and the viscous layer and the dicing layer are peeled off from the release sheet to make the viscous layer The outer portions of the crystal layer and the crystal cutting layer are exposed. Next, the exposed die layer is adhered to the divided semiconductor wafer, and the outer peripheral portion of the exposed dicing layer is adhered to the dicing ring. Next, the protective sheet adhered to the surface of the divided semiconductor wafer is peeled off. Thereafter, the die layer is diced along the cut portion of the divided semiconductor wafer. After dicing, the semiconductor wafer with the viscous layer is peeled off from the dicing layer. The semiconductor wafer with the attached die layer is attached to the substrate from the side of the die layer.

於專利文獻1所記載之切晶-黏晶帶中,存在該切晶-黏晶帶以局部變形之狀態黏附於切晶環之情形。In the dicing-bonding ribbon described in Patent Document 1, there is a case where the dicing-bonding ribbon is adhered to the dicing ring in a state of local deformation.

於此情形時,存在將切晶層黏附於切晶環後,於切晶層,通常緩和黏附時之拉伸應力之收縮力會起作用,從而切晶層之收縮力局部性地不同之情形。因此,存在作為分割後半導體晶圓之切斷部分的切晶線彎曲之(稱為脊線位移之現象)情形。特別是對保護片進行加熱而加以剝離之情形時,藉由加熱,切晶層之黏附時之拉伸應力易於緩和,從而切晶線易於彎曲。因此,存在無法對黏晶層高精度地進行切晶,或晶片間未均等地拉寬,從而附帶黏晶層之半導體晶片之拾取性較低之情形。In this case, when the dicing layer is adhered to the dicing ring, the contraction force of the tensile stress is usually applied to the dicing layer, and the contraction force of the dicing layer is locally different. . Therefore, there is a case where the dicing line is bent as a cut portion of the divided semiconductor wafer (a phenomenon called ridge displacement). In particular, when the protective sheet is heated and peeled off, the tensile stress at the time of adhesion of the dicing layer is easily relaxed by heating, so that the dicing line is easily bent. Therefore, there is a case where the crystal layer cannot be crystallized with high precision or the wafers are not uniformly stretched, and the pick-up property of the semiconductor wafer with the adhesion layer is low.

本發明之目的在於提供一種獲得附帶黏著劑層之半導體晶片時,在黏附於切晶環時可抑制局部性變形,從而可提高切晶之精度,且藉由晶片間均等地拉寬,可提高附帶黏著劑層之半導體晶片之拾取性之切晶-黏晶帶、以及使用該切晶-黏晶帶之半導體晶片之製造方法。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor wafer having an adhesive layer capable of suppressing local deformation when adhered to a dicing ring, thereby improving the precision of dicing, and by uniformly widening between wafers, it is possible to improve A dicing-bonding ribbon for picking up a semiconductor wafer with an adhesive layer, and a method of manufacturing a semiconductor wafer using the dicing-bonding ribbon.

根據本發明之較廣態樣,提供一種切晶-黏晶帶,其包含黏著劑層、及積層於該黏著劑層之一面之基材層,於切晶時,在上述基材層之外周部分黏附有切晶環,上述基材層於外周部分具有於黏附時黏附於切晶環之黏附起點,將上述基材層之除上述黏附起點外之部分中之黏附於上述切晶環上的部分之寬度設為W(mm),將上述基材層之除上述黏附起點外之部分中之上述基材層之外徑設為D(mm)時,自上述基材層之靠上述黏附起點側之外周前端朝向內側相距0.3W(mm)之距離的位置處之上述黏附起點之長度L(mm)處於0.30D~0.44D(mm)之範圍內。According to a broader aspect of the present invention, there is provided a dicing-bonding layer comprising an adhesive layer and a substrate layer laminated on one side of the adhesive layer, and in the case of dicing, outside the substrate layer a part of the substrate is adhered to the dicing ring, and the substrate layer has an adhesion starting point adhered to the dicing ring at the peripheral portion, and adheres to the dicing ring in a portion of the substrate layer other than the adhesion starting point. The width of the portion is set to W (mm), and when the outer diameter of the base material layer in the portion other than the adhesion starting point of the base material layer is D (mm), the adhesion starting point from the base material layer The length L (mm) of the above-mentioned adhesion starting point at the position where the outer peripheral end of the side is at a distance of 0.3 W (mm) from the inner side is in the range of 0.30D to 0.44D (mm).

於本發明之切晶-黏晶帶之某一特定態樣中,上述基材層之上述黏附起點側之外周前端之曲率大於上述基材層之除上述黏附起點外之部分之外周端的曲率。In a specific aspect of the dicing-bonding ribbon of the present invention, the curvature of the outer peripheral end of the adhesion starting point side of the substrate layer is greater than the curvature of the peripheral end of the substrate layer other than the adhesion starting point.

於本發明之切晶-黏晶帶之其他特定態樣中,上述基材層於上述黏附起點側之外周端具有凸部,且上述基材層之上述黏附起點側之外周前端為上述凸部之頂點。In another specific aspect of the dicing-bonding ribbon of the present invention, the base material layer has a convex portion at an outer peripheral end of the adhesion starting point side, and the outer peripheral end of the adhesion starting point side of the base material layer is the convex portion. The apex.

於本發明之切晶-黏晶帶之進而其他特定態樣中,上述基材層於上述黏附起點側之外周端具有複數個凸部,且該複數個凸部由曲線連接。In still another specific aspect of the dicing-bonding ribbon of the present invention, the substrate layer has a plurality of convex portions at the outer peripheral end of the adhesion starting point side, and the plurality of convex portions are connected by a curve.

本發明之附帶黏著劑層之半導體晶片之製造方法包含如下步驟:使用根據本發明構成之切晶-黏晶帶、以及含有保護片及積層於該保護片之一面且分割成各個半導體晶片之分割後半導體晶圓之積層體,將上述切晶-黏晶帶之上述黏著劑層黏附於上述積層體之上述分割後半導體晶圓;將上述基材層之上述黏附起點黏附於圓環狀之切晶環,其次將除上述黏附起點外之上述基材層之外周部分黏附於上述切晶環;自上述分割後半導體晶圓剝離上述保護片;沿上述分割後半導體晶圓之切斷部分對上述黏著劑層進行切晶;及切晶後,自上述基材層剝離黏附有上述半導體晶片之上述黏著劑層,將半導體晶片連同上述黏著劑層一併取出。再者,亦可同時進行如下步驟:將上述切晶-黏晶帶之上述黏著劑層黏附於上述積層體之上述分割後半導體晶圓;及將上述基材層之上述黏附起點黏附於圓環狀之切晶環,其次將除上述黏附起點外之上述基材層之外周部分黏附於上述切晶環。The method for fabricating a semiconductor wafer with an adhesive layer according to the present invention comprises the steps of: using a diced-bonded ribbon formed according to the present invention, and a segment comprising a protective sheet and laminated on one side of the protective sheet and divided into individual semiconductor wafers a laminated body of the semiconductor wafer, wherein the adhesive layer of the dicing-bonding ribbon is adhered to the divided semiconductor wafer of the laminated body; and the adhesion starting point of the substrate layer is adhered to the annular shape a ring, and a peripheral portion of the substrate layer excluding the adhesion starting point is adhered to the dicing ring; the protective sheet is peeled off from the divided semiconductor wafer; and the cut portion of the semiconductor wafer is separated The adhesive layer is subjected to dicing; and after the dicing, the adhesive layer of the semiconductor wafer is peeled off from the base material layer, and the semiconductor wafer is taken out together with the adhesive layer. Furthermore, the step of adhering the adhesive layer of the dicing-bonding ribbon to the divided semiconductor wafer of the laminate; and adhering the adhesion starting point of the substrate layer to the ring may be simultaneously performed. The dicing ring of the shape is followed by adhering the outer peripheral portion of the base material layer other than the above-mentioned adhesion starting point to the above-mentioned cleavage ring.

於本發明之附帶黏著劑層之半導體晶片之製造方法的某一特定態樣中,進而包含如下步驟:於半導體晶圓之表面形成用以將該半導體晶圓分割成各個半導體晶片之切口;於形成有切口之上述半導體晶圓之表面黏附保護片;及研磨黏附有上述保護片之上述半導體晶圓之背面,將上述半導體晶圓分割成各個半導體晶片,從而獲得上述積層體。In a specific aspect of the method for fabricating a semiconductor wafer with an adhesive layer of the present invention, the method further includes the steps of: forming a slit for dividing the semiconductor wafer into individual semiconductor wafers on a surface of the semiconductor wafer; And forming a surface-adhesive protective sheet of the semiconductor wafer with the slit; and polishing the back surface of the semiconductor wafer to which the protective sheet is adhered, and dividing the semiconductor wafer into individual semiconductor wafers to obtain the laminated body.

本發明之附帶黏著劑層之半導體晶片之其他製造方法包含如下步驟:使用根據本發明構成之切晶-黏晶帶及半導體晶圓,將上述切晶-黏晶帶之上述黏著劑層黏附於上述半導體晶圓;將上述基材層之上述黏附起點黏附於圓環狀之切晶環,其次將除上述黏附起點外之上述基材層之外周部分黏附於上述切晶環;對上述半導體晶圓及上述黏著劑層進行切晶;及切晶後,自上述基材層剝離黏附有上述半導體晶片之上述黏著劑層,將半導體晶片連同上述黏著劑層一併取出。再者,亦可同時進行如下步驟:黏附於上述積層體之上述分割後半導體晶圓;及將上述基材層之上述黏附起點黏附於圓環狀之切晶環,其次將除上述黏附起點外之上述基材層之外周部分黏附於上述切晶環。Another method of manufacturing a semiconductor wafer with an adhesive layer of the present invention comprises the steps of adhering the above-mentioned adhesive layer of the above-mentioned diced-adhesive tape to a dicing-bonded ribbon and a semiconductor wafer constructed according to the present invention. The semiconductor wafer; the adhesion starting point of the substrate layer is adhered to an annular dicing ring, and then the outer peripheral portion of the substrate layer except the adhesion starting point is adhered to the dicing ring; The round and the adhesive layer are subjected to dicing; and after the dicing, the adhesive layer of the semiconductor wafer is peeled off from the base material layer, and the semiconductor wafer is taken out together with the adhesive layer. Furthermore, the following steps may be simultaneously performed: adhering the divided semiconductor wafer to the laminated body; and adhering the adhesion starting point of the substrate layer to the annular cleavage ring, and secondly, in addition to the adhesion starting point The outer peripheral portion of the above-mentioned base material layer is adhered to the above-mentioned dicing ring.

本發明之切晶-黏晶帶係將於除黏附起點外之部分之基材層之黏附於切晶環的部分之寬度設為W(mm),將於除黏附起點外之部分之基材層之外徑設為D(mm)時,於基材層之自黏附起點側之外周前端起向內側0.3W(mm)之距離的位置之黏附起點之長度L(mm)處於0.30D~0.44D(mm)之範圍內,故而藉由將基材層之黏附起點黏附於圓環狀之切晶環,其次將除黏附起點外之基材層之外周部分黏附於切晶環,可抑制局部性變形而將切晶-黏晶帶黏附於切晶環。因此,切晶後之切晶線難以彎曲。因此,可提高附帶黏著劑層之半導體晶片之拾取性。The cleavage-adhesive ribbon of the present invention has a width at which a portion of the substrate layer excluding the adhesion starting point adheres to the dicing ring is W (mm), and a portion which will be outside the adhesion starting point When the outer diameter of the layer is D (mm), the length L (mm) of the adhesion starting point at a position of the distance from the front end of the base layer to the inner side of 0.3 W (mm) from the end of the adhesion layer is 0.30D to 0.44. In the range of D (mm), the adhesion starting point of the substrate layer is adhered to the annular dicing ring, and the outer peripheral portion of the substrate layer except the adhesion starting point is adhered to the dicing ring, thereby suppressing the local portion. Sexual deformation adheres the diced-bonded ribbon to the cleavage ring. Therefore, the dicing line after dicing is difficult to bend. Therefore, the pick-up property of the semiconductor wafer with the adhesive layer can be improved.

進而,於使用保護片及分割後半導體晶圓之積層體獲得附帶黏著劑層之半導體晶片之情形時,即便將切晶-黏晶帶之黏著劑層黏附於積層體之分割後半導體晶圓,且自分割後半導體晶圓剝離保護片,作為分割後半導體晶圓之切斷部分的切晶線亦難以彎曲。因此,可高精度地對黏著劑層進行切晶,從而可提高拾取性。Further, when a semiconductor wafer with an adhesive layer is obtained by using a protective sheet and a laminated body of the divided semiconductor wafer, even if the adhesive layer of the dicing-adhesive tape is adhered to the divided semiconductor wafer of the laminated body, Further, since the semiconductor wafer is peeled off from the divided protective sheet, the dicing line which is the cut portion of the divided semiconductor wafer is also difficult to bend. Therefore, the adhesive layer can be crystallized with high precision, and the pick-up property can be improved.

以下,參照圖式,說明本發明之具體實施形態及實施例,藉此闡明本發明。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be elucidated by referring to the drawings and the embodiments of the invention.

(切晶-黏晶帶)(Cut-bonded ribbon)

圖1(a)及(b)係模式性地表示本發明之一實施形態之切晶-黏晶帶之圖。圖1(a)係局部欠缺平面圖,圖1(b)係沿圖1(a)中之I-I線之局部欠缺前視剖面圖。再者,於圖1及下述圖中,為便於圖示,尺寸及大小係自實際之尺寸及大小適當變更。1(a) and 1(b) are diagrams schematically showing a diced-bonded ribbon according to an embodiment of the present invention. Fig. 1(a) is a partially missing plan view, and Fig. 1(b) is a partially missing front cross-sectional view taken along line I-I of Fig. 1(a). In addition, in FIG. 1 and the following drawings, the size and size are appropriately changed from the actual size and size for convenience of illustration.

如圖1(a)及(b)所示,切晶-黏晶帶1包含長條狀之脫模層2。於脫模層2之上表面2a,依此順序積層有黏著劑層3、基材層4、切晶層5。於黏著劑層3之一面3a(第1面)積層有基材層4。於黏著劑層3之另一面3b(第2面)積層有脫模層2。As shown in FIGS. 1(a) and (b), the diced-bonded ribbon 1 comprises a strip-shaped release layer 2. On the upper surface 2a of the release layer 2, an adhesive layer 3, a base material layer 4, and a crystal cut layer 5 are laminated in this order. The base material layer 4 is laminated on one surface 3a (first surface) of the adhesive layer 3. A release layer 2 is laminated on the other surface 3b (second surface) of the adhesive layer 3.

於長條狀之脫模層2之上表面2a,等間隔地配置有包含黏著劑層3、基材層4及切晶層5之複數個積層物。於該積層物之側方,亦可在脫模層2之上表面2a設置有保護片。A plurality of laminates including the adhesive layer 3, the base material layer 4, and the crystal cut layer 5 are disposed at equal intervals on the upper surface 2a of the strip-shaped release layer 2. On the side of the laminate, a protective sheet may be provided on the upper surface 2a of the release layer 2.

脫模層2例如為脫模膜。脫模層2係用以保護黏著劑層3之黏附半導體晶圓之另一面3b。再者,脫模層2可不必使用。The release layer 2 is, for example, a release film. The release layer 2 serves to protect the other side 3b of the adhesive semiconductor layer 3 to which the semiconductor wafer is adhered. Further, the release layer 2 can be omitted.

作為構成脫模層2之材料,可列舉聚對苯二甲酸乙二醇酯樹脂等之聚酯系樹脂、聚四氟乙烯樹脂、聚乙烯樹脂、聚丙烯樹脂、聚甲基戊烯樹脂、聚醋酸乙烯酯樹脂等聚烯烴系樹脂、聚氯乙烯樹脂、及聚醯亞胺樹脂等塑膠樹脂等。Examples of the material constituting the release layer 2 include a polyester resin such as a polyethylene terephthalate resin, a polytetrafluoroethylene resin, a polyethylene resin, a polypropylene resin, a polymethylpentene resin, and a poly A polyolefin resin such as a vinyl acetate resin, a polyvinyl chloride resin, or a plastic resin such as a polyimide resin.

脫模層2之表面亦可進行脫模處理。脫模層可為單層,亦可為複數層。於脫模層為複數層之情形時,各層亦可由不同之樹脂所形成。The surface of the release layer 2 can also be subjected to mold release treatment. The release layer may be a single layer or a plurality of layers. In the case where the release layer is a plurality of layers, the layers may also be formed of different resins.

就更進一步提高脫模層2之處理性或剝離性之觀點而言,脫模層2之厚度較佳為處於10~100 μm之範圍內。The thickness of the release layer 2 is preferably in the range of 10 to 100 μm from the viewpoint of further improving the rationality or releasability of the release layer 2.

黏著劑層3係用於半導體晶片之黏晶之層。黏著劑層3係用以將半導體晶片接合於基板或其他半導體晶片等。Adhesive layer 3 is used for the layer of the die bond of the semiconductor wafer. The adhesive layer 3 is used to bond a semiconductor wafer to a substrate or other semiconductor wafer or the like.

黏著劑層3係由例如包含適當之硬化性樹脂等硬化性化合物之硬化性樹脂組合物、或熱塑性樹脂等形成。由於硬化前之上述硬化性樹脂組合物較軟,故而易於因外力而變形。於獲得附帶黏著劑層3之半導體晶片後,將所獲得之附帶黏著劑層3之半導體晶片自黏著劑層3側積層至基板等被黏著體。其後,賦予熱或光之能量,使黏著劑層3硬化,藉此可經由黏著劑層3使半導體晶片牢固地接合於被黏著體。The pressure-sensitive adhesive layer 3 is formed of, for example, a curable resin composition containing a curable compound such as a suitable curable resin, or a thermoplastic resin. Since the curable resin composition before curing is soft, it is easily deformed by an external force. After the semiconductor wafer with the adhesive layer 3 is obtained, the obtained semiconductor wafer with the adhesive layer 3 is laminated from the side of the adhesive layer 3 to the adherend such as a substrate. Thereafter, energy of heat or light is applied to harden the adhesive layer 3, whereby the semiconductor wafer can be firmly bonded to the adherend via the adhesive layer 3.

為使上述硬化性樹脂組合物硬化,係使用硬化劑。作為該硬化劑,例如可列舉三烷基四氫鄰苯二甲酸酐等加熱硬化型酸酐系硬化劑、苯酚系硬化劑、胺系硬化劑或雙氰胺等潛在性硬化劑、及陽離子系觸媒型硬化劑等。為調整硬化速度或硬化物之物性等,亦可併用上述硬化劑與硬化促進劑。In order to harden the said curable resin composition, a hardening agent is used. Examples of the curing agent include a heat curing type acid anhydride type curing agent such as trialkyltetrahydrophthalic anhydride, a latent curing agent such as a phenol curing agent, an amine curing agent or dicyandiamide, and a cationic contact lens. Medium hardener, etc. In order to adjust the hardening speed, the physical properties of the cured product, and the like, the above-mentioned hardener and hardening accelerator may be used in combination.

黏著劑層3之厚度並無特別限定。黏著劑層3之厚度較佳為處於1~100 μm之範圍內。黏著劑層3之厚度之更佳下限為3 μm,更佳上限為60 μm。若黏著劑層3之厚度處於上述範圍內,則易於黏附半導體晶片,從而可進一步因應半導體裝置之薄型化。The thickness of the adhesive layer 3 is not particularly limited. The thickness of the adhesive layer 3 is preferably in the range of 1 to 100 μm. A lower limit of the thickness of the adhesive layer 3 is 3 μm, and a higher limit is 60 μm. If the thickness of the adhesive layer 3 is within the above range, the semiconductor wafer can be easily adhered, and the thickness of the semiconductor device can be further increased.

基材層4包含具有非黏著性之非黏著部4A。非黏著部4A設置於基材層4之中央區域。非黏著部4A設置於與黏著劑層3之黏附半導體晶圓之位置相對應之部分。非黏著部4A之平面形狀為圓形。於平面觀察時,基材層4較黏著劑層3更大,非黏著部4A較黏著劑層3更大。因此,非黏著部4A具有較黏著劑層3之外周側面3c更向側方突出之區域。因此,於黏著劑層3黏附半導體晶圓時,可使半導體晶圓準確地位置對準於黏著劑層3之黏附有非黏著部4A之部分。黏附後,可於黏附有半導體晶圓之黏著劑層3之一面3a上確實地配置非黏著部4A。因此,切晶後,可容易地自基材層4之非黏著部4A剝離附帶黏著劑層3之半導體晶片。因此,可降低生產損失,從而可提高良率。The base material layer 4 includes a non-adhesive non-adhesive portion 4A. The non-adhesive portion 4A is provided in a central region of the base material layer 4. The non-adhesive portion 4A is provided at a portion corresponding to the position of the adhesive layer 3 to which the semiconductor wafer is adhered. The planar shape of the non-adhesive portion 4A is circular. The substrate layer 4 is larger than the adhesive layer 3 when viewed in plan, and the non-adhesive portion 4A is larger than the adhesive layer 3. Therefore, the non-adhesive portion 4A has a region that protrudes more laterally than the outer peripheral side surface 3c of the adhesive layer 3. Therefore, when the semiconductor wafer is adhered to the adhesive layer 3, the semiconductor wafer can be accurately aligned with the portion of the adhesive layer 3 to which the non-adhesive portion 4A is adhered. After the adhesion, the non-adhesive portion 4A can be reliably disposed on one surface 3a of the adhesive layer 3 to which the semiconductor wafer is adhered. Therefore, after the dicing, the semiconductor wafer with the adhesive layer 3 can be easily peeled off from the non-adhesive portion 4A of the base material layer 4. Therefore, the production loss can be reduced, thereby improving the yield.

再者,所謂「非黏著性」,不僅係指表面不具有黏著性,亦包含具有以手指碰觸表面時不會黏住之程度之黏著性之情形。具體而言,所謂「非黏著」,係指將基材層4之非黏著部4A黏附於不鏽鋼板,將基材層4以300 mm/分之剝離速度剝離時,黏著力為0.05 N/25 mm寬度以下。In addition, the term "non-adhesive" means not only that the surface does not have adhesiveness, but also the degree of adhesion which does not adhere when the finger touches the surface. Specifically, the term "non-adhesive" means that the non-adhesive portion 4A of the base material layer 4 is adhered to the stainless steel plate, and when the base material layer 4 is peeled off at a peeling speed of 300 mm/min, the adhesive force is 0.05 N/25. Below the mm width.

基材層4於非黏著部4A之外側部分之區域包含具有黏著性之黏著部4B。黏著部4B為環狀。基材層4覆蓋黏著劑層3,且基材層4之黏著部4B黏附於脫模層2之上表面2a。於黏著劑層3之一面3a之整面積層有基材層4之非黏著部4A。於黏著劑層3之一面3a未積層有黏著部4B。於切晶時,在基材層4之黏著部4B黏附切晶環。The base material layer 4 includes an adhesive portion 4B having adhesiveness in a region of the outer portion of the non-adhesive portion 4A. The adhesive portion 4B is annular. The base material layer 4 covers the adhesive layer 3, and the adhesive portion 4B of the base material layer 4 adheres to the upper surface 2a of the release layer 2. The non-adhesive portion 4A of the base material layer 4 is formed over the entire area of one surface 3a of the adhesive layer 3. The adhesive portion 4B is not laminated on one surface 3a of the adhesive layer 3. At the time of dicing, the dicing ring is adhered to the adhering portion 4B of the base material layer 4.

於圖2中,僅放大切晶-黏晶帶1之基材層4而以平面圖表示。In Fig. 2, only the base material layer 4 of the diced-bonded ribbon 1 is enlarged and shown in plan view.

如圖2所示,基材層4於外周部分具有在黏附開始時黏附於切晶環之黏附起點4C。黏附起點4C為黏附開始部分。於獲得附帶黏著劑層之半導體晶片時,自黏附起點4C起將基材層4之外周部分黏附於切晶環。基材層4之黏附於切晶環之部分為具有黏著性之黏著部4B。As shown in FIG. 2, the base material layer 4 has an adhesion starting point 4C adhered to the dicing ring at the beginning of adhesion at the outer peripheral portion. Adhesion starting point 4C is the beginning of adhesion. When the semiconductor wafer with the adhesive layer is obtained, the outer peripheral portion of the base material layer 4 is adhered to the dicing ring from the adhesion starting point 4C. The portion of the base material layer 4 adhered to the dicing ring is an adhesive portion 4B having adhesiveness.

基材層4之平面形狀大致為圓形,除黏附起點4C部分外之基材層4之平面形狀為圓形之一部分。於圖2中,以一點鏈線表示假設基材層4整體之平面形狀為圓形之情形時之虛擬線。The planar shape of the base material layer 4 is substantially circular, and the planar shape of the base material layer 4 except for the portion of the adhesion starting point 4C is a part of a circle. In FIG. 2, a virtual line when a planar shape of the entire base material layer 4 is assumed to be circular is indicated by a dotted line.

將除黏附起點4C外之基材層4之黏附於切晶環之部分的寬度設為W(mm),將於除黏附起點4C外之部分之基材層4之外徑(直徑)設為D(mm)。於本實施形態中,於基材層4之自黏附起點4C側之外周前端起向內側0.3W(mm)之距離的位置之黏附起點4C之長度L(mm)為0.30D~0.44D(mm)之範圍內。若長度L小於0.30D,則於黏附時發生局部變形之可能性升高。又,若長度L大於0.44D,則自切晶環露出之可能性變高,於已露出之情形時,有成為向下一步驟之搬送過程中黏附於其他切晶環、或於加工裝置內黏附於周邊部等的困擾之原因。進而,若黏附起點之長度過短,則於黏附開始時,應力易於集中在黏附起點。藉由延長黏附起點之長度,可使黏附開始時之應力沿黏附起點之長度方向分散。因此,可防止經預先切晶之分割後半導體晶圓中之複數個半導體晶片之位置偏移。The width of the portion of the base material layer 4 other than the adhesion starting point 4C adhered to the dicing ring is W (mm), and the outer diameter (diameter) of the substrate layer 4 which is outside the adhesion starting point 4C is set to D (mm). In the present embodiment, the length L (mm) of the adhesion starting point 4C at a position at a distance of 0.3 W (mm) from the front end of the base layer 4 from the outer edge of the adhesion start point 4C side is 0.30D to 0.44D (mm). Within the scope of). If the length L is less than 0.30 D, the possibility of local deformation at the time of adhesion increases. Moreover, if the length L is larger than 0.44D, the possibility of exposure from the dicing ring becomes high, and when it is exposed, it may adhere to other cleavage rings or to the processing apparatus during the transfer to the next step. The cause of the troubles of sticking to the peripheral parts. Further, if the length of the adhesion starting point is too short, the stress tends to concentrate on the adhesion starting point at the start of adhesion. By extending the length of the adhesion starting point, the stress at the beginning of the adhesion can be dispersed along the length of the adhesion starting point. Therefore, it is possible to prevent the positional shift of the plurality of semiconductor wafers in the semiconductor wafer after the pre-cutting.

黏附起點4C之前端係將自假設基材層4整體之平面形狀為圓形之情形時之虛擬線(圖2之一點鏈線)之黏附方向上之前端向黏附方向突出之長度設為突出長度Z(mm)。於下述實施形態中,亦將相同地突出之長度設為突出長度Z(mm)。突出長度Z(mm)宜小於0.20W,突出程度宜較小。若突出量變大,則存在黏附至切晶環時,黏附在切晶環之部分之寬度變得不均勻,或自切晶環露出之情形。所謂「黏附方向」,係指將設置有黏附開始時黏附於切晶環之黏附起點之基材層之一端、及與該一端為相反側之另一端連結之方向。The front end of the adhesion starting point 4C is set to a length from the front end in the direction of adhesion of the virtual line (one dot chain line of FIG. 2) in the direction in which the planar shape of the entire base layer 4 is assumed to be circular. Z (mm). In the following embodiment, the length that protrudes in the same manner is also set as the protruding length Z (mm). The protruding length Z (mm) should be less than 0.20 W, and the degree of protrusion should be small. When the amount of protrusion becomes large, when the adhesion to the dicing ring occurs, the width of the portion adhered to the dicing ring becomes uneven, or the self-cut ring is exposed. The term "adhesion direction" means a direction in which one end of a base material layer adhered to an adhesion start point of a dicing ring at the beginning of adhesion and a other end opposite to the one end side are provided.

寬度W係將基材層4黏附至切晶環時,於除黏附起點4C外之部分之自切晶環之內周端至基材層4之外周端為止之距離。The width W is a distance from the inner peripheral end of the portion other than the adhesion starting point 4C to the outer peripheral end of the base layer 4 when the base layer 4 is adhered to the dicing ring.

除黏附起點4C部分外之基材層4之平面形狀為圓形之一部分,外徑D係表示於圓形部分之基材層4之外徑(直徑)。The planar shape of the base material layer 4 except for the adhesion starting point 4C portion is a circular portion, and the outer diameter D is the outer diameter (diameter) of the base material layer 4 of the circular portion.

黏附起點4C具有寬度方向及較該寬度方向更長之長度方向。長度L係表示於基材層4之自黏附起點4C側之外周前端起向內側,即於黏附方向上向內側0.3W之距離的位置之黏附起點4C之長度方向尺寸。長度L係表示於基材層4之自黏附起點4C側之外周前端起向與基材層4之黏附起點4C側為相反側0.3W之距離的位置之黏附起點4C之長度方向尺寸。The adhesion starting point 4C has a width direction and a length direction longer than the width direction. The length L is expressed in the longitudinal direction of the adhesion starting point 4C of the base layer 4 from the outer peripheral end of the adhesion starting point 4C side toward the inner side, that is, the distance of 0.3 W inward in the adhesion direction. The length L is a dimension in the longitudinal direction of the adhesion starting point 4C at a position from the outer peripheral end of the base layer 4 from the outer peripheral end of the adhesion starting point 4C to the side opposite to the adhesion starting point 4C side of the base material layer 4 by 0.3 W.

基材層4於黏附起點4C側之外周端含有3個凸部4a~4c。凸部4b位於凸部4a與凸部4c之間。圖2中,將凸部4a之頂點表示為B1,將凸部4b之頂點表示為A1,將凸部4c之頂點表示為B2。A1係基材層4之黏附起點4C側之外周前端。The base material layer 4 has three convex portions 4a to 4c at the outer peripheral end of the adhesion start point 4C side. The convex portion 4b is located between the convex portion 4a and the convex portion 4c. In Fig. 2, the apex of the convex portion 4a is represented as B1, the apex of the convex portion 4b is represented as A1, and the apex of the convex portion 4c is represented as B2. The adhesion starting point 4C side of the A1 base material layer 4 is the outer peripheral end.

於基材層4中,B1與A1由直線連接,且A1與B2由直線連接。由連結B1、A1及B2之3條直線所圍成之部分之平面形狀為連結B1與A1之直線、及連結A1與B2之直線之長度相等之等腰三角形。圖2中,將連結B1與B2之直線、與自A1下垂至該直線之垂線之交叉點表示為A11。In the base material layer 4, B1 and A1 are connected by a straight line, and A1 and B2 are connected by a straight line. The planar shape of the portion surrounded by the three straight lines connecting B1, A1, and B2 is an isosceles triangle connecting the straight lines of B1 and A1 and the lengths of the straight lines connecting A1 and B2. In Fig. 2, the intersection of the straight line connecting B1 and B2 with the perpendicular line from A1 to the straight line is denoted as A11.

B1與基材層4之圓形部分、及B2與基材層4之圓形部分係由直線連接。圖2中,將B1與基材層4之圓形部分之接點表示為C1,將B2與基材層4之圓形部分之接點表示為C2。連結B1與C1之直線係基材層4之圓形部分之於C1之切線。連結B2與C2之直線係基材層4之圓形部分之於C2之切線。The circular portion of B1 and the substrate layer 4, and the circular portion of B2 and the substrate layer 4 are connected by a straight line. In Fig. 2, the junction of B1 and the circular portion of the substrate layer 4 is denoted as C1, and the junction of B2 with the circular portion of the substrate layer 4 is denoted as C2. The circular portion of the linear substrate layer 4 connecting B1 and C1 is tangent to C1. The circular portion of the linear substrate layer 4 connecting B2 and C2 is tangent to C2.

基材層4之非黏著部4A與黏著部4B係形成為一體。非黏著部4A與黏著部4B係由相同之材料形成,而並非由不同之材料形成。The non-adhesive portion 4A of the base material layer 4 and the adhesive portion 4B are integrally formed. The non-adhesive portion 4A and the adhesive portion 4B are formed of the same material, and are not formed of different materials.

基材層4例如可使用具有活性能量線硬化型或熱硬化型之黏著性之組合物形成。於活性能量線硬化型之組合物之情形時,藉由對相對於組合物之活性能量線之照射量進行部分調整,可使基材層4之黏著性局部性地不同。為使基材層4具有非黏著性,只要增多活性能量線之照射量即可。為使基材層4具有黏著性,只要不照射活性能量線、或減少活性能量線之照射量即可。The base material layer 4 can be formed, for example, by using a composition having an active energy ray-curing type or a thermosetting type. In the case of an active energy ray-curable composition, the adhesion of the substrate layer 4 can be locally different by partially adjusting the amount of irradiation with respect to the active energy ray of the composition. In order to make the base material layer 4 non-adhesive, it is sufficient to increase the amount of irradiation of the active energy ray. In order to make the base material layer 4 adhesive, it is sufficient that the active energy ray is not irradiated or the amount of irradiation of the active energy ray is reduced.

基材層4較佳為由包含丙烯酸系聚合物之組合物形成。基材層4較佳為由使包含丙烯酸系聚合物之組合物交聯而成之交聯體形成。於此情形時,可更進一步提高切晶時之切削性。又,可容易地控制及設計基材層4之極性、儲存模數(storage modulus)或斷裂伸長率(rupture elongation)。The base material layer 4 is preferably formed of a composition containing an acrylic polymer. The base material layer 4 is preferably formed of a crosslinked body obtained by crosslinking a composition containing an acrylic polymer. In this case, the machinability at the time of crystal cutting can be further improved. Moreover, the polarity, storage modulus or rupture elongation of the substrate layer 4 can be easily controlled and designed.

上述丙烯酸系聚合物並無特別限定。上述丙烯酸系聚合物較佳為(甲基)丙烯酸烷基酯聚合物。作為(甲基)丙烯酸烷基酯聚合物,宜使用具有碳數為1~18之烷基之(甲基)丙烯酸烷基酯聚合物。藉由使用具有碳數為1~18之烷基之(甲基)丙烯酸烷基酯聚合物,可充分地降低基材層4之極性,可降低基材層4之表面能量,且可提高黏著劑層3之自基材層4之剝離性。The acrylic polymer is not particularly limited. The above acrylic polymer is preferably an alkyl (meth)acrylate polymer. As the (meth)acrylic acid alkyl ester polymer, an alkyl (meth)acrylate polymer having an alkyl group having 1 to 18 carbon atoms is preferably used. By using an alkyl (meth) acrylate polymer having an alkyl group having 1 to 18 carbon atoms, the polarity of the substrate layer 4 can be sufficiently lowered, the surface energy of the substrate layer 4 can be lowered, and adhesion can be improved. The peelability of the agent layer 3 from the substrate layer 4.

上述組合物較佳為包含活性能量線反應起始劑及熱反應起始劑中之至少一者,更佳為包含活性能量線反應起始劑。活性能量線反應起始劑較佳為光反應起始劑。The above composition preferably contains at least one of an active energy ray reaction initiator and a thermal reaction initiator, and more preferably an active energy ray reaction initiator. The active energy ray reaction initiator is preferably a photoreaction initiator.

上述活性能量線中包含紫外線、電子束、α線、β線、γ線、X線、紅外線及可見光線。於該等活性能量線中,紫外線或電子束因硬化性優異且硬化物難以劣化,故而較佳。The active energy ray includes ultraviolet rays, electron beams, α rays, β rays, γ rays, X rays, infrared rays, and visible rays. Among these active energy rays, ultraviolet rays or electron beams are preferable because they are excellent in hardenability and hardly deteriorated.

作為上述光反應起始劑,例如可使用光自由基產生劑或光陽離子產生劑等。作為上述熱反應起始劑,可列舉熱自由基產生劑等。於上述組合物中,為控制黏著力,亦可添加異氰酸酯系交聯劑。As the photoreaction initiator, for example, a photoradical generator, a photocation generator, or the like can be used. Examples of the thermal reaction initiator include a thermal radical generator and the like. In the above composition, an isocyanate crosslinking agent may be added to control the adhesion.

基材層4之厚度並無特別限定。基材層4之厚度較佳為處於1~100 μm之範圍內。基材層4之厚度之更佳下限為5 μm,更佳上限為60 μm。若基材層4之厚度滿足上述較佳下限,可更進一步提高伸展性。若基材層4之厚度滿足上述較佳上限,則厚度變得更加均勻,從而可更進一步提高切晶之精度。The thickness of the base material layer 4 is not particularly limited. The thickness of the substrate layer 4 is preferably in the range of 1 to 100 μm. A lower limit of the thickness of the substrate layer 4 is 5 μm, and a more preferred upper limit is 60 μm. If the thickness of the base material layer 4 satisfies the above preferred lower limit, the stretchability can be further improved. When the thickness of the base material layer 4 satisfies the above preferred upper limit, the thickness becomes more uniform, and the precision of the crystal cutting can be further improved.

切晶層5例如為切晶膜。作為構成切晶層5之材料,可列舉聚對苯二甲酸乙二醇酯樹脂等聚酯系樹脂、聚四氟乙烯樹脂、聚乙烯樹脂、聚丙烯樹脂、聚甲基戊烯樹脂、聚醋酸乙烯酯樹脂等聚烯烴系樹脂、聚氯乙烯樹脂、及聚醯亞胺樹脂等塑膠樹脂等。其中,因伸展性優異,環境負荷較小,故宜使用聚烯烴系樹脂。The dicing layer 5 is, for example, a dicing film. Examples of the material constituting the crystal cut layer 5 include a polyester resin such as a polyethylene terephthalate resin, a polytetrafluoroethylene resin, a polyethylene resin, a polypropylene resin, a polymethylpentene resin, and a polyacetic acid. A polyolefin resin such as a vinyl ester resin, a polyvinyl chloride resin, or a plastic resin such as a polyimide resin. Among them, polyolefin resin is preferred because it has excellent stretchability and a small environmental load.

切晶層5之厚度並無特別限定。切晶層5之厚度較佳為處於10~200 μm之範圍內。切晶層5之厚度之更佳下限為60 μm,更佳上限為150 μm。若切晶層5之厚度處於上述範圍內,則可更進一步提高脫模層2之剝離性及切晶層5之伸展性。The thickness of the crystal cutting layer 5 is not particularly limited. The thickness of the dicing layer 5 is preferably in the range of 10 to 200 μm. A lower limit of the thickness of the dicing layer 5 is preferably 60 μm, and a more preferred upper limit is 150 μm. When the thickness of the dicing layer 5 is within the above range, the releasability of the release layer 2 and the stretchability of the dicing layer 5 can be further improved.

於本實施形態中,切晶層5之平面形狀與基材層4之平面形狀相同。切晶層5之平面形狀亦可與基材層4之平面形狀不同。切晶層5之大小於不妨礙本發明之效果之範圍內,可大於基材層4之大小,亦可小於基材層4之大小。切晶層5之大小較佳為大於基材層4之大小。In the present embodiment, the planar shape of the crystal cutting layer 5 is the same as the planar shape of the base material layer 4. The planar shape of the dicing layer 5 may also be different from the planar shape of the substrate layer 4. The size of the dicing layer 5 may be larger than the size of the substrate layer 4 or smaller than the size of the substrate layer 4 within a range that does not impair the effects of the present invention. The size of the dicing layer 5 is preferably larger than the size of the substrate layer 4.

於切晶-黏晶帶1中,係使用切晶層5。亦可省略切晶層5,由基材層4兼用作切晶層。於切晶-黏晶帶1中,可於基材層4之黏著部4B黏附切晶環,故而無需於切晶層5黏附切晶環。因此,可省略切晶層5。於切晶層5無需黏附切晶環,故而切晶層5亦可不具有黏著力。因此,可自更廣範圍選擇構成切晶層5之材料及組成。In the dicing-mulet zone 1, a dicing layer 5 is used. The dicing layer 5 may also be omitted, and the substrate layer 4 also serves as a dicing layer. In the dicing-adhesive tape 1, the dicing ring can be adhered to the adhesive portion 4B of the base material layer 4, so that it is not necessary to adhere the dicing ring to the dicing layer 5. Therefore, the crystal cutting layer 5 can be omitted. Since the dicing layer 5 does not need to adhere to the dicing ring, the dicing layer 5 may not have an adhesive force. Therefore, the material and composition constituting the crystal cutting layer 5 can be selected from a wider range.

於切晶時,可更進一步有效地防止半導體晶片之飛出等,故而較佳為於基材層4之與黏附有黏著劑層3之一面為相反側之另一面黏附有切晶層5。於此情形時,對基材層4並未大幅要求伸展性等,故而可自更廣範圍選擇構成基材層4之材料及組成。In the case of dicing, the semiconductor wafer can be prevented from flying out more effectively. Therefore, it is preferable that the dicing layer 5 is adhered to the other surface of the base material layer 4 opposite to the surface on which the adhesive layer 3 is adhered. In this case, since the stretchability and the like are not greatly required for the base material layer 4, the material and composition constituting the base material layer 4 can be selected from a wider range.

於圖3及圖4中,表示基材層之變形例。3 and 4 show a modification of the base material layer.

圖3、4所示之基材層11、12除黏附起點之形狀不同外,與基材層4同樣地構成。基材層11、12包含非黏著部11A、12A、及設於非黏著部11A、12A之外周部分之區域的黏著部11B、12B。基材層11、12之黏附於切晶環之部分係具有黏著性之黏著部11B、12B。The base material layers 11 and 12 shown in FIGS. 3 and 4 are configured in the same manner as the base material layer 4 except that the shape of the adhesion starting point is different. The base material layers 11 and 12 include the non-adhesive portions 11A and 12A and the adhesive portions 11B and 12B provided in the regions of the outer peripheral portions of the non-adhesive portions 11A and 12A. The portions of the base material layers 11 and 12 adhered to the dicing ring are adhesive portions 11B and 12B.

基材層11、12之平面形狀大致為圓形,且除黏附起點11C、12C部分外之基材層11、12之平面形狀為圓形之一部分。於圖3、4中,以一點鏈線表示假設基材層11、12整體之平面形狀為圓形之情形時之虛擬線。將於基材層11、12之除黏附起點11C、12C外之部分之基材層11、12的黏附於切晶環之部分之寬度設為W(mm),將於除黏附起點11C、12C外之部分之基材層11、12之外徑設為D(mm)。於基材層11、12之自黏附起點11C、12C側之外周前端起向內側0.3W(mm)之距離的位置之黏附起點11C、12C之長度L(mm)處於0.30D~0.44D(mm)之範圍內。若長度L小於0.30D,則黏附時發生局部變形之可能性升高。又,若長度L大於0.44D,則自切晶環露出之可能性變高,且於已露出之情形時,存在導致向下一步驟之搬送過程中黏附於其他切晶環、或於加工裝置內黏附於周邊部等的問題之情形。The planar shape of the substrate layers 11, 12 is substantially circular, and the planar shape of the substrate layers 11, 12 except for the portions of the adhesion starting points 11C, 12C is a part of a circle. In Figs. 3 and 4, the virtual line when the planar shape of the entire base material layers 11, 12 is assumed to be circular is indicated by a dotted line. The width of the portion of the base material layers 11 and 12 excluding the adhesion starting points 11C and 12C which adheres to the dicing ring is set to W (mm), and will be removed from the adhesion starting point 11C, 12C. The outer diameter of the outer base material layers 11, 12 is set to D (mm). The length L (mm) of the adhesion starting points 11C, 12C at the position of the distance from the front end of the outer peripheral edge 11C, 12C of the base material layers 11 and 12 to the inner side at a distance of 0.3 W (mm) is 0.30D to 0.44D (mm). Within the scope of). If the length L is less than 0.30 D, the possibility of local deformation at the time of adhesion increases. Moreover, if the length L is greater than 0.44D, the possibility of exposure from the dicing ring becomes high, and when it is exposed, there is a possibility of adhering to other cleavage rings during the transfer to the next step, or to the processing device. A problem in which the inside adheres to a problem such as a peripheral portion.

圖3所示之基材層11於黏附起點11C側之外周端包含4個凸部11a~11d。凸部11b及凸部11c位於凸部11a與凸部11d之間,且凸部11b位於凸部11a側,凸部11c位於凸部11d側。圖3中,將凸部11a之頂點表示為B1,將凸部11b之頂點表示為A1,將凸部11c之頂點表示為A2,將凸部11d之頂點表示為B2。A1及A2係基材層11之黏附起點11C側之外周前端。The base material layer 11 shown in Fig. 3 includes four convex portions 11a to 11d at the outer peripheral end of the adhesion starting point 11C side. The convex portion 11b and the convex portion 11c are located between the convex portion 11a and the convex portion 11d, and the convex portion 11b is located on the convex portion 11a side, and the convex portion 11c is located on the convex portion 11d side. In Fig. 3, the vertex of the convex portion 11a is represented as B1, the vertex of the convex portion 11b is represented as A1, the vertex of the convex portion 11c is represented as A2, and the vertex of the convex portion 11d is represented as B2. The A1 and A2 base material layers 11 adhere to the outer peripheral end of the starting point 11C side.

於基材層11中,B1與A1由直線連接,A1與A2由曲線連接,且A2與B2由直線連接。藉由連結B1、A1、A2及B2之4條直線所圍成之部分之平面形狀為將連結A1與A2之直線作為上底,將連結B1與B2之直線作為下底之等腰梯形。圖3中,將凸部11b與凸部11c之間之凹部之最深部表示為A11。又,圖3中,將連結B1與B2之直線、與自A1下垂至該直線之垂線之交叉點表示為A21,將連結B1與B2之直線、與自A2下垂至該直線之垂線之交叉點表示為A22。In the base material layer 11, B1 and A1 are connected by a straight line, A1 and A2 are connected by a curve, and A2 and B2 are connected by a straight line. The planar shape of the portion surrounded by the four straight lines connecting B1, A1, A2, and B2 is such that the straight line connecting A1 and A2 is the upper base, and the straight line connecting B1 and B2 is the isosceles trapezoid of the lower bottom. In Fig. 3, the deepest portion of the concave portion between the convex portion 11b and the convex portion 11c is denoted as A11. Further, in Fig. 3, the intersection of the straight line connecting B1 and B2 with the perpendicular line from A1 to the straight line is denoted as A21, and the line connecting B1 and B2 and the intersection of the straight line from A2 to the straight line of the straight line Expressed as A22.

B1與基材層11之圓形部分、及B2與基材層11之圓形部分由直線連接。圖3中,將B1與基材層11之圓形部分之接點表示為C1,將B2與基材層11之圓形部分之接點表示為C2。連結B1與C1之直線及連結B2與C2之直線分別為基材層11之圓形部分之於C1、C2之切線。The circular portion of B1 and the substrate layer 11, and the circular portion of B2 and the substrate layer 11 are connected by a straight line. In Fig. 3, the junction of B1 and the circular portion of the substrate layer 11 is denoted as C1, and the junction of B2 with the circular portion of the substrate layer 11 is denoted as C2. The straight line connecting B1 and C1 and the straight line connecting B2 and C2 are tangent lines of C1 and C2 of the circular portion of the base material layer 11, respectively.

圖4所示之基材層12於黏附起點12C側之外周端包含4個凸部12a~12d。凸部12b及凸部12c位於凸部12a與凸部12d之間,且凸部12b位於凸部12a側,凸部12c位於凸部12d側。圖4中,將凸部12a之頂點表示為A1,將凸部12b之頂點表示為A2,將凸部21c之頂點表示為A3,將凸部21d之頂點表示為A4。A1、A2、A3及A4均為基材層12之黏附起點12C側之外周前端。The base material layer 12 shown in Fig. 4 includes four convex portions 12a to 12d at the outer peripheral end of the adhesion starting point 12C side. The convex portion 12b and the convex portion 12c are located between the convex portion 12a and the convex portion 12d, and the convex portion 12b is located on the convex portion 12a side, and the convex portion 12c is located on the convex portion 12d side. In FIG. 4, the vertex of the convex portion 12a is represented as A1, the vertex of the convex portion 12b is represented as A2, the vertex of the convex portion 21c is represented as A3, and the vertex of the convex portion 21d is represented as A4. A1, A2, A3, and A4 are the outer peripheral ends of the adhesion starting point 12C side of the base material layer 12.

於基材層12中,A1與A2、A2與A3、A3與A4分別由曲線連接。圖4中,將凸部12a與凸部12b之間的凹部之最深部表示為A11,將凸部12b與凸部12c之間的凹部之最深部表示為A12,將凸部12c與凸部12d之間的凹部之最深部表示為A13。In the base material layer 12, A1 and A2, A2 and A3, and A3 and A4 are respectively connected by a curve. In Fig. 4, the deepest portion of the concave portion between the convex portion 12a and the convex portion 12b is denoted as A11, the deepest portion of the concave portion between the convex portion 12b and the convex portion 12c is denoted as A12, and the convex portion 12c and the convex portion 12d The deepest portion between the recesses is denoted as A13.

A1與基材層12之圓形部分、及A4與基材層12之圓形部分係相連接。圖4中,將A1與基材層12之圓形部分之接點表示為C1,將A4與基材層12之圓形部分之接點表示為C2。A1與C1由曲線及直線連接,且A1側為曲線,C1側為直線。圖4中,將自A1延伸之曲線與自C1延伸之直線之邊界表示為B1。A4與C2由曲線及直線連接,且A4側為曲線,C2側為直線。圖4中,將自A4延伸之曲線與自C2延伸之直線之邊界表示為B2。自C1延伸之直線及自C2延伸之直線分別為基材層12之圓形部分之於C1、C2之切線。A1 is connected to the circular portion of the substrate layer 12 and the circular portion of the substrate layer 12 of A4. In Fig. 4, the junction of A1 and the circular portion of the substrate layer 12 is denoted as C1, and the junction of A4 and the circular portion of the substrate layer 12 is denoted as C2. A1 and C1 are connected by a curve and a straight line, and the A1 side is a curve, and the C1 side is a straight line. In Fig. 4, the boundary between the curve extending from A1 and the straight line extending from C1 is represented as B1. A4 and C2 are connected by curves and straight lines, and the A4 side is a curve, and the C2 side is a straight line. In Fig. 4, the boundary between the curve extending from A4 and the straight line extending from C2 is represented as B2. The straight line extending from C1 and the straight line extending from C2 are the tangent to the circular portion of the substrate layer 12 at C1 and C2, respectively.

圖4中,將連結B1與B2之直線、與自A1下垂至該直線之垂線之交叉點表示為A21,將連結B1與B2之直線、與自A2下垂至該直線之垂線之交叉點表示為A22,將連結B1與B2之直線、與自A3下垂至該直線之垂線之交叉點表示為A23,將連結B1與B2之直線、與自A4下垂至該直線之垂線之交叉點表示為A24。In Fig. 4, the intersection of the straight line connecting B1 and B2 with the perpendicular line from A1 to the straight line is denoted as A21, and the intersection of the straight line connecting B1 and B2 with the perpendicular line from A2 to the straight line is expressed as In A22, the intersection of the straight line connecting B1 and B2 with the perpendicular line from A3 to the straight line is denoted as A23, and the intersection of the straight line connecting B1 and B2 with the perpendicular line from A4 to the straight line is denoted as A24.

凸部12a~12d之前端為曲線。基材層12之黏附起點12C側之外周前端之於A1~A4的曲率大於基材層12之除黏附起點12C外之部分之外周端的曲率。The front ends of the convex portions 12a to 12d are curved. The curvature of A1 to A4 at the outer peripheral end of the adhesion starting point 12C side of the base material layer 12 is larger than the curvature of the outer peripheral end of the portion of the base material layer 12 excluding the adhesion starting point 12C.

如圖3及圖4所示,只要於基材層之自黏附起點側之外周前端起向內側0.3W(mm)之距離的位置之黏附起點之長度L(mm)處於0.30D~0.44D(mm)之範圍內,基材層之黏附起點之平面形狀即可進行適當變更。As shown in FIG. 3 and FIG. 4, the length L (mm) of the adhesion starting point at a position of a distance of 0.3 W (mm) from the front end of the base layer to the inner side of the adhesion layer is 0.30D to 0.44D ( Within the range of mm), the planar shape of the adhesion starting point of the substrate layer can be appropriately changed.

如基材層12,基材層之黏附起點側之外周前端之曲率較佳為大於基材層之除黏附起點外之部分之外周端的曲率。於此情形時,自脫模層2進行剝離時,基材層之黏附起點側之外周前端成為剝離起點,從而可容易地進行剝離,於獲得附帶黏著劑層之半導體晶片時,可更進一步高精度地對黏著劑層進行切晶。For example, in the base material layer 12, the curvature of the outer peripheral end of the adhesion starting point side of the base material layer is preferably larger than the curvature of the outer peripheral end of the base material layer except for the portion other than the adhesion starting point. In this case, when the release layer 2 is peeled off, the outer peripheral end of the base layer on the adhesion start side is a peeling origin, and the peeling can be easily performed, and the semiconductor wafer with the adhesive layer can be further increased. The adhesive layer is crystallized with precision.

基材層4之黏附起點4C側之外周前端係凸部4b之頂點A1。基材層11之黏附起點11C側之外周前端係凸部11b、11c之頂點A1、A2。基材層12之黏附起點12C側之外周前端係凸部12a~12d之頂點A1~A4。如上所述,基材層較佳為於黏附起點側之外周端含有凸部,且基材層之黏附起點側之外周前端為該凸部之頂點。於此情形時,自脫模層2剝離時,基材層之黏附起點側之凸部成為剝離起點,從而可容易地進行剝離,當獲得附帶黏著劑層之半導體晶片時,可更進一步高精度地對黏著劑層進行切晶。The apex A1 of the outer peripheral end portion of the base material layer 4 on the adhesion start point 4C side. The base end layer 11 is adhered to the apex A1 and A2 of the outer peripheral end portion convex portions 11b and 11c on the outer side of the adhesion starting point 11C side. The apex A1 to A4 of the outer peripheral end projections 12a to 12d of the outer peripheral end of the base layer 12 on the adhesion start point 12C side. As described above, the base material layer preferably has a convex portion at the outer peripheral end on the adhesion start side, and the outer peripheral end of the base layer on the adhesion start side is the apex of the convex portion. In this case, when the release layer 2 is peeled off, the convex portion on the adhesion start side of the base material layer serves as a peeling starting point, so that peeling can be easily performed, and when the semiconductor wafer with the adhesive layer is obtained, the precision can be further improved. The layer of the adhesive is diced.

基材層11於黏附起點11C側之外周端含有複數個凸部11a~11d,且凸部11b與凸部1tc由曲線連接。基材層12於黏附起點12C側之外周端含有複數個凸部12a~12d,且該複數個凸部12a~12d由曲線連接。如上所述,基材層較佳為於黏附起點側之外周端含有複數個凸部,且該複數個凸部由曲線連接。於此情形時,自脫模層2剝離時成為剝離起點,從而可容易地進行剝離,當獲得附帶黏著劑層之半導體晶片時,可更進一步高精度地對黏著劑層進行切晶。The base material layer 11 includes a plurality of convex portions 11a to 11d at the outer peripheral end of the adhesion starting point 11C side, and the convex portion 11b and the convex portion 1tc are connected by a curved line. The base material layer 12 includes a plurality of convex portions 12a to 12d at the outer peripheral end of the adhesion start point 12C side, and the plurality of convex portions 12a to 12d are connected by a curved line. As described above, the base material layer preferably has a plurality of convex portions at the outer peripheral end of the adhesion starting point side, and the plurality of convex portions are connected by a curve. In this case, when the release layer 2 is peeled off, it becomes a peeling origin, and peeling can be easily performed. When the semiconductor wafer with an adhesive layer is obtained, the adhesive layer can be further diced with higher precision.

又,於基材層4、11、12中,黏附起點4C、11C、12C與除黏附起點4C、11C、12C外之部分所成之內角為180度以下。即,於黏附起點4C、11C、12C之基端部分,黏附起點4C、11C、12C與除黏附起點4C、11C、12C外之部分係以內角為180度以下之方式連接。如上所述,若上述內角為180度以下,則可防止於黏附起點之基端,基材層被切斷。若上述內角超過180度,則存在於黏附起點之基端,基材層容易被切斷之傾向。Further, in the base material layers 4, 11, and 12, the internal angles of the adhesion starting points 4C, 11C, and 12C and the portions other than the adhesion starting points 4C, 11C, and 12C are 180 degrees or less. That is, at the base end portions of the adhesion starting points 4C, 11C, and 12C, the adhesion starting points 4C, 11C, and 12C are connected to the portions other than the adhesion starting points 4C, 11C, and 12C so that the internal angle is 180 degrees or less. As described above, when the internal angle is 180 degrees or less, the base end of the adhesion starting point can be prevented from being cut off. When the internal angle exceeds 180 degrees, the base layer is likely to be cut at the base end of the adhesion starting point.

於圖1所示之切晶-黏晶帶1中,在1個基材層4上,僅設有1處黏附起點4C。黏附起點4C係設置於長條狀脫模層2之長度方向之一端側。於圖15中表示切晶-黏晶帶之變形例。圖1所示之切晶-黏晶帶1與圖15所示之切晶-黏晶帶51係基材層上之黏附起點之個數及形成位置不同,伴隨於此切晶層亦不同。設置於切晶-黏晶帶1之黏附起點4C、與設置於切晶-黏晶帶51之基材層52之黏附起點52C之形狀相同。設置於切晶-黏晶帶51之基材層52與切晶層53之形狀相同。再者,於圖15中,基材層52係由切晶層53所覆蓋。In the dicing-bonding ribbon 1 shown in Fig. 1, only one adhesion starting point 4C is provided on one base material layer 4. The adhesion starting point 4C is provided on one end side of the longitudinal direction of the elongated release layer 2. A modification of the dicing-mulet zone is shown in FIG. The number of etched-bonded ribbons 1 shown in FIG. 1 and the number of adhesion starting points on the base layer of the diced-bonded ribbon 51 shown in FIG. 15 are different from each other, and the dicing layer is also different. The adhesion starting point 4C of the dicing-bonding ribbon 1 is the same as the adhesion starting point 52C of the substrate layer 52 provided on the dicing-bonding ribbon 51. The base material layer 52 disposed on the dicing-bonding ribbon 51 has the same shape as the dicing layer 53. Further, in FIG. 15, the base material layer 52 is covered by the crystal cutting layer 53.

於圖15所示之切晶-黏晶帶51中,於1個基材層52上,設置有2處黏附起點52C。黏附起點52C係設置於長條狀脫模層2之長度方向之一端側、及與該一端側相反之另一端側。如上所述,較佳為於1個基材層上設置有複數個黏附起點,且較佳為設置有至少2個黏附起點。於在1個基材層上設置有複數個黏附起點之情形時,較佳為於基材層之一端側及與該一端側相反之另一端側設置有黏附起點。於此情形時,可消除切晶-黏晶帶使用時之方向性。又,例如於未能較佳地自一端側之黏附起點黏附基材層之情形等時,可自另一端側之黏附起點黏附基材層。更具體而言,於未能較佳地自一端側之黏附起點黏附基材層之情形等時,藉由將長條狀之切晶-黏晶帶暫時捲取後再次捲開,可自另一端側之黏附起點黏附基材層。In the dicing-bonding ribbon 51 shown in Fig. 15, two adhesion starting points 52C are provided on one base material layer 52. The adhesion starting point 52C is provided on one end side in the longitudinal direction of the elongated release layer 2 and on the other end side opposite to the one end side. As described above, it is preferable to provide a plurality of adhesion starting points on one substrate layer, and it is preferable to provide at least two adhesion starting points. In the case where a plurality of adhesion starting points are provided on one base material layer, it is preferable to provide an adhesion starting point on one end side of the base material layer and the other end side opposite to the one end side. In this case, the directionality of the diced-bonded ribbon can be eliminated. Further, for example, when the base material layer is not adhered preferably from the adhesion starting point on the one end side, the base material layer can be adhered from the adhesion starting point on the other end side. More specifically, in the case where the base material layer is not preferably adhered from the adhesion start point on the one end side, the long strip-shaped cleavage-adhesive ribbon is temporarily wound up and then wound up again, and The adhesion starting point on one end side adheres to the substrate layer.

(附帶黏著劑層之半導體晶片之製造方法)(Method of manufacturing a semiconductor wafer with an adhesive layer)

其次,以下說明使用圖1(a)、(b)及圖2所示之切晶- 黏晶帶1之情形時的附帶黏著劑層之半導體晶片之製造方法的一例。Next, described below with reference to FIG 1 (a), (b) and FIG cutting the crystal shown in FIG. 2 - example of a method of manufacturing a semiconductor wafer the adhesive layer of the die-incidental with the case when the 1.

首先,包含切晶-黏晶帶1、及積層體21。First, the dicing-bonded ribbon 1, and the laminated body 21 are included.

如圖5(d)所示,積層體21包含保護片22、及積層於保護片22之一面22a之分割後半導體晶圓23。分割後半導體晶圓23被分割成各個半導體晶片。分割後半導體晶圓23之平面形狀為圓形。As shown in FIG. 5(d), the laminated body 21 includes a protective sheet 22 and a divided semiconductor wafer 23 laminated on one surface 22a of the protective sheet 22. The divided semiconductor wafer 23 is divided into individual semiconductor wafers. The planar shape of the semiconductor wafer 23 after the division is circular.

積層體21可經由圖5(a)~(d)所示之各步驟,以如下方式獲得。The laminate 21 can be obtained in the following manner via the respective steps shown in Figs. 5(a) to (d).

首先,如圖5(a)所示,準備半導體晶圓23A。半導體晶圓23A係分割前半導體晶圓。半導體晶圓23A之平面形狀為圓形。於半導體晶圓23A之表面23a,在藉由界道(street)呈矩陣狀劃分而成之各區域內,形成有用以構成各個半導體晶片之電路。First, as shown in FIG. 5(a), a semiconductor wafer 23A is prepared. The semiconductor wafer 23A is a semiconductor wafer before division. The planar shape of the semiconductor wafer 23A is circular. On the surface 23a of the semiconductor wafer 23A, circuits for forming the respective semiconductor wafers are formed in respective regions which are divided into a matrix by a street.

如圖5(b)所示,對所準備之半導體晶圓23A自表面23a側進行切晶。切晶後,半導體晶圓23A未被切斷。於半導體晶圓23A之表面23a形成有用以分割成各個半導體晶片之切口23c。切晶係例如使用包含高速旋轉之刀片之切晶裝置等來進行。As shown in FIG. 5(b), the prepared semiconductor wafer 23A is diced from the surface 23a side. After the dicing, the semiconductor wafer 23A is not cut. A slit 23c for dividing into individual semiconductor wafers is formed on the surface 23a of the semiconductor wafer 23A. The dicing system is performed, for example, using a dicing apparatus including a blade that rotates at a high speed.

其次,如圖5(c)所示,於半導體晶圓23A之表面23a黏附保護片22。其後,對半導體晶圓23A之背面23b進行研磨,使半導體晶圓23A之厚度變薄。此處,半導體晶圓23A之背面23b係研磨至切口23c部分為止。以如此方式,可獲得圖5(d)所示之積層體21。Next, as shown in FIG. 5(c), the protective sheet 22 is adhered to the surface 23a of the semiconductor wafer 23A. Thereafter, the back surface 23b of the semiconductor wafer 23A is polished to reduce the thickness of the semiconductor wafer 23A. Here, the back surface 23b of the semiconductor wafer 23A is polished to the portion of the slit 23c. In this manner, the laminated body 21 shown in Fig. 5(d) can be obtained.

半導體晶圓23A之背面23b較佳為研磨至切口23c部分為止。研磨係使用包含例如研磨磁鐵等之磨床(grinder)等的研磨機來進行。於研磨時,在半導體晶圓23A之表面23a黏附有保護片22,故而於電路上不會附著研磨屑。又,即便於研磨後半導體晶圓23A分割成各個半導體晶片,複數個半導體晶片亦不會零亂而仍舊黏附於保護片22。The back surface 23b of the semiconductor wafer 23A is preferably polished to the portion of the slit 23c. The polishing is performed using a grinder including a grinder such as a grinding magnet. At the time of polishing, the protective sheet 22 is adhered to the surface 23a of the semiconductor wafer 23A, so that no abrasive grains adhere to the circuit. Further, even after the semiconductor wafer 23A is divided into individual semiconductor wafers after the polishing, the plurality of semiconductor wafers are not cluttered and adhere to the protective sheet 22.

獲得積層體21後,如圖6(a)所示,使積層體21自保護片22側搭載至平台25上。於平台25上,在自分割後半導體晶圓23之外周側面相隔固定間隔之位置,設置有圓環狀之切晶環26。一面剝離切晶-黏晶帶1之脫模層2,或於剝離脫模層2後,將所露出之黏著劑層3之另一面3b黏附於分割後半導體晶圓23之背面23b。又,將所露出之基材層4之外周部分自黏附起點4C黏附於切晶環26。After the laminated body 21 is obtained, as shown in FIG. 6(a), the laminated body 21 is mounted on the stage 25 from the side of the protective sheet 22. On the stage 25, an annular ring-shaped ring 26 is provided at a position spaced apart from each other by the outer circumferential side of the semiconductor wafer 23 after the division. The release layer 2 of the dicing-adhesive tape 1 is peeled off, or after the release layer 2 is peeled off, the other surface 3b of the exposed adhesive layer 3 is adhered to the back surface 23b of the divided semiconductor wafer 23. Further, the outer peripheral portion of the exposed base material layer 4 is adhered to the dicing ring 26 from the adhesion starting point 4C.

於圖8(a)中,以前視剖面圖表示將基材層4黏附於切晶環26時之狀態,並且於圖8(b)中,以平面圖表示將基材層4黏附於切晶環26後之狀態。In Fig. 8(a), a front cross-sectional view shows a state in which the base material layer 4 is adhered to the dicing ring 26, and in Fig. 8(b), the base material layer 4 is adhered to the dicing ring in plan view. The state after 26.

如圖8(a)及(b)所示,通常係於將基材層4黏附於切晶環26時,使用剝離邊緣32將基材層4及切晶層5自脫模層2之上表面2a剝離。將基材層4之黏附起點4C黏附於切晶環26,利用捲輥31按壓黏附起點4C上。繼而,一面拉伸黏著劑層3、基材層4及切晶層5以避免於黏著劑層3、基材層4及切晶層5上產生褶皺,一面將基材層4之外周部分黏附於切晶環26。於黏附於切晶環26之基材層4及切晶層5,收縮力在起作用。As shown in FIGS. 8( a ) and ( b ), generally, when the base material layer 4 is adhered to the dicing ring 26 , the base material layer 4 and the dicing layer 5 are self-released from the release layer 2 using the peeling edge 32 . The surface 2a is peeled off. The adhesion starting point 4C of the base material layer 4 is adhered to the dicing ring 26, and is pressed against the adhesion starting point 4C by the winding roller 31. Then, the adhesive layer 3, the base material layer 4, and the dicing layer 5 are stretched one by one to avoid wrinkles on the adhesive layer 3, the base material layer 4, and the dicing layer 5, and the outer peripheral portion of the base material layer 4 is adhered. In the cleavage ring 26. The shrinkage force acts on the base layer 4 and the dicing layer 5 adhered to the dicing ring 26.

若上述收縮力局部性地不同,則例如將基材層黏附於切晶環後,或者自分割後半導體晶圓剝離保護片後,分割後半導體晶圓之切斷部分即切晶線易於彎曲。When the shrinkage force is locally different, for example, after the base material layer is adhered to the dicing ring, or the protective wafer is peeled off from the semiconductor wafer after the division, the cut crystal line which is the cut portion of the semiconductor wafer after the division is easily bent.

於切晶-黏晶帶1中,長度L(mm)處於0.30D~0.44D(mm)之範圍內。即,於將切晶-黏晶帶1之基材層4黏附於切晶環時,將基材層4之自黏附起點4C側之外周前端起向內側0.3W之距離的位置黏附於切晶環26,其次將除黏附起點4C外之基材層4之外周部分黏附於切晶環26。換言之,於黏附開始時,黏附於切晶環26之基材層4部分之長度L(mm)處於0.30D~0.44D(mm)之範圍內。因此,黏附於切晶環26之基材層4、及積層於該基材層4之黏著劑層3及切晶層5之收縮力難以局部性地大幅不同。In the diced-bonded ribbon 1, the length L (mm) is in the range of 0.30D to 0.44D (mm). That is, when the base layer 4 of the dicing-bonding ribbon 1 is adhered to the dicing ring, the base layer 4 is adhered to the dicing at a position 0.3W from the outer peripheral end of the adhesion starting point 4C side. The ring 26, nextly, adheres the outer peripheral portion of the base material layer 4 other than the adhesion starting point 4C to the dicing ring 26. In other words, at the beginning of adhesion, the length L (mm) of the portion of the substrate layer 4 adhered to the dicing ring 26 is in the range of 0.30D to 0.44D (mm). Therefore, the shrinkage force of the base material layer 4 adhered to the dicing ring 26 and the adhesive layer 3 and the dicing layer 5 laminated on the base material layer 4 is hardly locally different.

因此,將基材層4黏附於切晶環26後,或於自黏附於黏著劑層3之分割後半導體晶圓23剝離保護片22後,分割後半導體晶圓23之切晶線難以彎曲。因此,可高精度地對黏著劑層3進行切晶。進而,可提高附帶黏著劑層3之半導體晶片之拾取性。Therefore, after the base material layer 4 is adhered to the dicing ring 26 or the protective sheet 22 is peeled off from the divided semiconductor wafer 23 adhered to the adhesive layer 3, the dicing line of the semiconductor wafer 23 after the division is difficult to bend. Therefore, the adhesive layer 3 can be crystallized with high precision. Further, the pick-up property of the semiconductor wafer with the adhesive layer 3 can be improved.

將基材層4黏附於切晶環26後,如圖6(b)所示,將黏附有黏著劑層3之分割後半導體晶圓23自平台25取出並翻轉過來。此時,以將切晶環26黏附於基材層4之黏著部4B之狀態取出。將所取出之分割後半導體晶圓23翻轉以使表面23a成為上方,而搭載於另一平台27上。After the base material layer 4 is adhered to the dicing ring 26, as shown in FIG. 6(b), the divided semiconductor wafer 23 to which the adhesive layer 3 is adhered is taken out from the stage 25 and turned over. At this time, the dicing ring 26 is adhered to the adhesive portion 4B of the base material layer 4 in a state of being taken out. The taken-out semiconductor wafer 23 is inverted so that the surface 23a is placed upward and mounted on the other stage 27.

其次,如圖7(a)所示,自分割後半導體晶圓23之表面23a剝離保護片22。於剝離保護片22時,為易於剝離,亦可對保護片22進行加熱。Next, as shown in FIG. 7(a), the protective sheet 22 is peeled off from the surface 23a of the semiconductor wafer 23 after the division. When the protective sheet 22 is peeled off, the protective sheet 22 may be heated in order to facilitate peeling.

其次,如圖7(b)所示,沿分割後半導體晶圓23之切口23c(切斷部分),即沿切晶線對黏著劑層3進行切晶。以貫通兩面之方式對黏著劑層3進行切晶,分割成各個半導體晶片之大小。於切晶後,在黏著劑層3形成切斷部分3d。於使用切晶-黏晶帶1之情形時,在黏附有分割後半導體晶圓23之黏著劑層3部分之下方,設置有具有非黏著性之非黏著部4A,故而可高精度地進行切晶。因此,切晶後,可提高附帶黏著劑層之半導體晶片之拾取性。Next, as shown in FIG. 7(b), the adhesive layer 3 is diced along the slit 23c (cut portion) of the divided semiconductor wafer 23, that is, along the dicing line. The adhesive layer 3 is diced in such a manner as to penetrate the both sides, and is divided into the sizes of the respective semiconductor wafers. After the dicing, the cut portion 3d is formed in the adhesive layer 3. When the dicing-adhesive tape 1 is used, a non-adhesive non-adhesive portion 4A is provided under the portion of the adhesive layer 3 to which the divided semiconductor wafer 23 is adhered, so that the cutting can be performed with high precision. crystal. Therefore, after dicing, the pick-up property of the semiconductor wafer with the adhesive layer can be improved.

切晶係只要係以貫通黏著劑層3之方式進行則並無特別限定。作為對黏著劑層3進行切晶之方法,可列舉使用切晶刀片之方法、及雷射切晶之方法等。於使用分割後半導體晶圓23之情形時,通常係使用雷射切晶之方法。The dicing system is not particularly limited as long as it is carried through the adhesive layer 3 . As a method of dicing the adhesive layer 3, the method of using a crystal cutting blade, the method of laser-cutting, etc. are mentioned. In the case of using the divided semiconductor wafer 23, a laser dicing method is generally used.

於基材層4之非黏著部4A例如已被硬化之情形時,非黏著部4A難以藉由雷射光之照射而發生反應。因此,基材層4難以融著於黏著劑層3。因此,即使於已進行使用雷射光之切晶之情形時,亦可輕鬆地進行半導體晶片之拾取。When the non-adhesive portion 4A of the base material layer 4 is hardened, for example, the non-adhesive portion 4A is difficult to react by irradiation of laser light. Therefore, it is difficult for the base material layer 4 to be fused to the adhesive layer 3. Therefore, even when the dicing using the laser light has been performed, the pickup of the semiconductor wafer can be easily performed.

對半導體晶圓進行切晶而分割成各個半導體晶片後,拉伸切晶層5,擴大經分割而成之各個半導體晶片間之間隔。其後,將半導體晶片連同黏著劑層3一併自基材層4剝離而取出。以如此方式,可獲得附帶黏著劑層3之半導體晶片。After the semiconductor wafer is diced and divided into individual semiconductor wafers, the dicing layer 5 is stretched to expand the interval between the divided semiconductor wafers. Thereafter, the semiconductor wafer and the adhesive layer 3 are peeled off from the base material layer 4 and taken out. In this manner, a semiconductor wafer with an adhesive layer 3 can be obtained.

又,較佳為於切晶後,不改變黏著劑層3與非黏著部4A之間之剝離力而取出半導體晶片。基材層4之黏附於黏著劑層3之非黏著部4A具有非黏著性。因此,切晶後,即便不改變上述剝離力,亦可輕鬆地取出附帶黏著劑層3之半導體晶片。Further, it is preferable to take out the semiconductor wafer after the dicing, without changing the peeling force between the adhesive layer 3 and the non-adhesive portion 4A. The non-adhesive portion 4A of the base material layer 4 adhered to the adhesive layer 3 has non-adhesive properties. Therefore, after the dicing, the semiconductor wafer with the adhesive layer 3 can be easily taken out without changing the peeling force.

其次,以下說明使用圖9(a)、(b)所示之切晶-黏晶帶1之附帶黏著劑層之半導體晶片的製造方法的另一例。Next, another example of a method of manufacturing a semiconductor wafer using the adhesive layer of the dicing-bonding ribbon 1 shown in Figs. 9(a) and (b) will be described below.

首先,準備上述切晶-黏晶帶1及半導體晶圓41。半導體晶圓41之平面形狀為圓形。半導體晶圓41未分割成各個半導體晶片。First, the above-described diced-bonded ribbon 1 and semiconductor wafer 41 are prepared. The planar shape of the semiconductor wafer 41 is circular. The semiconductor wafer 41 is not divided into individual semiconductor wafers.

如圖9(a)所示,將半導體晶圓41翻轉,使經翻轉之半導體晶圓41自表面41a側搭載於平台25上。於平台25上,在自半導體晶圓41之外周側面相隔固定間隔之位置,設置有圓環狀之切晶環26。一面剝離切晶-黏晶帶1之脫模層2,或於剝離脫模層2後,將所露出之黏著劑層3之另一面3b黏附於半導體晶圓41之背面41b。又,將所露出之基材層4之外周部分自黏附起點4C黏附於切晶環26。As shown in FIG. 9(a), the semiconductor wafer 41 is turned over, and the inverted semiconductor wafer 41 is mounted on the stage 25 from the surface 41a side. On the stage 25, an annular cleavage ring 26 is provided at a position spaced apart from the outer circumferential side of the semiconductor wafer 41 at a fixed interval. The release layer 2 of the dicing-bonding ribbon 1 is peeled off, or after the release layer 2 is peeled off, the other surface 3b of the exposed adhesive layer 3 is adhered to the back surface 41b of the semiconductor wafer 41. Further, the outer peripheral portion of the exposed base material layer 4 is adhered to the dicing ring 26 from the adhesion starting point 4C.

其次,如圖9(b)所示,將黏附有黏著劑層3之半導體晶圓41自平台25取出並翻轉過來。此時,以將切晶環26黏附於基材層4之黏著部4B之狀態取出。將所取出之半導體晶圓41翻轉以使表面41a成為上方,而搭載至另一平台27上。其次,對半導體晶圓41連同黏著劑層3一併進行切晶,分割成各個半導體晶片。將半導體晶圓41及黏著劑層3分別以貫通兩面之方式切斷。於切晶後,在半導體晶圓41形成切斷部分41c,在黏著劑層3形成切斷部分3d,且於基材層4形成切口。Next, as shown in FIG. 9(b), the semiconductor wafer 41 to which the adhesive layer 3 is adhered is taken out from the stage 25 and turned over. At this time, the dicing ring 26 is adhered to the adhesive portion 4B of the base material layer 4 in a state of being taken out. The taken-out semiconductor wafer 41 is turned over so that the surface 41a becomes upward and is mounted on the other stage 27. Next, the semiconductor wafer 41 is diced together with the adhesive layer 3, and is divided into individual semiconductor wafers. The semiconductor wafer 41 and the adhesive layer 3 are cut so as to penetrate both sides. After the dicing, the cut portion 41c is formed in the semiconductor wafer 41, the cut portion 3d is formed in the adhesive layer 3, and a slit is formed in the base material layer 4.

其次,拉伸切晶層5,將半導體晶片連同黏著劑層3一併自基材層4剝離而取出,藉此可獲得附帶黏著劑層3之半導體晶片。Next, the crystal cutting layer 5 is stretched, and the semiconductor wafer and the adhesive layer 3 are peeled off from the base material layer 4 and taken out, whereby the semiconductor wafer with the adhesive layer 3 can be obtained.

以下,藉由列舉實施例及比較例,對本發明進行具體說明。本發明並不限定於以下之實施例。Hereinafter, the present invention will be specifically described by way of examples and comparative examples. The invention is not limited to the following examples.

(丙烯酸系聚合物1)(acrylic polymer 1)

使95重量份之丙烯酸-2-乙基己酯、5重量份之丙烯酸-2-羥乙酯、0.2重量份之作為光自由基產生劑之Irgacure651之(汽巴-嘉基(Ciba-Geigy)公司製造、50%乙酸乙酯溶液)、及0.01重量份之十二硫醇溶解於乙酸乙酯中,獲得溶液。對該溶液照射紫外線而進行聚合,獲得聚合物之乙酸乙酯溶液。進而,相對於100重量份之該溶液之固形物成分,使3.5重量份的2-甲基丙烯醯氧乙基異氰酸酯(昭和電工公司製造,Karenz MOI)進行反應,獲得丙烯酸共聚物(丙烯酸系聚合物1)。所獲得之丙烯酸系聚合物1之重量平均分子量為70萬,且酸值為0.86(mgKOH/g)。95 parts by weight of 2-ethylhexyl acrylate, 5 parts by weight of 2-hydroxyethyl acrylate, and 0.2 parts by weight of Irgacure 651 as a photoradical generator (Ciba-Geigy) The company manufactured, 50% ethyl acetate solution, and 0.01 part by weight of dodecanol were dissolved in ethyl acetate to obtain a solution. The solution was irradiated with ultraviolet rays to carry out polymerization to obtain an ethyl acetate solution of the polymer. Further, 3.5 parts by weight of 2-methylpropenyloxyethyl isocyanate (manufactured by Showa Denko, Karenz MOI) was reacted with respect to 100 parts by weight of the solid content of the solution to obtain an acrylic copolymer (acrylic polymerization). Matter 1). The obtained acrylic polymer 1 had a weight average molecular weight of 700,000 and an acid value of 0.86 (mgKOH/g).

又,作為構成用以形成基材層之組合物之材料,準備以下之化合物。Further, as a material constituting the composition for forming the substrate layer, the following compounds were prepared.

(光聚合起始劑)(photopolymerization initiator)

Irgacure651(日本汽巴(Ciba Japan)公司製造)Irgacure651 (manufactured by Ciba Japan)

(寡聚物)(oligomer)

U324A:新中村化學工業公司製造,丙烯酸聚氨酯寡聚物(具有10個官能基之丙烯酸聚氨酯寡聚物),重量平均分子量:1,300U324A: Manufactured by Xinzhongcun Chemical Industry Co., Ltd., acrylic urethane oligomer (10 functional acrylic urethane oligomer), weight average molecular weight: 1,300

(交聯劑)(crosslinking agent)

CoronateL-45:日本聚氨酯工業公司製造,異氰酸酯系交聯劑Coronate L-45: manufactured by Japan Polyurethane Industry Co., Ltd., isocyanate crosslinking agent

(切晶層)(cut layer)

使用聚乙烯(普瑞曼聚合物(Prime Polymer)公司製造,M12)作為原料,藉由T模法製造作為厚度為100 μm之切晶層之聚乙烯膜。A polyethylene film as a crystal cut layer having a thickness of 100 μm was produced by a T-die method using polyethylene (manufactured by Prime Polymer Co., Ltd., M12) as a raw material.

(實施例1)(Example 1)

於實施例1中,形成圖1(a)、(b)及圖2所示之形狀之切晶-黏晶帶及基材層。In the first embodiment, a diced-bonded ribbon and a substrate layer having the shapes shown in Figs. 1(a), (b) and 2 are formed.

(1) 第1積層體之製作(1) Production of the first laminate

調配1 100重量份之上述丙烯酸系聚合物、1重量份之Irgacure651、15重量份之作為丙烯酸聚氨酯寡聚物之U324A、及1重量份之CoronateL-45,獲得黏著劑組合物。將所獲得之黏著劑組合物塗佈於脫模PET(polyethylene terephthalate,聚對苯二甲酸伸乙酯)膜,於110℃進行5分鐘乾燥,去除溶劑,從而形成組合物層。To 100 parts by weight of the above acrylic polymer, 1 part by weight of Irgacure 651, 15 parts by weight of U324A as an urethane urethane oligomer, and 1 part by weight of Coronate L-45, an adhesive composition was obtained. The obtained adhesive composition was applied to a release PET (polyethylene terephthalate) film, dried at 110 ° C for 5 minutes, and the solvent was removed to form a composition layer.

對積層作為切晶層之聚乙烯膜之基材層之面進行鏡面加工及電暈處理。於與黏附有組合物層之脫模PET膜之面為相反側之面黏附聚乙烯膜。其後,於40℃保管24小時。The surface of the base material layer of the polyethylene film which is a layered layer is mirror-finished and corona-treated. A polyethylene film was adhered to the opposite side of the surface of the release PET film to which the composition layer was adhered. Thereafter, it was stored at 40 ° C for 24 hours.

其次,對所獲得之組合物層之中央區域,使用水銀燈,以成為2000 mJ/cm2 之能量之方式照射光,使組合物層硬化。以如此方式,獲得基材層(厚度20 μm),該基材層係於中央區域含有非黏著部,於該非黏著部之外側部分之區域含有黏著部者。Next, light was irradiated to the central region of the obtained composition layer by using a mercury lamp so as to have an energy of 2000 mJ/cm 2 to harden the composition layer. In this manner, a base material layer (thickness: 20 μm) having a non-adhesive portion in the central portion and an adhesive portion in the region of the outer portion of the non-adhesive portion was obtained.

以上述方式,獲得依此順序積層有脫模PET膜、基材層及切晶層之第1積層體。In the above manner, the first layered body in which the release PET film, the base material layer, and the crystal cut layer were laminated in this order was obtained.

(2) 第2積層體之製作(2) Production of the second laminate

調配15重量份之G-2050M(日油公司製造,含環氧基之丙烯酸聚合物,重量平均分子量Mw為20萬)、70重量份之EXA-7200HH(DIC(迪愛生)公司製造,二環戊二烯型環氧化物)、15重量份之HP-4032D(DIC公司製造,萘型環氧化物)、38重量份之YH-309(三菱化學公司製造,酸酐系硬化劑)、8重量份之2MAOK-PW(四國化成公司製造,咪唑)、2重量份之S320(智索(Chisso)公司製造,胺基矽烷)、及4重量份之MT-10(德山(Tokuyama)公司製造,表面疏水化燻矽),獲得調配物。將所獲得之調配物以固形物成分成為60重量%之方式添加至作為溶劑之甲基乙基酮(MEK(methyl ethyl ketone))中,並加以攪拌,而獲得塗液。15 parts by weight of G-2050M (manufactured by NOF Corporation, an epoxy group-containing acrylic polymer, weight average molecular weight Mw of 200,000), 70 parts by weight of EXA-7200HH (DIC (Di Ai Sheng) Co., Ltd., 2nd ring Pentadiene type epoxide), 15 parts by weight of HP-4032D (manufactured by DIC Corporation, naphthalene type epoxide), 38 parts by weight of YH-309 (manufactured by Mitsubishi Chemical Corporation, an acid anhydride type hardener), 8 parts by weight 2MAOK-PW (manufactured by Shikoku Chemical Co., Ltd., imidazole), 2 parts by weight of S320 (manufactured by Chisso Co., Ltd., amino decane), and 4 parts by weight of MT-10 (manufactured by Tokuyama Co., Ltd.) The surface is hydrophobized and smoked) to obtain a formulation. The obtained preparation was added to methyl ethyl ketone (MEK (methyl ethyl ketone)) as a solvent so as to have a solid content of 60% by weight, and stirred to obtain a coating liquid.

將所獲得之塗液塗佈於脫模PET膜上以使厚度成為10 μm,並於110℃之燒爐內進行2分鐘加熱乾燥。The obtained coating liquid was applied onto a release PET film to have a thickness of 10 μm, and dried by heating in a furnace at 110 ° C for 2 minutes.

其後,以黏著劑層之平面形狀成為下述表1所示之直徑之圓形的方式進行加工,獲得於脫模PET膜上積層有黏著劑層之第2積層體。Thereafter, the planar shape of the adhesive layer was processed to have a circular shape as shown in the following Table 1, and a second laminated body in which an adhesive layer was laminated on the release PET film was obtained.

(3) 切晶-黏晶帶之製作(3) Fabrication of dicing-bonded ribbon

其次,剝離第1積層體之脫模PET膜,使基材層露出。將基材層及切晶層之積層體自基材層側以60℃層壓至黏著劑層上,從而獲得層壓體。其後,以成為圖1(a)、(b)及圖2所示之形狀,即下述表1所示之尺寸之方式,切下基材層及切晶層。以如此方式,製作具有依次順序積層有脫模PET膜/黏著劑層/基材層/切晶層之4層積層構造之切晶-黏晶帶。Next, the release PET film of the first laminate was peeled off to expose the substrate layer. The laminate of the base material layer and the dicing layer was laminated from the side of the base material layer to the adhesive layer at 60 ° C to obtain a laminate. Thereafter, the base material layer and the crystal cut layer were cut out so as to have the shapes shown in Figs. 1 (a), (b) and Fig. 2, that is, the sizes shown in Table 1 below. In this manner, a diced-bonded ribbon having a four-layered laminated structure in which a release PET film/adhesive layer/substrate layer/cut layer was sequentially laminated was prepared.

於所獲得之切晶-黏晶帶中,具有非黏著部較黏著劑層更大且非黏著部較黏著劑層之外周側面更向側方突出之區域。In the obtained diced-bonded ribbon, there is a region where the non-adhesive portion is larger than the adhesive layer and the non-adhesive portion protrudes more laterally than the outer peripheral side of the adhesive layer.

(實施例2~4)(Examples 2 to 4)

於實施例2~4中,形成有圖1(a)、(b)及圖2所示之形狀之切晶-黏晶帶及基材層。除如下述表1所示般變更基材層及切晶層之尺寸以外,與實施例1同樣地製作切晶-黏晶帶。再者,於圖2中,黏附起點4C之前端並未自假設基材層4整體之平面形狀為圓形之情形時之虛擬線(一點鏈線)之黏附方向上之前端向黏附方向突出,但於實施例4中,黏附起點4C之前端則自虛擬線之黏附方向上之前端向黏附方向突出。In Examples 2 to 4, a diced-bonded ribbon and a substrate layer having the shapes shown in Figs. 1(a), (b) and 2 were formed. A diced-bonded ribbon was produced in the same manner as in Example 1 except that the dimensions of the base layer and the diced layer were changed as shown in Table 1 below. Further, in FIG. 2, the front end of the adhesion starting point 4C does not protrude from the front end in the direction of adhesion of the imaginary line (a little chain line) when the planar shape of the entire base layer 4 is assumed to be circular. However, in the embodiment 4, the front end of the adhesion starting point 4C protrudes from the front end in the adhesion direction of the virtual line toward the adhesion direction.

(實施例5~6)(Examples 5 to 6)

於實施例2~6中,除將基材層及切晶層之形狀及尺寸變更為圖3所示之形狀,即下述表2所示之尺寸以外,與實施例1同樣地製作切晶-黏晶帶。再者,於圖3中,黏附起點11C之前端並未自假設基材層11整體之平面形狀為圓形之情形時之虛擬線(一點鏈線)之黏附方向上之前端向黏附方向突出,但於實施例6中,黏附起點11C之前端則自虛擬線之黏附方向上之前端向黏附方向突出。In the second to sixth embodiments, the shape of the base material layer and the crystal cutting layer was changed to the shape shown in FIG. 3, that is, the size shown in Table 2 below, and the crystal was produced in the same manner as in Example 1. - A sticky layer. Further, in FIG. 3, the front end of the adhesion starting point 11C does not protrude from the front end in the direction of adhesion of the virtual line (a little chain line) when the planar shape of the entire base layer 11 is assumed to be circular, However, in the embodiment 6, the front end of the adhesion starting point 11C protrudes from the front end in the adhesion direction of the virtual line toward the adhesion direction.

(實施例7)(Example 7)

於實施例7中,除將基材層及切晶層之形狀及尺寸變更為圖4所示之形狀,即下述表3所示之尺寸以外,與實施例1同樣地製作切晶-黏晶帶。In the seventh embodiment, except that the shape and size of the base layer and the dicing layer were changed to the shapes shown in FIG. 4, that is, the sizes shown in Table 3 below, the dicing-adhesion was produced in the same manner as in Example 1. Crystal ribbon.

(比較例1~5)(Comparative examples 1 to 5)

於比較例1~5中,除將基材層及切晶層之形狀及尺寸變更為下述表4所示之圖10~14中之任一形狀,即下述表4所示之尺寸以外,與實施例1同樣地製作切晶-黏晶帶。In Comparative Examples 1 to 5, the shape and size of the base layer and the dicing layer were changed to any of the shapes shown in Tables 4 to 14 shown in Table 4 below, that is, the dimensions shown in Table 4 below. A diced-bonded ribbon was produced in the same manner as in Example 1.

於比較例1、2、4、5中,基材層之平面形狀大致為圓形,且除黏附起點部分外之基材層之平面形狀為圓形之一部分。於圖10~11、13~14中,以一點鏈線表示假設基材層101~102、104~105整體之平面形狀為圓形之情形時之虛擬線。於比較例3中,基材層103之平面形狀為圓形。In Comparative Examples 1, 2, 4, and 5, the planar shape of the base material layer was substantially circular, and the planar shape of the base material layer excluding the adhesion starting portion was a part of a circle. In FIGS. 10 to 11 and 13 to 14, the virtual line when the planar shape of the entire base material layers 101 to 102 and 104 to 105 is assumed to be circular is indicated by a one-dot chain line. In Comparative Example 3, the planar shape of the base material layer 103 was circular.

(評價)(Evaluation)

於直徑為300 mm(12inch)之半導體晶圓(矽晶圓,厚度為80 μm)之表面切入深度為100 μm之切口。其次,自丙烯酸系黏著劑側將作為保護片之背面研磨帶Icross SB135S-BN(三井化學公司製造,於烯烴之單面塗佈有丙烯酸系黏著劑)層壓於半導體晶圓之表面。其次,研磨半導體晶圓之背面直至半導體晶圓之厚度成為35 μm後,使用CMP(Chemical Mechanical Polishing,化學機械拋光法)研磨漿,進行半導體晶圓之背面之鏡面潤飾,直至半導體晶圓之厚度成為30 μm為止。以如此方式,獲得保護片及分割後半導體晶圓之積層體。The surface of a 300 mm (12 inch) diameter semiconductor wafer (矽 wafer, thickness 80 μm) was cut into a depth of 100 μm. Next, a backside polishing tape Icross SB135S-BN (manufactured by Mitsui Chemicals, Inc., coated with an acrylic adhesive on one side of the olefin) as a protective sheet was laminated on the surface of the semiconductor wafer from the acrylic adhesive side. Next, the back surface of the semiconductor wafer is polished until the thickness of the semiconductor wafer is 35 μm, and then the slurry is polished using CMP (Chemical Mechanical Polishing) to polish the back surface of the semiconductor wafer until the thickness of the semiconductor wafer. It is 30 μm. In this manner, a laminate of the protective sheet and the divided semiconductor wafer is obtained.

其次,使用晶圓貼片機DAM-812M(Takatori公司製造),將切晶黏晶膜黏附於積層體之分割後半導體晶圓之背面及切晶環(外徑為400 mm,內徑為350 mm)。再者,搭載積層體之分割後半導體晶圓之平台設定成60℃。Next, a wafer mounter DAM-812M (manufactured by Takatori Co., Ltd.) was used to adhere the die-cutting film to the back surface of the divided semiconductor wafer and the dicing ring (outer diameter 400 mm, inner diameter 350). Mm). Further, the stage of the semiconductor wafer after the division of the laminated body was set to 60 °C.

其次,將黏附有黏著劑層之分割後半導體晶圓自平台取出並翻轉過來,搭載至另一平台上。其後,於60℃自分割後半導體晶圓之表面剝離保護片。Next, the divided semiconductor wafer to which the adhesive layer is adhered is taken out from the platform and turned over, and loaded onto another platform. Thereafter, the protective sheet was peeled off from the surface of the semiconductor wafer after division at 60 °C.

其次,使用切晶裝置DFL7160(迪思科(Disco)公司製造),於雷射輸出0.5 W、頻率50 kHz、傳送速度100 mm/秒、散焦量-0.05 mm、焦點位置為黏著劑層表面之條件下,將黏著劑層切晶成各個半導體晶片之大小。切晶後,使用黏晶機bestem D-02(佳能機械(Canon Machinery)公司製造),於夾頭尺寸8 mm見方、頂出速度5 mm/秒、拾取溫度23℃之條件下,連續地拾取20個附帶黏著劑層之半導體晶片。Secondly, using the crystal cutting device DFL7160 (manufactured by Disco), the laser output is 0.5 W, the frequency is 50 kHz, the transmission speed is 100 mm/sec, the defocus amount is -0.05 mm, and the focus position is the surface of the adhesive layer. The adhesive layer is diced to the size of each semiconductor wafer. After dicing, a die bonder Bextem D-02 (manufactured by Canon Machinery Co., Ltd.) was used to continuously pick up the chuck with a size of 8 mm square, an ejection speed of 5 mm/sec, and a pick-up temperature of 23 °C. 20 semiconductor wafers with an adhesive layer.

於上述附帶黏著劑層之半導體晶片之製造中,對下述(1)~(4)之評價項目進行評價。In the manufacture of the semiconductor wafer with the above adhesive layer, the evaluation items of the following (1) to (4) were evaluated.

(1) 突出性(1) Prominence

根據下述判定基準,判定將基材層之外周部分自黏附起點黏附於切晶環時之突出性。Based on the following criteria, the protrusion of the outer peripheral portion of the base material layer from the adhesion starting point to the dicing ring was determined.

[突出性之判定基準][Judging criteria for prominence]

○:可毫無問題地將基材層黏附於切晶環○: The substrate layer can be adhered to the dicing ring without any problem

×:存在無法將基材層之黏附起點黏附於切晶環之情形×: There is a case where the adhesion starting point of the substrate layer cannot be adhered to the dicing ring

(2)黏附後之基材層有無切斷或變形(2) Whether the substrate layer after adhesion is cut or deformed

根據下述判定基準,判定黏附於分割後半導體晶圓後之基材層有無切斷或變形。Based on the following criteria, it is determined whether or not the substrate layer adhered to the semiconductor wafer after the division is cut or deformed.

[黏附後之基材層有無切斷或變形之判定基準][Criteria for determining whether or not the substrate layer is adhered or deformed after adhesion]

○:於黏附後,基材層無切斷或變形○: After the adhesion, the substrate layer is not cut or deformed

△:於黏附後,基材層雖未被切斷,但被拉伸△: After the adhesion, the substrate layer is not cut but stretched

×:於黏附後,基材層被切斷×: After the adhesion, the substrate layer is cut off

(3)基材層之露出(3) Exposure of the substrate layer

根據下述判定基準,判定將基材層之外周部分自黏附起點黏附於切晶環時之基材層之露出。The exposure of the base material layer when the outer peripheral portion of the base material layer adhered to the dicing ring from the adhesion starting point was determined based on the following criteria.

[黏附後之基材層之露出的判定基準][Criteria for judging the exposure of the substrate layer after adhesion]

○:於黏附後,基材層未自切晶環露出○: After adhesion, the substrate layer is not exposed from the cleavage ring

×:於黏附後,基材層自切晶環露出×: After adhesion, the substrate layer is exposed from the dicing ring

(4)脊線位移(4) Ridge displacement

剝離保護片後,觀察分割後半導體晶圓之切斷部分,根據下述判定基準,對脊線位移進行判定。After the protective sheet was peeled off, the cut portion of the semiconductor wafer after the division was observed, and the ridge displacement was determined based on the following criteria.

[脊線位移之判定基準][Determination of ridge line displacement]

○:複數個半導體晶片之對齊排列無異常,於2個半導體晶片間之切斷部分之延長線上,無不存在鄰接於該2個半導體晶片之2個半導體晶片間之切斷部分的部分○: the alignment of the plurality of semiconductor wafers is not abnormal, and on the extension line of the cut portion between the two semiconductor wafers, there is no part of the cut portion between the two semiconductor wafers adjacent to the two semiconductor wafers

×:複數個半導體晶片之對齊排列存在異常,於2個半導體晶片間之切斷部分之延長線上,有不存在鄰接於該2個半導體晶片之2個半導體晶片間之切斷部分的部分×: There is an abnormality in the alignment of the plurality of semiconductor wafers, and there is no portion of the cut portion between the two semiconductor wafers adjacent to the cut portion of the two semiconductor wafers.

(5)拾取性(5) Pickup

根據下述判定基準,判定附帶黏著劑層之半導體晶片之拾取性。The pick-up property of the semiconductor wafer with the adhesive layer was determined based on the following criteria.

[拾取性之判定基準][Criteria for picking up]

○:沒有無法拾取之半導體晶片○: There are no semiconductor wafers that cannot be picked up.

×:有無法拾取之半導體晶片×: There are semiconductor wafers that cannot be picked up.

再者,該拾取不良的主要原因在於由脊線之異常(半導體晶片之對齊排列異常)所導致之半導體晶片之傾斜,其係因半導體晶片之識別不足所引起。Moreover, the main cause of the pickup failure is the tilt of the semiconductor wafer caused by the abnormality of the ridge line (the alignment of the semiconductor wafer is abnormal), which is caused by insufficient recognition of the semiconductor wafer.

將結果示於下述表5。The results are shown in Table 5 below.

1、51...切晶-黏晶帶1, 51. . . Cleavage-adhesive zone

2...脫模層2. . . Release layer

2a...上表面2a. . . Upper surface

3...黏著劑層3. . . Adhesive layer

3a、22a...一面3a, 22a. . . one side

3b...另一面3b. . . the other side

3c...外周側面3c. . . Peripheral side

3d、41c...切斷部分3d, 41c. . . Cut off part

4、11、12、52、101、102、103、104、105...基材層4, 11, 12, 52, 101, 102, 103, 104, 105. . . Substrate layer

4A、11A、12A...非黏著部4A, 11A, 12A. . . Non-adhesive part

4B、11B、12B...黏著部4B, 11B, 12B. . . Adhesive part

4C、11C、12C、52C...黏附起點4C, 11C, 12C, 52C. . . Sticking to the starting point

4a~4c、11a~11d、12a~12d...凸部4a~4c, 11a~11d, 12a~12d. . . Convex

5、53...切晶層5,53. . . Crystal layer

21...積層體twenty one. . . Laminated body

22...保護片twenty two. . . Protective sheet

23...分割後半導體晶圓twenty three. . . Divided semiconductor wafer

23A、41...半導體晶圓23A, 41. . . Semiconductor wafer

23a、41a...表面23a, 41a. . . surface

23b、41b...背面23b, 41b. . . back

23c...切口23c. . . incision

25、27...平台25, 27. . . platform

26...切晶環26. . . Cleavage ring

31...捲輥31. . . Roll

32...剝離邊緣32. . . Stripping edge

A1、A2、A3、A4、B1、B2...頂點A1, A2, A3, A4, B1, B2. . . vertex

A11...交叉點、凸部11b與凸部11c之間之凹部之最深部、凸部12a與凸部12b之間之凹部之最深部A11. . . The deepest portion of the intersection between the intersection, the convex portion 11b and the convex portion 11c, and the deepest portion of the concave portion between the convex portion 12a and the convex portion 12b

A12...凸部12b與凸部12c之間之凹部之最深部A12. . . The deepest part of the recess between the convex portion 12b and the convex portion 12c

A13...凸部12c與凸部12d之間之凹部之最深部A13. . . The deepest part of the recess between the convex portion 12c and the convex portion 12d

A21、A22、A23、A24...交叉點A21, A22, A23, A24. . . intersection

C1、C2...接點C1, C2. . . contact

I-I...線I-I. . . line

D...外徑D. . . Outer diameter

L...長度L. . . length

W...寬度W. . . width

圖1(a)及(b)係模式性地表示本發明之一實施形態之切晶-黏晶帶之局部欠缺平面圖及局部欠缺前視剖面圖;1(a) and 1(b) are schematic partial cross-sectional plan views and a partial front cross-sectional view of a diced-adhesive tape according to an embodiment of the present invention;

圖2係僅放大圖1所示之切晶-黏晶帶之基材層而模式性表示之局部欠缺平面圖;Figure 2 is a partial plan view showing the substrate layer of the diced-bonded ribbon shown in Figure 1 in a schematic manner;

圖3係模式性地表示切晶-黏晶帶之基材層之變形例之局部欠缺平面圖;3 is a partial lack plan view schematically showing a modification of the base layer of the diced-adhesive tape;

圖4係模式性地表示切晶-黏晶帶之基材層之其他變形例之局部欠缺平面圖;4 is a partial missing plan view schematically showing another modification of the base layer of the diced-adhesive tape;

圖5(a)~(d)係用以說明獲得製造附帶黏著劑層之半導體晶片時所使用之積層體之各步驟的一例之局部欠缺前視剖面圖;5(a) to 5(d) are partially broken front cross-sectional views for explaining an example of each step of obtaining a laminate used in the production of a semiconductor wafer with an adhesive layer;

圖6(a)~(b)係用以說明使用本發明之一實施形態之切晶-黏晶帶製造附帶黏著劑層之半導體晶片之方法之一例之局部欠缺前視剖面圖;6(a) to 6(b) are partially broken front cross-sectional views for explaining an example of a method of manufacturing a semiconductor wafer with an adhesive layer using a diced-bonded ribbon according to an embodiment of the present invention;

圖7(a)~(b)係用以說明使用本發明之一實施形態之切晶-黏晶帶製造附帶黏著劑層之半導體晶片之方法之一例之局部欠缺前視剖面圖;7(a) to 7(b) are partially fragmentary front cross-sectional views showing an example of a method of manufacturing a semiconductor wafer with an adhesive layer using a diced-bonded ribbon according to an embodiment of the present invention;

圖8(a)係表示將切晶-黏晶帶黏附於切晶環時之狀態之前視剖面圖,圖8(b)係表示將切晶-黏晶帶黏附於切晶環後之狀態之平面圖;Fig. 8(a) is a front cross-sectional view showing a state in which a dicing-adhesive tape is adhered to a dicing ring, and Fig. 8(b) is a view showing a state in which a dicing-adhesive tape is adhered to a dicing ring. Floor plan

圖9(a)及(b)係用以說明使用本發明之一實施形態之切晶-黏晶帶製造附帶黏著劑層之半導體晶片之其他方法之局部欠缺前視剖面圖;9(a) and 9(b) are partially fragmentary front cross-sectional views for explaining another method of manufacturing a semiconductor wafer with an adhesive layer using a diced-bonded ribbon according to an embodiment of the present invention;

圖10係模式性地表示比較例1之基材層之形狀之局部欠缺平面圖;Figure 10 is a partially broken plan view schematically showing the shape of the substrate layer of Comparative Example 1;

圖11係模式性地表示比較例2之基材層之形狀之局部欠缺平面圖;Figure 11 is a partially broken plan view schematically showing the shape of the substrate layer of Comparative Example 2;

圖12係模式性地表示比較例3之基材層之形狀之局部欠缺平面圖;Figure 12 is a partially broken plan view schematically showing the shape of the substrate layer of Comparative Example 3;

圖13係模式性地表示比較例4之基材層之形狀之局部欠缺平面圖;Figure 13 is a partially broken plan view schematically showing the shape of the substrate layer of Comparative Example 4;

圖14係模式性地表示比較例5之基材層之形狀之局部欠缺平面圖;及Figure 14 is a partially broken plan view schematically showing the shape of the substrate layer of Comparative Example 5;

圖15係模式性地表示圖1所示之切晶-黏晶帶之變形例之局部欠缺平面圖。Fig. 15 is a partially broken plan view schematically showing a modification of the diced-bonded ribbon shown in Fig. 1.

1...切晶-黏晶帶1. . . Cleavage-adhesive zone

2...脫模層2. . . Release layer

2a...上表面2a. . . Upper surface

3...黏著劑層3. . . Adhesive layer

3a...一面3a. . . one side

3b...另一面3b. . . the other side

3c...外周側面3c. . . Peripheral side

4...基材層4. . . Substrate layer

4A...非黏著部4A. . . Non-adhesive part

4B...黏著部4B. . . Adhesive part

4C...黏附起點4C. . . Sticking to the starting point

4a~4c...凸部4a~4c. . . Convex

5...切晶層5. . . Crystal layer

26...切晶環26. . . Cleavage ring

31...捲輥31. . . Roll

32...剝離邊緣32. . . Stripping edge

D...外徑D. . . Outer diameter

L...長度L. . . length

W...寬度W. . . width

Claims (7)

一種切晶-黏晶帶,其包含:黏著劑層;及基材層,其積層於上述黏著劑層之一面;且於切晶時,在上述基材層之外周部分黏附切晶環,上述基材層於外周部分含有在黏附開始時黏附於切晶環之黏附起點;將上述基材層之除上述黏附起點外之部分中之黏附於上述切晶環的部分之寬度設為W(mm),將上述基材層之除上述黏附起點外之部分中之外徑設為D(mm)時,自上述基材層之靠上述黏附起點側之外周前端朝向內側相距0.3W之距離的位置處之上述黏附起點之長度L(mm)為0.30D~0.44D(mm)之範圍內。A dicing-bonded ribbon comprising: an adhesive layer; and a substrate layer laminated on one side of the adhesive layer; and in the case of dicing, a dicing ring is adhered to a peripheral portion of the substrate layer, The base material layer has an adhesion starting point adhered to the dicing ring at the beginning of adhesion at the outer peripheral portion; and a width of a portion of the substrate layer excluding the adhesion starting point adhered to the dicing ring is set to W (mm) When the outer diameter of the portion of the base material layer other than the adhesion starting point is D (mm), the distance from the outer peripheral end of the base material layer to the inner side of the adhesion starting point side is 0.3 W. The length L (mm) of the above-mentioned adhesion starting point is in the range of 0.30D to 0.44D (mm). 如請求項1之切晶-黏晶帶,其中上述基材層之上述黏附起點側之外周前端之曲率大於上述基材層之除上述黏附起點外之部分之外周端的曲率。The dicing-bonded ribbon of claim 1, wherein a curvature of the outer peripheral end of the adhesion starting point side of the substrate layer is greater than a curvature of a peripheral end of the substrate layer other than the adhesion starting point. 如請求項1或2之切晶-黏晶帶,其中上述基材層於上述黏附起點側之外周端包含凸部;且上述基材層之黏附起點側之外周前端為上述凸部之頂點。The dicing-adhesive tape of claim 1 or 2, wherein the base material layer includes a convex portion at an outer peripheral end of the adhesion start point side; and an outer peripheral end of the base material layer on the adhesion start side is an apex of the convex portion. 如請求項1之切晶-黏晶帶,其中上述基材層於上述黏附起點側之外周端包含複數個凸部,且該複數個凸部由曲線連接。The dicing-bonded ribbon of claim 1, wherein the substrate layer comprises a plurality of convex portions at a peripheral end of the adhesion starting point side, and the plurality of convex portions are connected by a curve. 一種附帶黏著劑層之半導體晶片之製造方法,其包含如下步驟:使用如請求項1至4中任一項之切晶-黏晶帶、以及含有保護片及積層於該保護片之一面且分割成各個半導體晶片之分割後半導體晶圓之積層體,將上述切晶-黏晶帶之上述黏著劑層黏附於上述積層體之上述分割後半導體晶圓;將上述基材層之上述黏附起點黏附於圓環狀之切晶環,其次將除上述黏附起點外之上述基材層之外周部分黏附於上述切晶環;自上述分割後半導體晶圓剝離上述保護片;沿上述分割後半導體晶圓之切斷部分對上述黏著劑層進行切晶;及切晶後,自上述基材層剝離黏附有上述半導體晶片之上述黏著劑層,將半導體晶片連同上述黏著劑層一併取出。A method of manufacturing a semiconductor wafer with an adhesive layer, comprising the steps of: using a dicing-bonding ribbon according to any one of claims 1 to 4, and comprising a protective sheet and laminating one side of the protective sheet and dividing a layered body of the divided semiconductor wafers of the respective semiconductor wafers, the adhesion layer of the diced-bonded ribbon is adhered to the divided semiconductor wafer of the laminate; and the adhesion starting point of the substrate layer is adhered a ring-shaped dicing ring, and secondly, a peripheral portion of the substrate layer excluding the adhesion starting point is adhered to the dicing ring; the protective film is peeled off from the divided semiconductor wafer; and the semiconductor wafer is separated along the segment The cut portion is diced to the adhesive layer; and after the dicing, the adhesive layer of the semiconductor wafer is peeled off from the base material layer, and the semiconductor wafer is taken out together with the adhesive layer. 如請求項5之附帶黏著劑層之半導體晶片之製造方法,其中進而包含如下步驟:於半導體晶圓之表面,形成用以將該半導體晶圓分割成各個半導體晶片之切口;於形成有切口之上述半導體晶圓之表面黏附保護片;及研磨黏附有上述保護片之上述半導體晶圓之背面,將上述半導體晶圓分割成各個半導體晶片,從而獲得上述積層體。The method for fabricating a semiconductor wafer with an adhesive layer according to claim 5, further comprising the steps of: forming a slit for dividing the semiconductor wafer into individual semiconductor wafers on a surface of the semiconductor wafer; The surface of the semiconductor wafer is adhered to the protective sheet; and the back surface of the semiconductor wafer to which the protective sheet is adhered is polished, and the semiconductor wafer is divided into individual semiconductor wafers to obtain the laminated body. 一種附帶黏著劑層之半導體晶片之製造方法,其包含如下步驟:使用如請求項1至4中任一項之切晶-黏晶帶及半導體晶圓,將上述切晶-黏晶帶之上述黏著劑層黏附於上述半導體晶圓;將上述基材層之上述黏附起點黏附於圓環狀之切晶環,其次將除上述黏附起點外之上述基材層之外周部分黏附於上述切晶環;對上述半導體晶圓及上述黏著劑層進行切晶;及切晶後,自上述基材層剝離黏附有上述半導體晶片之上述黏著劑層,將半導體晶片連同上述黏著劑層一併取出。A method of manufacturing a semiconductor wafer with an adhesive layer, comprising the steps of: using the diced-bonded ribbon and the semiconductor wafer according to any one of claims 1 to 4, Adhesive layer is adhered to the semiconductor wafer; the adhesion starting point of the substrate layer is adhered to the annular dicing ring, and then the outer peripheral portion of the substrate layer except the adhesion starting point is adhered to the cleavage ring The semiconductor wafer and the adhesive layer are diced, and after the dicing, the adhesive layer of the semiconductor wafer is peeled off from the substrate layer, and the semiconductor wafer is taken out together with the adhesive layer.
TW100104469A 2010-02-12 2011-02-10 A method for manufacturing a semiconductor wafer with a spin - die tape and an adhesive layer TWI498955B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010028682 2010-02-12

Publications (2)

Publication Number Publication Date
TW201140676A TW201140676A (en) 2011-11-16
TWI498955B true TWI498955B (en) 2015-09-01

Family

ID=44367746

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100104469A TWI498955B (en) 2010-02-12 2011-02-10 A method for manufacturing a semiconductor wafer with a spin - die tape and an adhesive layer

Country Status (5)

Country Link
JP (2) JP4902812B2 (en)
KR (1) KR20120120292A (en)
CN (1) CN102844843A (en)
TW (1) TWI498955B (en)
WO (1) WO2011099473A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI749111B (en) * 2016-11-29 2021-12-11 日商琳得科股份有限公司 Double-sided adhesive sheet and manufacturing method of semiconductor device

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5651051B2 (en) * 2011-03-11 2015-01-07 積水化学工業株式会社 Dicing-die bonding tape and method for manufacturing semiconductor chip with adhesive layer
JP6823921B2 (en) * 2015-09-28 2021-02-03 リンテック株式会社 Sheet manufacturing equipment and manufacturing method, and sheet pasting equipment and sticking method
JP2017163009A (en) * 2016-03-10 2017-09-14 東芝メモリ株式会社 Method of manufacturing semiconductor device
JP6790025B2 (en) * 2018-05-31 2020-11-25 古河電気工業株式会社 Manufacturing method of electronic device processing tape and electronic device processing tape

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005116790A (en) * 2003-10-08 2005-04-28 Hitachi Chem Co Ltd Process film for manufacturing semiconductor element and dicing/die bonding integrated tape
JP2006245467A (en) * 2005-03-07 2006-09-14 Disco Abrasive Syst Ltd Laser-machining method and laser-machining apparatus
JP2006295774A (en) * 2005-04-14 2006-10-26 Konica Minolta Photo Imaging Inc Imaging apparatus, control method thereof, and image processing program for digital camera

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005036633A1 (en) * 2003-10-07 2005-04-21 Nagase & Co., Ltd. Process for producing electronic member, and ic chip with adhesive
CN100428418C (en) * 2004-02-09 2008-10-22 株式会社迪斯科 Method for cutting wafer
JP4503429B2 (en) * 2004-02-10 2010-07-14 リンテック株式会社 Manufacturing method of semiconductor device
JP4677758B2 (en) * 2004-10-14 2011-04-27 日立化成工業株式会社 Die-bonded dicing sheet, method for manufacturing the same, and method for manufacturing a semiconductor device
JP2009256458A (en) * 2008-04-16 2009-11-05 Hitachi Chem Co Ltd Pressure-sensitive adhesive sheet and method for manufacturing semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005116790A (en) * 2003-10-08 2005-04-28 Hitachi Chem Co Ltd Process film for manufacturing semiconductor element and dicing/die bonding integrated tape
JP2006245467A (en) * 2005-03-07 2006-09-14 Disco Abrasive Syst Ltd Laser-machining method and laser-machining apparatus
JP2006295774A (en) * 2005-04-14 2006-10-26 Konica Minolta Photo Imaging Inc Imaging apparatus, control method thereof, and image processing program for digital camera

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI749111B (en) * 2016-11-29 2021-12-11 日商琳得科股份有限公司 Double-sided adhesive sheet and manufacturing method of semiconductor device

Also Published As

Publication number Publication date
JP4902812B2 (en) 2012-03-21
WO2011099473A1 (en) 2011-08-18
JP2012084916A (en) 2012-04-26
KR20120120292A (en) 2012-11-01
CN102844843A (en) 2012-12-26
JPWO2011099473A1 (en) 2013-06-13
TW201140676A (en) 2011-11-16

Similar Documents

Publication Publication Date Title
US7438631B2 (en) Surface-protecting sheet and semiconductor wafer lapping method
TWI498955B (en) A method for manufacturing a semiconductor wafer with a spin - die tape and an adhesive layer
WO2003043076A2 (en) Surface protective sheet for use in wafer back grinding and process for producing semiconductor chip
KR101186064B1 (en) Protective structure of semiconductor wafer, method for protecting semiconductor wafer, multilayer protective sheet used therein, and method for processing semiconductor wafer
KR102171423B1 (en) Sheet for forming resin film
JP5438522B2 (en) Dicing die bonding tape and manufacturing method thereof
JP5522773B2 (en) Semiconductor wafer holding method, chip body manufacturing method, and spacer
JP2011199008A (en) Method for manufacturing pressure-sensitive adhesive sheet, dicing-die bonding tape, and semiconductor chip with pressure-sensitive adhesive sheet
JP5006126B2 (en) Wafer surface protection tape and wafer grinding method
JP5651051B2 (en) Dicing-die bonding tape and method for manufacturing semiconductor chip with adhesive layer
JP2009130333A (en) Manufacturing method of semiconductor device
TWI803567B (en) Long laminated sheet and its coil
JP2007250790A (en) Manufacturing method of semiconductor chip
JP2013129723A (en) Pressure-sensitive adhesive sheet and production method of semiconductor chip
TW201518467A (en) Dicing/die-bonding tape and method for manufacturing semiconductor chip provided with adhesive layer
KR20210142584A (en) Semiconductor device manufacturing method and laminate
TWI791742B (en) Coils of long laminated sheets
TWI797238B (en) Long laminated sheet and its coil
TW202200730A (en) Method for wafer backside polishing and method for wafer carrying
JP2013065625A (en) Dicing-die bonding tape, manufacturing kit of semiconductor chip with adhesive layer and manufacturing method of semiconductor chip with adhesive layer
TW201633388A (en) Wafer processing tape
JP2014060201A (en) Dicing-die bonding tape and manufacturing method of semiconductor chip with adhesive layer
JP2015076421A (en) Dicing/die bonding tape and method for manufacturing semiconductor chip with pressure-sensitive adhesive layer
JP2014063896A (en) Dicing-die bonding tape and manufacturing method of semiconductor chip with adhesive layer
JP2013207032A (en) Dicing-die bonding tape and manufacturing method for semiconductor chip with adhesive layer

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees