TWI493667B - 具有後鈍化互連結構之半導體元件及形成具有後鈍化互連結構之半導體元件之方法 - Google Patents

具有後鈍化互連結構之半導體元件及形成具有後鈍化互連結構之半導體元件之方法 Download PDF

Info

Publication number
TWI493667B
TWI493667B TW102136061A TW102136061A TWI493667B TW I493667 B TWI493667 B TW I493667B TW 102136061 A TW102136061 A TW 102136061A TW 102136061 A TW102136061 A TW 102136061A TW I493667 B TWI493667 B TW I493667B
Authority
TW
Taiwan
Prior art keywords
pad
contact
dummy
opening
forming
Prior art date
Application number
TW102136061A
Other languages
English (en)
Other versions
TW201436134A (zh
Inventor
Hsienwei Chen
Tsungyuan Yu
Haoyi Tsai
Mirngji Lii
Chenhua Yu
Original Assignee
Taiwan Semiconductor Mfg Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg Co Ltd filed Critical Taiwan Semiconductor Mfg Co Ltd
Publication of TW201436134A publication Critical patent/TW201436134A/zh
Application granted granted Critical
Publication of TWI493667B publication Critical patent/TWI493667B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02233—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body not in direct contact with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02233—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body not in direct contact with the bonding area
    • H01L2224/02235—Reinforcing structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0235—Shape of the redistribution layers
    • H01L2224/02351—Shape of the redistribution layers comprising interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02375—Top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/03013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the bonding area, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/03019—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for protecting parts during the process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05555—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05681—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/1191—Forming a passivation layer after forming the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

具有後鈍化互連結構之半導體元件及形成具有後鈍化 互連結構之半導體元件之方法
本申請案主張於2013年3月15日提出申請之標題為「SEMICONDUCTOR DEVICE WITH POST-PASSIVATION INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME」之美國臨時申請案第61/790,958號之優先權，該申請案在此以引用之方式併入本文。
本發明係關於具有後鈍化互連結構之半導體元件及形成具有後鈍化互連結構之半導體元件之方法。
半導體元件係使用在各種電子應用中，諸如個人電腦、蜂巢式電話、數位攝影機及其他電子設備。半導體工業藉由持續縮減最小特徵尺寸持續改良各種電子組件(例如，電晶體、二極體、電阻、電容器等)之整合密度，此舉允許將更多組件整合至給定面積內。在一些應用中，該等更小電子組件也要求更小封裝，該等更小封裝利用比過去的封裝更少的面積。
已開發之用於半導體元件之一種更小封裝類型係晶圓級封裝(wafer level packaging；WLP)，其中將積體電路晶粒封裝在封裝件中，該等封裝件通常包括後鈍化互連(post-passivation interconnect；PPI)結構或再分配層(redistribution layer；RDL)，該PPI結構或RDL係用來扇出用於積體電路晶粒之接觸墊之接線，使得可在大於晶粒之接觸墊的節距或墊上進行電氣接觸。WLP封裝由於WLP封裝之簡單結構的優勢而越來越多應用在積體電路封裝中。然而，對於一些WLP封裝，用於WLP封裝之底層凸塊金屬化(under bump metallization；UBM)層可相對昂貴。對於無UBM層之一些其他低成本WLP封裝，在諸如焊球之連接元件與PPI結構之間的黏著可產生問題，諸如焊球裂縫之較高發生率。設計無UBM層之低成本WLP封裝同時增加在諸如焊球之連接元件與PPI結構之間的黏著是一個挑戰。
在一實施方式中，揭露一種半導體元件，包含：一接觸墊及一虛設墊(dummy pad)，上覆於一半導體基板；一保護層，上覆於該接觸墊及該虛設墊；一互連結構，上覆於該保護層且包含設置在該虛設墊上方之一安裝墊部分，其中該安裝墊部分包含一接觸穿孔，該接觸穿孔通過該保護層且接觸部分的該虛設墊；及一凸塊，上覆於該互連結構之該安裝墊部分。
在一實施方式中，揭露一種形成一半導體元件 之方法，包含：在一半導體基板上方形成一接觸墊；在一半導體基板上方形成一虛設墊，該虛設墊與該接觸墊間隔開；形成上覆於該接觸墊、該虛設墊及該半導體基板之一聚合物層；形成該聚合物層中之一第一開口，該第一開口暴露部分的該接觸墊；形成該聚合物層中之一第二開口，該第二開口暴露部分的該虛設墊；形成一導電層，該導電層上覆於該聚合物層且經由該第一開口及該第二開口接觸該接觸墊之該暴露部分及該虛設墊之該暴露部分；及在該導電層上形成一凸塊，該凸塊設置在該虛設墊上方。
10‧‧‧半導體基板
12‧‧‧金屬層
14‧‧‧介電層
15‧‧‧開口
16‧‧‧接觸墊
18‧‧‧虛設墊
18e‧‧‧邊緣
20‧‧‧鈍化層
24‧‧‧互連結構
28‧‧‧模製化合物
100"‧‧‧半導體元件
242‧‧‧部分
243e‧‧‧端
244‧‧‧接觸穿孔
244e"‧‧‧邊緣
18e"‧‧‧邊緣
22‧‧‧保護層
26‧‧‧凸塊
100‧‧‧半導體元件
201‧‧‧第一開口
202‧‧‧第二開口
221‧‧‧第三開口
222‧‧‧第四開口
241‧‧‧部分
243‧‧‧部分
243e"‧‧‧邊緣
244e‧‧‧邊緣
S1‧‧‧間隔
S2‧‧‧間隔
S3‧‧‧間隔
為使更全面理解本發明及本發明之優勢，現在連同隨附圖式參考下列描述，其中：第1圖至第4圖圖示根據實施例中間步驟在形成後鈍化互連(PPI)結構中之剖視圖；第5A圖至第5C圖以自上而下的視角圖示後鈍化互連(PPI)結構之實例；第6圖圖示根據一些實施例形成於後鈍化互連(PPI)結構上之凸塊的剖視圖；第7圖圖示根據一些實施例模製化合物在凸塊及後鈍化互連(PPI)結構上之剖視圖；第8圖圖示根據另一實施例之後鈍化互連(PPI)結構之剖視圖；及第9圖以自上而下的視角圖示第8圖中圖示之後鈍化互 連(PPI)結構之實例。
在不同圖式中之對應數字及符號大體係指對應部分，除非另有陳述。繪圖以圖示實施例之相關態樣且不一定按比例繪製。
下文詳細論述所提供實施例之製造及使用。然而，應瞭解，本發明提供可在各式各樣的特定上下文中實施之許多可應用概念。所論述之特定實施例僅說明製造及使用所述傳導互連或接頭(「互連」)之具體方式，且不限制本發明之範疇。
將相對於特定上下文而描述實施例，即在製造及使用例如用於扇入或扇出晶圓級封裝總成或WLCSP總成之互連。然而，其他實施例亦可應用於其他以電氣方式連接之組件，包括但不限於堆疊封裝總成、晶粒至晶粒總成、晶圓至晶圓總成、晶粒至基板總成、用在裝配封裝中、用在處理基板中、仲介層、基板或類似物，或安裝輸入組件、板、晶粒或其他組件，或用於任何類型積體電路或電氣組件之連接封裝或安裝組合。
參閱第1圖至第9圖描述本發明之實施例，且亦論述實施例之變體。在本發明之各種視圖及說明性實施例上，相同元件符號係用來指定相同元件。另外，圖式意欲為說明性、不按比例且不意欲為限制。應注意，為簡單化，並非所有的元件符號皆包括在每個後續圖式中。相反，將與每 個圖式之描述最相關的元件符號包括在每個圖式中。
第1圖為圖示根據實施例之半導體元件100之形成的剖視圖，半導體元件100包括上覆於半導體基板10之接觸墊16及虛設墊18。
半導體基板10係由矽或其他塊狀半導體材料構成。半導體基板10可為晶圓、晶粒或基礎半導體晶圓之部分。主動元件及被動元件、導電層及介電層可根據晶粒之電氣設計而形成在半導體基板10中或半導體基板10上。在實施例中，半導體基板10包括頂級金屬層12及上覆於金屬層12之頂級介電層14，其中介電層14包括暴露部分金屬層12之圖案化開口15。開口15為用於以電氣方式連接隨後形成之接觸墊及互連結構的窗口。在實施例中，間隔開之接觸墊16及虛設墊18隨後形成在介電層14上之相同水平處。接觸墊16係經由介電層14之開口15以電氣方式連接至金屬層12，而虛設墊18係在無服務於半導體基板10與任何其他連接器或基板之間的電氣連接的情況下形成於介電層14上。在一些實施例中，接觸墊16及虛設墊18係由導電材料(諸如鋁(Al)、銅(Cu)、Al合金、Cu合金或另一類似材料)形成。
第2圖為圖示根據實施例鈍化層20之形成的剖視圖。
鈍化層20係沉積在半導體基板10及接觸墊16及虛設墊18上方。在實施例中，鈍化層20經遮蔽及蝕刻以具有分別暴露部分的接觸墊16及虛設墊18的第一開口201 及第二開口202。在一些實施例中，鈍化層20包括介電層、聚合物層或前述各者之組合。鈍化層20可為單層或層壓層。
第3圖為圖示根據實施例之保護層22之形成的剖視圖。
保護層22係形成於鈍化層20上。在實施例中，保護層22經遮蔽及蝕刻以形成第三開口221及第四開口222。第三開口221係形成在第一開口201內，以使得保護層22經由第一開口201接觸部分的接觸墊16且暴露部分的接觸墊16。類似地，第四開口222係形成在第二開口202內，以使得保護層22經由第二開口202接觸部分的虛設墊18且暴露部分的虛設墊18。在實施例中，保護層22中之第四開口222之直徑(d1)係在約20微米(μm)至約100μm的範圍內。在一些實施例中，保護層22係由聚合物、聚醯亞胺、氮化物、氧化物或其他非導電層形成。保護層22可為單層或層壓層。
第4圖為圖示根據實施例之互連結構24之形成的剖視圖。
互連結構24(亦稱為後鈍化互連(PPI)結構24)係形成於保護層22上且分別經由開口221及開口222接觸接觸墊16之暴露部分及虛設墊18之暴露部分。在實施例中，PPI結構24包括三個連續連接部分241、242及243。部分241為接觸墊部分241，設置在接觸墊16上方且經由開口221以電氣方式連接接觸墊16。部分243為安裝墊部分243，設 置在虛設墊18上方且經由開口222接觸虛設墊18。安裝墊部分243包括形成於保護層22之開口222中的至少一個接觸穿孔244且接觸虛設墊18。部分242為跡線(trace)部分242，設置在兩個部分241與243之間。在一些實施例中，PPI結構24包括由以下各者形成之至少一個導電層：Al、Cu、Al合金、Cu合金、鈦(Ti)、鉭(Ta)、氮化鈦(TiN)、氮化鉭(TaN)、鈦鎢(TiW)、鉻(Cr)、鎳(Ni)、金(Au)或前述各者之組合。由剖視圖可見，第4圖圖示在保護層22之開口222中的僅一個接觸穿孔244。以自上而下的視角可有複數個此等接觸穿孔。
第5A圖至第5C圖以自上而下的視角圖示安裝墊部分243及虛設墊18之實例。
第5A圖圖示具有僅一個接觸穿孔244接觸虛設墊18之安裝墊部分243。接觸穿孔244可成形為圓形形狀、矩形形狀、正方形形狀、多邊形形狀或類似物。舉例而言，接觸穿孔244之直徑(d2)係在約20μm至約100μm的範圍內。在實施例中，安裝墊部分243之尺寸係小於虛設墊18之尺寸。可調整在安裝墊部分243與虛設墊18之間的對應位置以滿足元件性能及製程控制之需要。舉例而言，自安裝墊部分243之一端243e至虛設墊18鄰近於端243e之邊緣18e的距離D(亦稱為外殼尺寸)係約5μm或更大。
第5B圖圖示具有三個接觸穿孔244接觸虛設墊18之安裝墊部分243。在示例性實施例中，三個接觸穿孔244係分別形成在保護層22之三個開口222中。舉例而言，在兩 個鄰近接觸穿孔244之間的間隔S1為約20μm或更大，且在接觸穿孔244之邊緣244e與安裝墊部分243鄰近於邊緣244e之邊緣243e”之間的間隔S2為約5μm或更大。在實施例中，安裝墊部分243之尺寸係小於虛設墊18之尺寸。舉例而言，在安裝墊部分243與虛設墊18之間的外殼尺寸(距離D)為約5μm或更大。
第5C圖圖示虛設墊18上的四個接觸穿孔244。在示例性實施例中，四個接觸穿孔244係分別形成在保護層22之四個開口222中。舉例而言，在接觸穿孔244之邊緣244e與安裝墊部分243鄰近於邊緣244e之邊緣243e”之間的間隔S2為約5μm或更大。在實施例中，安裝墊部分243之尺寸係小於虛設墊18之尺寸。舉例而言，在安裝墊部分243與虛設墊18之間的外殼尺寸(距離D)為約5μm或更大。
第6圖圖示根據一些實施例在PPI結構24上形成凸塊26的剖視圖。
在實施例中，將凸塊26應用於安裝墊部分243使得球26接觸安裝墊部分243之上表面。舉例而言，球26可接觸且覆蓋安裝墊部分243之全部或一部分。在實施例中，凸塊26係藉由將焊球附接至安裝墊部分243且隨後將焊接材料熱回焊而形成之焊接凸塊。在實施例中，焊接凸塊具有大於約200μm之直徑。在一些實施例中，焊接凸塊包括無鉛預焊接層、SnAg或焊接材料，該焊接材料包括錫、鉛、銀、銅、鎳、鉍之合金或前述各者之組合。在一些實施例中， 焊接凸塊係藉由使用光微影技術接著進行回焊製程鍍敷焊接層而形成。
凸塊26係與安裝墊部分243接觸且設置在接觸穿孔244上方。連同在形成保護層22之開口222中的設計一起，接觸穿孔244可維持準確的球安裝位置以在球安裝及/或回焊製程期間防止球移位且為焊球提供更高強度的支撐及更好的黏著。此外，在接觸穿孔244及凸塊26下方的虛設墊18可改良在鈍化層20與PPI結構24之間的黏著，導致在凸塊方案下之更強健互連結構。
第7圖為根據實施例塗覆模製化合物28之剖視圖。
模製化合物28係塗覆於PPI結構24及保護層22上，且凸塊26係部分埋在模製化合物28中。在一些實施例中，模製化合物28係與凸塊26之下部分實體接觸，而凸塊26之上部分暴露且自模製化合物28之頂部表面突出。在一些實施例中，埋在模製化合物28中之凸塊26之高度係在凸塊26之總高度的約¼至¾之間。在至少一個實施例中，模製化合物28係藉由塗覆液體模製化合物且執行固化製程以固化且凝固液體模製化合物而形成。在一些實施例中，可將離型膜或軟材料塗覆於液體模製化合物上。將壓力施加於液體模製化合物上之離型膜上，以便將部分的凸塊26按壓至離型膜內。此外，施加於離型膜上之壓力可向下推動一些液體模製化合物。當將壓力施加於離型膜以推動與凸塊及液體模 製化合物相抵時，可執行固化來固化且凝固液體模製化合物。此後，將離型膜剝離模製化合物28，模製化合物28此刻處於固態。隨後蝕刻餘留在凸塊26之頂部分上的模製化合物28殘留。
在凸塊形成之後，例如，封裝材料可形成於半導體元件100上，可執行單一化製程以單一化個別元件，且可執行晶圓級或晶粒級堆疊或類似製程。實施例可用於許多不同情況。舉例而言，實施例可用於元件至元件接合設置、元件至晶圓接合設置、晶圓至晶圓接合設置、元件級封裝、晶圓級封裝或類似物。在一些實施例中，將第7圖圖示之半導體元件倒置翻轉且附接至另一基板，以形成封裝總成。第1圖至第7圖圖示之製程僅用於說明目的，且不為限制。可存在熟習此項技術者容易可見之處理步驟及處理材料的許多變體。
第8圖為圖示半導體元件100”之另一實施例之剖視圖，半導體元件100”包括虛設墊18上之PPI結構24。形成第8圖圖示之結構的製程與第1圖至第4圖圖示之製程具有部分重疊。第1圖至第4圖中的描述可同樣適用於第8圖圖示之重疊部分。
保護層22具有暴露部分的虛設墊18的開口222。在實施例中，保護層22中之開口222的直徑(d1)係在約20μm至約100μm的範圍內。PPI結構24係形成於保護層24上，且在虛設墊18上方具有安裝墊部分243。安裝墊 部分243具有形成於開口222中之接觸穿孔244且接觸虛設墊18。安裝墊部分243之尺寸係大於虛設墊18之尺寸。第9圖以自上而下的視角圖示第8圖圖示之安裝墊部分243及虛設墊18之實例。舉例而言，在接觸穿孔244之邊緣244e”與虛設墊18之邊緣18e”之間的間隔S3為約5μm或更大。
根據實施例，半導體元件包括：保護層，上覆於半導體基板上之接觸墊及虛設墊；互連結構，上覆於保護層且經由通過保護層之接觸穿孔接觸部分的虛設墊；凸塊，上覆於設置在虛設墊上方的互連結構。
根據另一實施例，半導體元件包括：上覆於半導體基板之接觸墊及虛設墊；保護層，上覆於接觸墊及虛設墊，其中保護層具有暴露部分接觸墊之第一開口及暴露部分虛設墊之第二開口；互連結構，上覆於保護層，其中互連結構包含：設置在接觸墊上方且經由保護層之第一開口以電氣方式連接至接觸墊之第一部分，及設置在虛設墊上方且經由保護層之第二開口實體上接觸虛設墊之第二部分；及凸塊，實體上接觸互連結構之第二部分。
根據另一實施例，形成半導體元件之方法包括以下步驟：在半導體基板上方形成接觸墊；在半導體基板上方形成虛設墊，虛設墊與接觸墊間隔開；形成上覆於接觸墊、虛設墊及半導體基板之聚合物層；在聚合物層中形成第一開口，第一開口暴露部分的接觸墊；在聚合物層中形成第二開口，第二開口暴露部分的虛設墊；形成導電層，導電層上覆 於聚合物層且經由第一開口及第二開口接觸接觸墊及虛設墊之暴露部分；及在導電層上形成凸塊，凸塊設置在虛設墊上方。
儘管已詳細描述本發明之實施例及本發明之實施例的優勢，但應理解，在不脫離藉由隨附申請專利範圍所界定之本發明之精神及範疇的情況下本文可進行各種改變、置換及變更。舉例而言，熟習此項技術者將容易理解，本文描述之許多特徵、功能、製程及材料可變化，同時仍保持在本發明之範疇內。此外，本發明之範疇不意欲局限於本說明書中所描述之製程、機器、製造、及物質之組成、構件、方法或步驟之特定實施例。因為熟習此項技術者將由本發明之揭示內容容易瞭解到，可根據本發明利用目前存在或以後將開發之執行實質上與本文描述之對應實施例相同的功能或實現實質上與本文描述之對應實施例相同的結果的製程、機器、製造、物質之組成、構件、方法或步驟。因此，隨附申請專利範圍意欲包括在申請專利範圍範疇內包括該等製程、機器、製造、物質之組成、構件、方法或步驟。
10‧‧‧半導體基板
12‧‧‧金屬層
14‧‧‧介電層
16‧‧‧接觸墊
18‧‧‧虛設墊
20‧‧‧鈍化層
22‧‧‧保護層
24‧‧‧互連結構
26‧‧‧凸塊
28‧‧‧模製化合物
100‧‧‧半導體元件
244‧‧‧接觸穿孔

Claims (10)

  1. 一種半導體元件，包含：一接觸墊及一虛設墊，上覆於一半導體基板；一保護層，上覆於該接觸墊及該虛設墊；一互連結構，上覆於該保護層且包含設置在該虛設墊上方之一安裝墊部分，其中該安裝墊部分包含一接觸穿孔，該接觸穿孔通過該保護層且接觸部分的該虛設墊；及一凸塊，上覆於該互連結構之該安裝墊部分。
  2. 如請求項1所述之半導體元件，其中該互連結構包含一接觸墊部分，該接觸墊部分設置在該接觸墊上方且經由該保護層中之一開口以電氣方式連接至該接觸墊。
  3. 如請求項2所述之半導體元件，其中該互連結構包含一跡線部分，該跡線部分連接該安裝墊部分及該接觸墊部分。
  4. 如請求項1所述之半導體元件，進一步包含一模製化合物，該模製化合物上覆於該互連結構且與該凸塊之一下部分實體接觸。
  5. 如請求項1所述之半導體元件，其中上覆於該半導體基板之該接觸墊及該虛設墊係形成在相同水平處。
  6. 如請求項1所述之半導體元件，進一步包含在該保護層與該虛設墊之間的一鈍化層。
  7. 如請求項1所述之半導體元件，其中該安裝墊部分包含複數個接觸穿孔，該複數個接觸穿孔通過該保護層且接觸部分的該虛設墊。
  8. 如請求項7所述之半導體元件，其中在兩個鄰近接觸穿孔之間的一間隔為約20μm或更大。
  9. 一種形成一半導體元件之方法，包含：在一半導體基板上方形成一接觸墊；在一半導體基板上方形成一虛設墊，該虛設墊與該接觸墊間隔開；形成上覆於該接觸墊、該虛設墊及該半導體基板之一聚合物層；形成該聚合物層中之一第一開口，該第一開口暴露部分的該接觸墊；形成該聚合物層中之一第二開口，該第二開口暴露部分的該虛設墊；形成一導電層，該導電層上覆於該聚合物層且經由該第一開口及該第二開口接觸該接觸墊之該暴露部分及該虛設墊之該暴露部分；及 在該導電層上形成一凸塊，該凸塊設置在該虛設墊上方。
  10. 如請求項9所述之方法，進一步包含：在該導電層上形成一模製化合物且覆蓋該凸塊之一下部分。
TW102136061A 2013-03-15 2013-10-04 具有後鈍化互連結構之半導體元件及形成具有後鈍化互連結構之半導體元件之方法 TWI493667B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201361790958P 2013-03-15 2013-03-15
US13/870,674 US9013038B2 (en) 2013-03-15 2013-04-25 Semiconductor device with post-passivation interconnect structure and method of forming the same

Publications (2)

Publication Number Publication Date
TW201436134A TW201436134A (zh) 2014-09-16
TWI493667B true TWI493667B (zh) 2015-07-21

Family

ID=51523881

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102136061A TWI493667B (zh) 2013-03-15 2013-10-04 具有後鈍化互連結構之半導體元件及形成具有後鈍化互連結構之半導體元件之方法

Country Status (2)

Country Link
US (2) US9013038B2 (zh)
TW (1) TWI493667B (zh)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9355978B2 (en) 2013-03-11 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices and methods of manufacture thereof
US9196529B2 (en) * 2013-09-27 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Contact pad for semiconductor devices
US9379075B2 (en) 2014-01-28 2016-06-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with bump stop structure
US9691686B2 (en) 2014-05-28 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Contact pad for semiconductor device
KR102440135B1 (ko) * 2015-08-21 2022-09-05 삼성전자주식회사 재배선 영역을 갖는 전자 소자
US9871017B2 (en) * 2016-01-04 2018-01-16 Infineon Technologies Ag Multi-level chip interconnect
US10199318B2 (en) 2016-05-19 2019-02-05 Mediatek Inc. Semiconductor package assembly
US9984987B2 (en) * 2016-08-05 2018-05-29 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
KR102658923B1 (ko) * 2016-09-12 2024-04-18 삼성전자주식회사 반도체 장치 및 반도체 패키지
US10453811B2 (en) 2016-11-29 2019-10-22 Taiwan Semiconductor Manufacturing Company, Ltd. Post passivation interconnect and fabrication method therefor
US10580753B2 (en) * 2017-07-21 2020-03-03 Infineon Technologies Ag Method for manufacturing semiconductor devices
US10763199B2 (en) * 2018-12-24 2020-09-01 Nanya Technology Corporation Semiconductor package structure and method for preparing the same
TWI805216B (zh) * 2022-02-09 2023-06-11 矽品精密工業股份有限公司 電子封裝件及其基板結構

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030136979A1 (en) * 2001-11-19 2003-07-24 Samsung Electronics Co., Ltd. Bonding pad structure of a semiconductor device and method for manufacturing the same
US20120299167A1 (en) * 2011-05-27 2012-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Uniformity control for ic passivation structure

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006037587A1 (de) 2006-08-11 2008-02-14 Advanced Chip Engineering Technology Inc. Halbleitervorrichtungs-Schutzstruktur und Verfahren zum Herstellen derselben

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030136979A1 (en) * 2001-11-19 2003-07-24 Samsung Electronics Co., Ltd. Bonding pad structure of a semiconductor device and method for manufacturing the same
US20120299167A1 (en) * 2011-05-27 2012-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Uniformity control for ic passivation structure

Also Published As

Publication number Publication date
US20150228598A1 (en) 2015-08-13
US20140264837A1 (en) 2014-09-18
US9013038B2 (en) 2015-04-21
US9443812B2 (en) 2016-09-13
TW201436134A (zh) 2014-09-16

Similar Documents

Publication Publication Date Title
TWI493667B (zh) 具有後鈍化互連結構之半導體元件及形成具有後鈍化互連結構之半導體元件之方法
US11961742B2 (en) Semiconductor device and manufacturing method thereof
TWI598966B (zh) 半導體裝置及其形成方法
KR102591618B1 (ko) 반도체 패키지 및 반도체 패키지의 제조 방법
CN109994389B (zh) 半导体封装结构及其制造方法
KR101803612B1 (ko) 3ｄ 패키지 구조 및 그 형성 방법
TWI819767B (zh) 半導體封裝以及製造其之方法
US10153240B2 (en) Method of packaging semiconductor devices
TWI550787B (zh) 晶粒中的環狀結構
US9111949B2 (en) Methods and apparatus of wafer level package for heterogeneous integration technology
TWI710085B (zh) 半導體結構及其製造方法
KR102642327B1 (ko) 반도체 디바이스 및 그 제조 방법
US20140187103A1 (en) System and Method for an Improved Fine Pitch Joint
TW202320262A (zh) 半導體裝置及其製造方法
TWI721038B (zh) 封裝結構、疊層封裝元件及其形成方法
US20150228594A1 (en) Via under the interconnect structures for semiconductor devices
TWI611486B (zh) 半導體結構及其製法
US10714403B2 (en) Semiconductor device package with patterned conductive layers and an interconnecting structure
TWI760701B (zh) 半導體裝置及製造其之方法
TW202008545A (zh) 半導體裝置及其製造方法
CN110739222A (zh) 电子装置和半导体封装结构的制造方法
WO2015123952A1 (zh) 半导体封装结构及其形成方法
US20170194239A1 (en) A semiconductor package having an etched groove for an embedded device formed on bottom surface of a support substrate and a method for fabricating the same
TW202407917A (zh) 半導體封裝以及製造其之方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees