TWI481192B - 耐過壓之通過閘 - Google Patents
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- H—ELECTRICITY
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- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
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- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
- H03K17/6874—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor in a symmetrical configuration
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- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
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- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/0814—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
- H03K17/08142—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/30—Modifications for providing a predetermined threshold before switching
- H03K17/302—Modifications for providing a predetermined threshold before switching in field-effect transistor switches
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- H—ELECTRICITY
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- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0018—Special modifications or use of the back gate voltage of a FET
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Description
本發明係有關於MOSFET裝置且特別是有關於做為低導通阻抗開關(low on-impedance switches)之MOSFET裝置。
MOSFET開關發現於許多應用中,且在高頻傳輸閘開關應用中已為常見。當技術進步時,此等電晶體開關變得更小、更快且功率效率更高。這些低導通阻抗開關常常用在使用不同電源之系統間傳送邏輯資料,例如,一5V系統傳送及/或從一3V系統接收邏輯信號。通常,該等電源決定高邏輯位準。此等開關可以彼此耦接由5V、3.3V及/或1.8V來供電之邏輯系統。
然而,較低電源位準之操作遭遇有關MOSFET電晶體中所固有之臨界需求的問題。例如,在具有不同電源之系統中,在一從一系統所傳送之邏輯信號高於該接收系統之電源的情況下將會遭遇困難。而過/欠壓效應會造成為人所知的嚴重MOSFET故障。
為了保護傳輸閘開關電晶體不受過/欠壓效應之影響的已知方法要付出高的代價。例如,使用兩個串接FET將增加通道電阻,或者如果使該等FET較大以減少通道電阻,則使用增加之晶片面積。如同在上述參考專利申請案中,其他方法未必能在電源開啟及/或電源關閉期間提供完全過/欠壓保護。
在發明名稱"耐過壓/欠壓傳輸閘"之美國專利第6,163,199('199)號中討論關於過/欠壓保護之另一方法。共同擁有該'199專利與本申情案,藉此在此以提及方式併入該專利。該'199專利更詳細論述習知技藝之限制,其是進一步利用平行配置之電晶體,藉由驅動所包含之傳輸電晶體的後閘極(主體接點),來達成過/欠壓保護。
其他已知設計著重在藉由最小化MOSFET結構中所固有之"基體效應(body effect)"以降低插入損失(insertion loss)及增加頻寬。相較於完美開關之情況,通常可將插入損失描述成為因非完美開關之加入而造成傳送至負載之信號功率損失。
Burghartz之美國專利第5,818,099('099)號中發現一著重在基體效應及插入損失之減少的代表性習知技藝設計。該'099專利描述一具有一p井區之-型MOSFET結構,其中如該'099專利之第6A圖所示使用n型井區使該p井區與該p型基板隔離。然而,當出現一信號電壓及關閉該傳輸開關之供應電壓時(例如,當在關閉該傳送或接收系統之電源前先對該傳輸開關關閉電源時),該'099低插入損失電路實施例可能具有較大漏電流。此外,當該開關應該在電源關閉期間關閉時,該開關可能變成打開。
例如,在該'099之第1圖中,繪示一具有典型偏壓+v井區的p型MOSFET。其確保該汲極/源極至井區pn接面二極體沒有變成順向偏壓。然而,如果該+V供應處於接地(藉由關閉該供應),同時在A端上具有高邏輯位準(例如,
+5V),則MOSFET開關中之pn汲極-井區二極體將會形成順向偏壓,而造成潛在傷害之電流路徑。而此電流路徑會對輸出電容器以+V電壓充電。因而,p型MOSFET之井區將被充電,並且,當不應該供電該開關時,卻供應該開關。
至Vdd電源軌之井區電流可以稱為井區漏電流(well leakage)且在某些習知技藝中係繼續存在之問題。存在有一種偏壓狀況,其中在該汲極、源極及Vdd間之電位差對於已知電路而言可能太小而無法正確地決定。本發明提出此習知技藝限制及其它限制。
在習知技藝MOSFET傳輸閘開關中,維持對在正常操作期間及/或在電源開啟及電源關閉操作期間所可能遭遇之所有電源(Vdd)值之耐過壓及保護提供之限制。習知技藝電路在電源開啟期間具有缺陷,其中例如,一關閉狀態之傳輸閘在此等操作期間可能沒有維持關閉及過量漏電流可能發生。
本發明尤其針對這些限制來作改善。
本發明提出該習知技藝之限制及問題,其提供一單主開關FET或像某些應用中之並列主開關FET的一傳輸閘。該等主開關FET例如將是第1圖之M1及M2。在此描述該並列開關配置,然而,熟習該項技藝者將瞭解使用一單主開關FET之本發明。
本發明提供要被驅動之該等主開關FET的井區或複數
個井區,以致於該固有pn接面及該等寄生電晶體不因在傳輸閘操作中所可能發現之各種電源電壓及信號位準電壓而變成順向偏壓。亦即,一經由+5V所供電之電子裝置傳送至另一+5V邏輯系統之+1.8伏信號將不受損害於高漏電流、崩潰或其他故障。
對於一主開關PMOSFET而言,該井區功能上耦接至局部電源或較高輸入信號電壓之較高者,無論哪個都是較高的;以及對於一NMOS而言,耦接至地(ground)或輸入信號電壓之較低者。
在此,"功能上連接"被界定為直接連接或具有不幹擾該等操作之介入零件。
本發明亦提供一種橫跨pn-接面之低順向電壓降二極體(最好,如肖特基二極體),其中該二極體低順向電壓降防止該傳輸電晶體中之pn接面導通。在一實施例中,將該肖特基二極體放置在+Vdd(二極體陽極)與該開關電晶體之井區(二極體陰極)間。例如,一主開關PMOS之汲極或源極至該具有+Vdd之井區的pn接面將受限於該順向二極體電壓降。該二極體電壓降足夠低,以致於不導通該pn接面。
本發明提供一種適當機制,其用以減少該等主開關之井區及閘極的漏電流及確保在一傳輸閘所遭遇之各種信號及電源位準下該等開關之適當實施例。在這方面上,用於該傳輸閘之打開及關閉的電路(致能電路)之電源具有一在一具體例中相同於一PMOS主開關電晶體之井區所連接之電路。縱使該用以驅動該致能電路之個別電路相同於該
PMOS主開關之井區所連接之電路,它具有減少任何閘極漏電流之有利效果而沒有負面地影響較大井區漏電流之減少。
該功能上供電該致能電路之電路亦具有如上所述之肖特基二極體。在此,供電該致能電路之電壓位準係該等輸入信號位準中之較高輸入信號位準+Vdd,然而那個電壓位準最少限度是一低於+Vdd之肖特基二極體電壓降。益處在於該等傳輸開關之關閉狀態將保持開關,而無關於該等信號位準及+Vdd電源及在電源關閉期間。
熟習該項技藝者將察覺到雖然將參考說明具體例、圖式及所使用之方法來進行下面詳述敘述,但是本發明並非意欲侷限於這些具體例及所使用之方法。更確切地說,本發明具有廣泛之範圍及意欲只被界定為所附請求項所述者。
下麵本發明的敘述參考該等所附圖式。
第1圖具有並接之一PMOS M1及一NMOS M2,其連結點A至點B。這兩個MOS電晶體係該等主並列電晶體開關,該等主並列電晶體開關包括一傳輸閘。每一該等電晶體開關之基板接點SUB功能上連接至地(ground)。PMOS M1之WELL連結至CKT A,它的閘極G連結至一致能信號en-,它的汲極連結至外部接點A及它的源極連結至外部接點B。在正常操作中,該傳輸閘從A傳送信號至B,反之亦然。
該並列NMOS M2之汲極功能上連接至外部接點A,以及它的源極連接至外部接點B。如熟習該項技藝者所知,常常可以互換這些電晶體之汲極及源極而沒有任何影響。M2之閘極G連接至一正真實致能信號en+,以及如下面所述連接至M2及M3之源極。PW(P井區)連接至一正真實致能信號en1+,以及M2之NW(N井區)連接至+Vdd。
對稱NMOS電晶體M3及M4提供一從點A至M2之PW連接及然後至點B之信號路徑。如此對於增加頻寬及降低插入損失有好的效果。當M2導通時,一在點A上之AC信號出現在點B上或在M2之源極及汲極兩者上。即使在M1跨有最小電壓降,部分AC信號將經由電容器從該源極及汲極兩者傳送至M2之井區Csw及Cdw。然而,在本發明中,當M3及M4導通時,它們的低電阻將會使跨在Csw及Cdw兩者之AC電壓維持具體不變,因此限制經由這些電容器因頻率所造成的AC信號損失。如此一來,減少因頻率所造成之插入損失及增加該開關之頻寬。M3及M4具有相同尺寸,其均等地分配從A至B之任何電壓降。而如此的對稱性提昇具有M2電路的操作。
第2圖繪示由電路10產生之致能信號。在本發明之一實施例中以CKT A'(CKT A之複製)(見第4圖)取代用於該致能電路之一般電源+Vdd。在第2圖中,M5與M6構成一典型反向器,M7與M8及M9與M10亦是如此。該反向器M9及M10輸出用以驅動M1閘極的en-。該反向器M11及M12輸出用以驅動M2、M3及M4閘極的en+。電阻器R1使M1
之導通信號變慢及電阻器R2使M2之導通變慢。越慢的信號會使該傳輸閘開關之導通更為容易。而M13輸出用以驅動NMOS M2之PW的en1+。
點12通常連接至+Vdd,然而,在此實施例中,點12連接至如下所述之CKT A'。如下所述之與該CKT A結合之CKT A'的連接減少來自M1之閘極(CKT A')與來自M1之WELL(CKT A)的總漏電流。
第3A及3B分別描述PMOS M1及隔離NMOS M2之剖面圖。pn接面表示二極體及寄生電晶體,它們在電源電位、輸入/輸出信號電位及在所包含之電路的電源開啟及電源關閉期間之電源與信號之順序的各種情況下可能影響該等開關之操作。例如,第3A圖之PMOS M1構成一從p型汲極或源極至n型型井區至p型基板(SUB)之寄生pnp電晶體。此外,當順向偏壓時或如果順向偏壓時,任何pn接面構成可能產生問題之寄生二極體。在該NMOS具有相似二極體及電晶體,然而具有一額外層(NI)(N隔離),就會需要對付更多的寄生現象。如以上所述,目的係要在電源開啟/關閉順序期間維持隔離,同時去除返回電源之漏電流。
第4圖係CKT A及A'之概要圖。所有電晶體係PMOS及所有它們的基板連線(未繪示)連結至地(ground)。
最初論述係有關於包括M14與M15(交互耦接電晶體)及M18之電路,其中M18經由假電源軌(prail)14驅動該PMOS M1之WELL。此電路描述用以對該PMOS M1提供過壓保護之電路。當該en係假(false)的時候,在M1之閘極
上的信號en-係高位準且M1係關閉的(該傳輸閘或開關係關閉的)。在A與B間具有一高阻抗連接(因為M2亦是關閉的)。如果A係低位準的,則M18係導通的,以及如果B係低位準的,則+Vdd出現在該假電源軌14上。如果B係高位準的及+Vdd係低位準,則B將出現在該假電源軌14上。將+Vdd或B之較高者饋送至該假電源軌14。同樣地,當B係低位準的時候,M16與M17(交互耦接電晶體)及M19將驅動該假電源軌14至+Vdd或A之較高者,無論哪個係較高位準的。如果+Vdd、A及B全部是低位元準的時候及該電路係有利的---沒有事情發生。
在習知技藝電路中,該WELL常常連接至+Vdd,以及如果+Vdd係低位準的,則該源極或汲極至M1之WELL的pn接面可能變成順向偏壓。該電路CKT A可防止上述發生。
當經由en-使M1偏壓成導通(及經由en+使M2處於導通)時,CKT A將防止至該+Vdd之漏電流。在此情況中,如果+Vdd變成低位準,同時A及B係高位準,則CKT A使M1之WELL與+Vdd斷開,因而防止漏電流。如果+Vdd、A及B全部是低位元準的(如果該傳輸閘係導通的,A及B必定是相等的),則該pn接面仍然不是順向偏壓且沒有漏電流。此外,在臨界內,如果A或B或+Vdd變成低於接地位準,則CKT A使該WELL維持在A、B或+Vdd之較高者。
第5圖係漏電流相對於DC電壓(過電壓)之代表曲線圖,其可能在+Vdd為3.6V時發生於某些習知技藝電路中。
該曲線圖表示可能漏電流路徑之組合。漏電流可能流經許多路徑,其發生可能從開關電晶體M1至地、至+Vdd、至A、至B或在點A與B間。例如,第4圖之電路的檢查描述:當+Vdd、B及A之DC位準比該等PMOS電晶體M14、M15、M16、M17、M18及M19之臨界要靠近彼此時,該假電源軌14(及12)可能有效地浮接。在此情況中,M1之WELL的電壓可能開始下降及導通該寄生pnp電晶體,其中該寄生pnp電晶體係由M1之汲極或源極至M1之基板所構成。事實上,當+Vdd為3.6V時,此可能常常發生之電壓為約+5V。此由在第5圖中之約+4.5V處的上升電流來表示。
提供該肖特基二極體D1,以減少因此下降所造成之習知技藝漏電流及藉此防止該寄生pnp之導通。
肖特基二極體係是一種具有小順向電壓降之半導體/金屬結構。在此應用中,D1係配置成用以防止該汲極或源極至WELL之pn接面,以及防止M1之寄生pnp電晶體導通。如熟習該項技藝者所知,數個較小肖特基二極體可用以取代D1。此等二極體可彼此並接,以進一步最少順向電壓降。
再次參考第1圖及第2圖,該致能電路10從CKT A'取得電源,其中該CKT A'係一相同於上面所述之CKT A的電路。在該實例中,M5、M7及M9之源極電壓將為如上所述之+Vdd、B或A之較高者。如果這些信號係低位準的,則M10、M11、M1及M2皆不導通而無關於該輸入en信號。如果這些信號中之任何一信號係高位準的,則該適當致
能信號將到達M1及M2之閘極。如上所述,如果這三個信號之大小彼此接近,則CKT A'之PMOS電路可能沒有作用。一如既往,在CKT A'中所發現之肖特基二極體D1將(在該順向肖特基二極體電壓降內)點12維持接近+Vdd之電位。
關於CKT A及CKT A',在此所示之電晶體實施可以以該技藝中所已知之其他電路來取代,其中該等其他電路將實施選擇A、B或+Vdd之較高者及將它呈現至點12及14的相同邏輯功能。
第6圖以方塊形式描述上述PMOS CKT A在M1上操作。如熟習該項技藝者所知,可以具有一對應電路,CKT B在M2上操作,如同CKT A在M1上操作。此外,包括M3及M4之CKT C'在M2上操作以增加頻寬,其可以具有一有相似於M3及M4所放置之電晶體的對應電路CKT C,以增加M1之頻寬。
在每一情況中,不使M1之WELL偏壓低於它的汲極/源極,以及因而,不使M1之汲極/源極至井區的pn接面順向偏壓。
應該瞭解到在此呈現上述實施例做為範例及允許它們的變更及替代。於是,將本發明廣泛地只界定為如以下所附請求項所述者。
10‧‧‧致能電路
12‧‧‧點
14‧‧‧假電源軌
+Vdd‧‧‧一般電源
A‧‧‧外部接點
B‧‧‧外部接點
D1‧‧‧肖特基二極體
en+‧‧‧正真實致能信號
en1+‧‧‧正真實致能信號
en-‧‧‧致能信號
G‧‧‧閘極
M1‧‧‧PMOS電晶體
M2‧‧‧NMOS電晶體
M5‧‧‧PMOS電晶體
M6‧‧‧NMOS電晶體
M7‧‧‧PMOS電晶體
M8‧‧‧NMOS電晶體
M9‧‧‧PMOS電晶體
M10‧‧‧NMOS電晶體
M11‧‧‧PMOS電晶體
M12‧‧‧NMOS電晶體
M13‧‧‧NMOS電晶體
M14‧‧‧PMOS電晶體
M15‧‧‧PMOS電晶體
M16‧‧‧PMOS電晶體
M17‧‧‧PMOS電晶體
M18‧‧‧PMOS電晶體
M19‧‧‧PMOS電晶體
R1‧‧‧電阻器
R2‧‧‧電阻器
SUB‧‧‧基板接點
第1圖係描述本發明之方塊簡圖;第2圖係一致能電路之簡圖;
第3A及3B係主電晶體之PMOS及NMOS範例的剖面圖;第4圖係用以供電該PMOS主電晶體之電路及用以供電該致能電路之雙工電路(duplicate circuit)之概要圖;第5圖係描述在習知技藝傳輸閘中所發現之過量漏電流的曲線圖;以及第6圖係描述本發明之關於一PMOS開關及一並列NMOS開關的使用之方塊圖。
10‧‧‧致能電路
12‧‧‧點
14‧‧‧假電源軌
+Vdd‧‧‧一般電源
A‧‧‧外部接點
B‧‧‧外部接點
en+‧‧‧正真實致能信號
en1+‧‧‧正真實致能信號
en-‧‧‧致能信號
G‧‧‧閘極
M1‧‧‧PMOS電晶體
M2‧‧‧NMOS電晶體
SUB‧‧‧基板接點
Claims (18)
- 一種具有低漏電之傳輸閘,包括:一場效第一傳輸電晶體,至少具有閘極、源極、汲極、井區及基板,其中分別在該汲極或源極上接收一輸入信號及在該源極或汲極上呈現一輸出信號;以及第二及第三電晶體,具有它們的個別汲極,其功能上連接至該第一傳輸電晶體之井區,該第二電晶體之閘極功能上連接至該第一電晶體之源極,以及該第三電晶體之閘極功能上連接至該第一傳輸電晶體之汲極;該第二電晶體之源極功能上連接至多個第一交互耦接電晶體,該等第一交互耦接電晶體配置成用以呈現一電源電壓或在該第一傳輸電晶體之汲極上的該信號電壓之較高者至該第二電晶體之源極;以及該第三電晶體之源極功能上連接至多個第二交互耦接電晶體,該等第二交互耦接電晶體配置成用以呈現正電位或在該第一傳輸電晶體之源極上的該信號電壓之較高者至該第三電晶體之源極。
- 如申請專利範圍第1項之傳輸閘,進一步包括一二極體,該二極體具有它的陽極連接至該電源之正電位及它的陰極連接至該第一傳輸電晶體之井區,其中該二極體之順向電壓降足夠低,以防止該第一傳輸電晶體之汲極或源極至井區之pn接面導通。
- 如申請專利範圍第2項之傳輸閘,其中該二極體係一肖特基二極體。
- 如申請專利範圍第2項之傳輸閘,其中該二極體包括兩個或更多並聯肖特基二極體。
- 如申請專利範圍第1項之傳輸閘,進一步包括一致能電路,界定一用以提供電源至該致能電路之電源接點、一致能輸入及一致能輸出,該致能輸出功能上連接至該第一傳輸電晶體之閘極。
- 如申請專利範圍第5項之傳輸閘,進一步包括一第二偏壓電路,界定一功能上連接至該致能電路之電源接點的輸出,該第二偏壓電路界定一功能上連接至該輸入信號之第四接點、一功能上連接至該輸出之第五接點及一功能上連接至一電源之正電位之第六接點,其中將最高電壓呈現至該致能電路之電源接點。
- 如申請專利範圍第6項之傳輸閘,進一步包括一二極體,其陽極連接至該電源之正電位且其陰極連接至該電源接點,以便提供電源至該致能電路。
- 如申請專利範圍第7項之傳輸閘,其中該二極體包括肖特基二極體。
- 如申請專利範圍第8項之傳輸閘,其中該二極體包括兩個或更多並聯肖特基二極體。
- 一種用以連接一輸入至一輸出及使該輸入與該輸出斷開之低漏電方法,該方法包括下列步驟:導通一場效第一傳輸電晶體,該場效第一傳輸電晶體至少具有閘極、源極、汲極、井區及基板,其中分別在該汲極或源極上接收一輸入信號及在該源極或汲極上呈 現一輸出信號;以及功能上連接第二及第三電晶體之汲極至該第一傳輸電晶體之井區;功能上連接該第二電晶體之閘極至該第一電晶體之源極及該第三電晶體之閘極至該第一傳輸電晶體之汲極;功能上連接該第二電晶體之源極至第一交互耦接電晶體,該等第一交互耦接電晶體配置成用以呈現一電源電壓或在該第一傳輸電晶體之汲極上的該信號電壓之較高者至該第二電晶體之源極;以及功能上連接該第三電晶體之源極至第二交互耦接電晶體,該等第二交互耦接電晶體配置成用以呈現該電源電壓之正電位之最高電壓或在該第一傳輸電晶體之源極上的該信號電壓之較高者至該第三電晶體之源極。
- 如申請專利範圍第10項之方法,進一步包括下列步驟:功能上連接一第一二極體陽極至該電源電壓及它的陰極至該第一傳輸電晶體之井區,其中該二極體之順向電壓降足夠低,以防止該第一傳輸電晶體之汲極或源極至井區的pn接面導通。
- 如申請專利範圍第11項之方法,進一步包括下列步驟:功能上將一個或多個二極體與該第一二極體並聯連接。
- 如申請專利範圍第10項之方法,進一步包括下列步驟:從一致能電路產生一致能信號及連接該致能信號至該第一傳輸電晶體之閘極。
- 如申請專利範圍第13項之方法,其中該產生一致能信號 之步驟包括下列步驟:由在該輸入信號、該輸出信號及一電源之一正電位中所選出之最高電壓供電該致能電路。
- 如申請專利範圍第14項之方法,其中該供電該致能電路之步驟包括下列步驟:功能上連接一第二偏壓電路,該第二偏壓電路界定一用以供電該致能電路之輸出;功能上連接該輸入信號、該輸出及一電源至該第二偏壓電路;以及選擇在該輸入信號、該輸出信號及該電源之該正電位中所選出之較高電壓,以供電該致能電路。
- 如申請專利範圍第15項之方法,進一步包括下列步驟:連接一二極體之陽極至該電源電壓及它的陰極至該致能電路,以便提供電源至該致能電路。
- 如申請專利範圍第16項之方法,其中該二極體包括一肖特基二極體。
- 如申請專利範圍第16項之方法,進一步包括下列步驟:功能上將一個或多個二極體與該第一二極體並聯連接。
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- 2008-03-13 WO PCT/US2008/003333 patent/WO2008118291A1/en active Application Filing
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Also Published As
Publication number | Publication date |
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US7514983B2 (en) | 2009-04-07 |
CN101682322A (zh) | 2010-03-24 |
WO2008118291A1 (en) | 2008-10-02 |
US20080231341A1 (en) | 2008-09-25 |
TW200917654A (en) | 2009-04-16 |
KR101492526B1 (ko) | 2015-02-11 |
CN101682322B (zh) | 2012-10-17 |
KR20100015887A (ko) | 2010-02-12 |
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