TWI479643B - 矽基底上所形成之互補金氧半導體（ｃｍｏｓ）及iii-v族裝置之電接點 - Google Patents

矽基底上所形成之互補金氧半導體（ｃｍｏｓ）及iii-v族裝置之電接點 Download PDF

Info

Publication number
TWI479643B
TWI479643B TW099101218A TW99101218A TWI479643B TW I479643 B TWI479643 B TW I479643B TW 099101218 A TW099101218 A TW 099101218A TW 99101218 A TW99101218 A TW 99101218A TW I479643 B TWI479643 B TW I479643B
Authority
TW
Taiwan
Prior art keywords
layer
iii
electrical contacts
transistor
germanium
Prior art date
Application number
TW099101218A
Other languages
English (en)
Other versions
TW201044554A (en
Inventor
Kamal Tabatabaie
Michael S Davis
Jeffrey R Laroche
Valery S Kaper
John P Bettencourt
Original Assignee
Raytheon Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Raytheon Co filed Critical Raytheon Co
Publication of TW201044554A publication Critical patent/TW201044554A/zh
Application granted granted Critical
Publication of TWI479643B publication Critical patent/TWI479643B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

矽基底上所形成之互補金氧半導體(CMOS)及III-V族裝置之電接點 [相關申請案之交互引用]
此申請案有關於與此專利申請案同天申請的共同申請之專利申請案美國專利申請案第(專利代理人卷號RTN2-214PUS)，其全部標的以引用方式包含於此。
本發明主要有關於電接點，尤其關於形成在矽基底上之CMOS裝置及III-V族裝置的電接點。
如在此技藝中已知，CMOS VLSI整合能力超過一億電晶體的程度。亦如在此技藝中已知，一些應用要求類比、RF或光電裝置亦形成在與CMOS裝置相同的基底上。這些類比、RF或光電裝置典型為III-V族裝置。說明整合CMOS裝置及III-V族裝置之一種技術使用Ge晶種層，如於2008年6月26日公開之美國專利申請公開案第2008/0149915 A1號中所述，亦參見美國專利案第7,374,106、7,286,726、7,057,256、6,930,82、5,767,539、6,154,475、7,321,713、及7,057,256號。亦參見，由Dohrman等人發表在Materials Science and Engineering B 135(2006)第235-237頁中之“Fabrication of silicon on lattice-engineered substrate(SOLES) as a platform for monolithic integration of CMOS and optoelectronic devices”。亦參見由Herrick等人發表於Material Research Society Symposium Proceedings,第1068冊，Materials Research Society(1068-C02-10)中之“Direct Growth of III-V Devices on Silicon”。
亦如在此技藝中已知，高溫程序技術用來形成小幾何的TaN或TiN上Cu之電接點到CMOS裝置；另一方面，III-V族電接點典型為TiPtAu或TiAu且使用剝離技術加以製造。
本發明人已認知TiPtAu或TiAu剝離技術的使用會限制電路密度且亦與已根深蒂固之基於Si CMOS VLSI銅互連程序不相容。本發明解決在第一層級金屬互連步驟異質整合的III-V族裝置與基於Si CMOS VLSI銅互連程序之間的互連問題。本發明描述一種異質整合的III-V族裝置與Si CMOS的金屬化方法，其與CMOS VLSI金屬互連程序完全相容。
根據本發明，設置一半導體結構，其具有：基底；在該基底上之晶種層；配置在該晶種層上之矽層；在該矽層中之電晶體裝置；配置在該晶種層中之III-V族裝置；以及複數電接點，該等電接點之每一個具有一TiN或TaN層及在該TaN或TiN層上之金屬層，該等電接點之一電連接至該Si CMOS電晶體且該等電接點之另一電連接至該III-V族裝置。
在一實施例中，該金屬為銅或鋁。
藉由此種佈置，解決在第一層級金屬互連步驟異質整合的III-V族裝置與基於Si CMOS VLSI銅或鋁互連程序之間的互連問題。此佈置與CMOS VLSI金屬互連程序完全相容。此佈置使用現有的先進薄膜技術，如原子層沈積(ALD)方法來提供完全CMOS VLSI程序相容的金屬互連方法，其藉由使用ALD沈積的TiN及/或TaN來接觸III-V族FET之源極、汲極、及閘極或III-V族HBT之射極、基極、及集極，以防止在這些接點及基於銅或鋁的Si CMOS VLSI互連之間的相互擴散。此外，此佈置提供對在Si基底上之異質整合的III-V族裝置中的基於III-V族裝置的端子之基於銅或鋁的低電阻及電感存取。如前述，此佈置與Si CMOS VLSI金屬互連程序完全相容。
在附圖及下列說明中提出本發明之一或更多實施例的細節。本發明之其他特徵、目的及優點將從說明及圖示及從申請專利範圍變得更清楚。
茲參照第1圖，顯示半導體結構10，其具有形成在矽半導體12之一部分上的CMOS場效電晶體(FET) 14及形成在矽基底上之橫向間隔的部份上的III-V族FET 15。矽半導體12在此為具有取決於應用之高或低電阻率的大塊矽。
配置在矽基底12上為二氧化矽絕緣層16及於二氧化矽絕緣層16上之如Ge的晶種層18。一二氧化矽絕緣層20配置在其上有CMOS電晶體14之矽基底12的部份上。如所示，在二氧化矽絕緣層20上有一矽層22。如所示，CMOS電晶體14形成在矽層22上。NMOS電晶體與PMOS電晶體藉由介電質(在此二氧化矽)區域24電絕緣。
晶種層18上形成有GaAs的高電阻率/半絕緣緩衝層19。如GaAs之III-V族材料層21係形成在緩衝層19上。
如所示，有至CMOS電晶體14之源極與汲極區域的鎢(W)接點26。CMOS電晶體14之閘極電極由參考符號27表示。如所示，鎢接點26藉由二氧化矽層28互相電絕緣。有至III-V族FET 15之源極與汲極區域之Ge/W、Ni/Ge/W、Pd/Ge/Al、Pd/Ge/W接點30。
TiN及/或TaN之原子層沈積(ALD)層32係沈積在鎢接點26上及Ge/W或Ni/Ge/W接點30上。TiN及/或TaN層32與III-V族FET 15之閘極區域肖特基接觸。有導電體34(在此電鍍銅)形成在層32上。注意到由介電質層36、37、38、及40電絕緣層32及34。在此層36、37、38、及40為：二氧化矽(層36)、PECVD SiN(層37)、低K的SiOC(碳氧化矽，亦即摻雜C之二氧化矽層並用於Si CMOS VLSI的製造中)間層(層38)、及PECVD的SiN層(層4())。在此層32為TiN或TaN。
詳言之，在層28上及鎢(W)接點26上之層36為二氧化矽。層37在層36上，層37為薄PECVD的SiN層。層38在層37上，層38為低介電質常數(低k ILD，在此碳氧化矽，亦即摻雜C之二氧化矽層並用於Si CMOS VLSI的製造中)。層40在層38上，層40為銅CMP之PECVD硬遮罩。
茲參照第2A至2G圖，其顯示形成結構10之程序。因此，參照第2A圖，在形成結構(其具有在矽基底12上之二氧化矽絕緣層16、在二氧化矽絕緣層16上之晶種層18、在晶種層18上之二氧化矽絕緣層20、在二氧化矽絕緣層20上之矽層22、形成在矽層22上之CMOS電晶體14、形成至CMOS電晶體14的源極與汲極區域及介電質層36的鎢(W)接點26)之後，蝕刻一III-V族裝置島區域50直至晶種層18的上表面。
茲參照第2B圖，將高電阻率/半絕緣緩衝層19(在此例如GaAs的III-V族材料)形成在晶種層18的上表面上。使用例如熟悉III-V族材料生長技藝者已知之分子束磊晶(MBE)或金屬有機CVD(MOCVD)生長技術將例如InP或GaAs的主動III-V族層21形成在緩衝層19上。
茲參照第2C圖，將源極與汲極接點30(在此Ge/W或Ni/Ge/W)形成在主動層21之源極與汲極區域上，之後取決於III-V族裝置結構在410至450℃的溫度熔合。如所述，在此將閘極凹部23形成在主動層21的上表面上。
茲參照第2D圖，如所示，將薄PECVD SiN層37形成於第2C圖中所示之結構的上表面上方。
茲參照第2E圖，將低介電質(低K)間層38形成在薄PECVD SiN層37上，接著沈積銅CMP用之PECVD SiN硬遮罩層40於低介電質(低K)間層38上。
茲參照第2F圖，形成貫穿介電質之接觸洞52以到達NMOS及PMOS FET 14之鎢拴26，且形成貫穿介電質之接觸洞53以到達III-V族FET裝置15之源極與汲極接點30及III-V族FET裝置15用之閘極區域23。在此，在閘極23之主動層21的部份上有一額外非關鍵濕蝕刻以形成雙凹部閘極區域。
茲參照第2G圖，將原子層沈積層32 Ni/TiN或Ni/TaN(注意到若III-V族裝置為基於GaAs或InP，原子層沈積薄膜可為TiN或TaN，而若III-V族裝置為基於GaN，原子層沈積薄膜可為Ni/TiN或Ni/TaN)沈積在第2F圖中所示之結構的表面上方。
將銅層34電鍍在層32之表面上並接著予以化學機械研磨(CMP)而得到第1圖中所示之結構。
茲參照第3A至3H圖，其顯示形成具有CMOS電晶體及III-V族異質接面雙極電晶體(HBT)的結構之程序。在此同樣地程序以具有在矽基底12上之二氧化矽絕緣層16、在二氧化矽絕緣層16上之晶種層18、在晶種層18上之二氧化矽絕緣層20、在二氧化矽絕緣層20上之矽層22、形成在矽層22上之CMOS電晶體14、形成至CMOS電晶體14的源極與汲極區域及介電質層36的鎢(W)接點26的結構開始，蝕刻一III-V族裝置島區域50直至晶種層18的上表面。
茲參照第3B圖，將高電阻率/半絕緣緩衝層19形成在晶種層18的上表面上。將例如InP或GaAs的主動III-V族層21’形成在緩衝層19上。在此，如所示，有在頂部有非常高摻雜之較低子集極層21a，且其上有III-V族集極層21b，且其上有III-V族基極層21c，且其上有III-V族射極層21d。
茲參照第3C圖，沿著基極-集極凸部67、基極歐姆接點68、射極歐姆接點69、及射極-基極凸部70形成集極歐姆接點66。再次以PECVD SiN層37覆蓋結構作為III-V族HBT 15’的第一被動層，如第3D圖中所示。可經由Pt/W薄層形成集極、基極、及射極歐姆接點。
茲參照第3E圖，接著如連同第2E、2F、及2G圖所述般處理結構，以分別產生如第3E、3F、及3G圖中所示之結構，以產生如第3H圖中所示之結構。因此，茲參照第3E圖，將低介電質(低K)間層38形成在薄PECVD SiN層37上，接著沈積銅CMP用之PECVD SiN硬遮罩層40於低介電質(低K)間層38上。
茲參照第3F圖，形成貫穿介電質之接觸洞52以到達NMOS及PMOS FET 14之鎢拴26，且形成貫穿介電質之接觸洞53a、53b、及53c以到達III-V族HBT裝置15’之集極、基極、及射極接點66、68、及69。
茲參照第3G圖，將原子層沈積層32 Ni/TiN或Ni/TaN沈積在第3F圖中所示之結構的表面上方。將銅層34電鍍在層32之表面上並接著予以化學機械研磨(CMP)而得到第3H圖中所示之結構。
已經說明本發明的多個實施例。然而，可了解到可做出不背離本發明之精神與範疇之各種修改。例如，取代銅可藉由噴濺沈積及減去圖案化而使用鋁作為層34。依此，其他實施例係在下列申請專利範圍之範疇內。
10．．．半導體結構
12．．．矽半導體
14．．．CMOS場效電晶體(FET)
15．．．III-V族FET
15’．．．III-V族異質接面雙極電晶體
16．．．二氧化矽絕緣層
18．．．晶種層
19．．．緩衝層
20．．．二氧化矽絕緣層
21、21’．．．III-V族材料層
21a．．．較低子集極層
21b．．．III-V族集極層
21c．．．III-V族基極層
21d．．．III-V族射極層
22．．．矽層
23．．．閘極凹部
24．．．介電質區域
26．．．接點
27．．．閘極電極
28．．．二氧化矽層
30．．．接點
32．．．原子層沈積(ALD)層
34．．．導電體
36、37、38、40．．．介電質層
50．．．III-V族裝置島區域
52、53、53a、53b、53d．．．接觸洞
66．．．集極歐姆接點
67．．．基極-集極凸部
68．．．基極歐姆接點
69．．．射極歐姆接點
70．．．射極-基極凸部
第1圖為根據本發明之半導體結構的剖面圖，此結構具有形成在基底上之矽層中之CMOS FET且具有形成在基底上之III-V族FET；
第2A至2G圖為第1圖之半導體結構在其之製造中的各個階段之剖面圖；以及
第3A至3H圖為根據本發明之另一實施例的另一半導體結構在其之製造中的各個階段之剖面圖，此結構具有形成在基底上之矽層中之CMOS FET且具有形成在基底上之III-V族HBT。
各個圖中之類似參考符號表示類似元件。
10．．．半導體結構
12．．．矽半導體
14．．．CMOS場效電晶體(FET)
15．．．III-V族FET
16．．．二氧化矽絕緣層
18．．．晶種層
19．．．緩衝層
20．．．二氧化矽絕緣層
21．．．III-V族材料層
22．．．矽層
24．．．介電質區域
26．．．接點
28．．．二氧化矽層
30．．．接點
32．．．原子層沈積(ALD)層
34．．．導電體
36、38、40．．．介電質層

Claims (20)

  1. 一種半導體結構，包含：基底；在該基底上之晶種層；配置在該晶種層上之矽層；在該矽層中之電晶體裝置；配置在該晶種層上之III-V族層；配置在該III-V族層中之III-V族裝置；以及複數電接點，該等電接點之每一個具有一TiN或TaN層及在該TaN或TiN層上之金屬層，該等電接點之一電連接至該矽層中之該電晶體裝置且該等電接點之另一電連接至該III-V族裝置，該等電接點之該另一具有與該III-V族層接觸之一Ge/W、Ni/Ge/W、Pd/Ge/Al或Pd/Ge/W層，且其中該TaN或TiN層被配置在該Ge/W、Ni/Ge/W、Pd/Ge/Al或Pd/Ge/W層上。
  2. 如申請專利範圍第1項所述之結構，其中該金屬層為鋁。
  3. 如申請專利範圍第1項所述之結構，其中該金屬層為銅。
  4. 如申請專利範圍第1項所述之結構，其中該電晶體裝置為矽場效電晶體。
  5. 如申請專利範圍第1項所述之結構，其中該矽層中具有CMOS FET。
  6. 如申請專利範圍第4項所述之結構，其中該III-V 族裝置為FET。
  7. 如申請專利範圍第5項所述之結構，其中該III-V族裝置為FET。
  8. 如申請專利範圍第4項所述之結構，其中該III-V族裝置為雙極電晶體。
  9. 如申請專利範圍第5項所述之結構，其中該III-V族裝置為雙極電晶體。
  10. 一種半導體結構，包含：基底；配置在該基底上之矽層；在該矽層中之電晶體裝置；配置在該基底上之III-V族裝置；以及複數電接點，該等電接點之每一個具有一TiN或TaN層及在該TaN或TiN層上之金屬層，該等電接點之一電連接至該電晶體裝置且該等電接點之另一電連接至該III-V族裝置，該等電接點之該另一具有與該III-V族層接觸之一Ge/W、Ni/Ge/W、Pd/Ge/Al或Pd/Ge/W層，且其中該TaN或TiN層被配置在該Ge/W、Ni/Ge/W、Pd/Ge/Al或Pd/Ge/W層上。
  11. 如申請專利範圍第10項所述之結構，其中該金屬層為鋁。
  12. 如申請專利範圍第10項所述之結構，其中該金屬層為銅。
  13. 一種半導體結構，包含： 基底；在該基底上之晶種層；配置在該晶種層上之矽層；在該矽層中之電晶體裝置；配置在該晶種層上之III-V族裝置；以及複數電接點，該等電接點之每一個具有一TiN或TaN層及在該TaN或TiN層上之銅或鋁層，該等電接點之一電連接至該電晶體裝置且該等電接點之另一電連接至該III-V族裝置，該等電接點之該另一具有與該III-V族層接觸之一Ge/W、Ni/Ge/W、Pd/Ge/Al或Pd/Ge/W層，且其中該TaN或TiN層被配置在該Ge/W、Ni/Ge/W、Pd/Ge/Al或Pd/Ge/W層上。
  14. 如申請專利範圍第12項所述之結構，其中該電晶體裝置為矽場效電晶體。
  15. 如申請專利範圍第12項所述之結構，其中該矽層中具有CMOS FET。
  16. 如申請專利範圍第13項所述之結構，其中該III-V族裝置為FET。
  17. 如申請專利範圍第14項所述之結構，其中該III-V族裝置為FET。
  18. 如申請專利範圍第13項所述之結構，其中該III-V族裝置為雙極電晶體。
  19. 如申請專利範圍第14項所述之結構，其中該III-V族裝置為雙極電晶體。
  20. 一種半導體結構，包含：基底；配置在該基底上之矽層；在該矽層中之電晶體裝置；配置在該基底上之III-V族層；配置在該III-V族層中之III-V族場效電晶體；以及複數電接點，該等電接點之每一個具有一TiN或TaN層，該TaN或TiN層為：(A)電連接至該矽層中之該電晶體裝置；(B)與III-V族材料肖特基接觸以提供閘極接觸給該III-V族場效電晶體；及(C)配置在一Ge/W、Ni/Ge/W、Pd/Ge/Al或Pd/Ge/W層上，該Ge/W、Ni/Ge/W、Pd/Ge/Al或Pd/Ge/W層與該III-V族場效電晶體之源極和汲極區接觸。
TW099101218A 2009-01-20 2010-01-18 矽基底上所形成之互補金氧半導體（ｃｍｏｓ）及iii-v族裝置之電接點 TWI479643B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/356,254 US7834456B2 (en) 2009-01-20 2009-01-20 Electrical contacts for CMOS devices and III-V devices formed on a silicon substrate

Publications (2)

Publication Number Publication Date
TW201044554A TW201044554A (en) 2010-12-16
TWI479643B true TWI479643B (zh) 2015-04-01

Family

ID=42040535

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099101218A TWI479643B (zh) 2009-01-20 2010-01-18 矽基底上所形成之互補金氧半導體（ｃｍｏｓ）及iii-v族裝置之電接點

Country Status (5)

Country Link
US (1) US7834456B2 (zh)
EP (1) EP2380195B1 (zh)
JP (1) JP5603882B2 (zh)
TW (1) TWI479643B (zh)
WO (1) WO2010085458A1 (zh)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8389348B2 (en) * 2010-09-14 2013-03-05 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanism of forming SiC crystalline on Si substrates to allow integration of GaN and Si electronics
US8847408B2 (en) * 2011-03-02 2014-09-30 International Rectifier Corporation III-nitride transistor stacked with FET in a package
US9847407B2 (en) 2011-11-16 2017-12-19 Skyworks Solutions, Inc. Devices and methods related to a gallium arsenide Schottky diode having low turn-on voltage
US9461153B2 (en) 2011-11-16 2016-10-04 Skyworks Solutions, Inc. Devices and methods related to a barrier for metallization of a gallium based semiconductor
US9287115B2 (en) 2014-03-12 2016-03-15 International Business Machines Corporation Planar III-V field effect transistor (FET) on dielectric layer
US9419580B2 (en) * 2014-10-31 2016-08-16 Raytheon Company Output matching network having a single combined series and shunt capacitor component
KR102402771B1 (ko) 2015-12-11 2022-05-26 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US9704958B1 (en) 2015-12-18 2017-07-11 International Business Machines Corporation III-V field effect transistor on a dielectric layer
KR102532202B1 (ko) 2016-01-22 2023-05-12 삼성전자 주식회사 반도체 소자
US10153300B2 (en) * 2016-02-05 2018-12-11 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device including a high-electron-mobility transistor (HEMT) and method for manufacturing the same
US10062693B2 (en) * 2016-02-24 2018-08-28 International Business Machines Corporation Patterned gate dielectrics for III-V-based CMOS circuits
US10593600B2 (en) 2016-02-24 2020-03-17 International Business Machines Corporation Distinct gate stacks for III-V-based CMOS circuits comprising a channel cap
JP6763703B2 (ja) * 2016-06-17 2020-09-30 ラピスセミコンダクタ株式会社 半導体装置および半導体装置の製造方法
US20180269105A1 (en) * 2017-03-15 2018-09-20 Globalfoundries Singapore Pte. Ltd. Bonding of iii-v-and-si substrates with interconnect metal layers
US10134945B1 (en) * 2017-08-28 2018-11-20 Taiwan Semiconductor Manufacturing Co., Ltd. Wafer to wafer bonding techniques for III-V wafers and CMOS wafers
US10431581B1 (en) * 2018-04-30 2019-10-01 Qualcomm Incorporated Complementary metal-oxide semiconductor (CMOS) integration with compound semiconductor devices
US10546852B2 (en) * 2018-05-03 2020-01-28 Qualcomm Incorporated Integrated semiconductor devices and method of fabricating the same
US11177216B2 (en) 2018-09-06 2021-11-16 Raytheon Company Nitride structures having low capacitance gate contacts integrated with copper damascene structures
US11024728B2 (en) * 2019-02-15 2021-06-01 Qualcomm Incorporated Monolithic self-aligned heterojunction bipolar transistor (HBT) and complementary metal-oxide-semiconductor (CMOS)
US11233159B2 (en) 2020-01-10 2022-01-25 Newport Fab, Llc Fabrication of semiconductor structure having group III-V device on group IV substrate with separately formed contacts using different metal liners
US11581452B2 (en) * 2020-01-10 2023-02-14 Newport Fab, Llc Semiconductor structure having group III-V device on group IV substrate and contacts with precursor stacks
US11545587B2 (en) * 2020-01-10 2023-01-03 Newport Fab, Llc Semiconductor structure having group III-V device on group IV substrate and contacts with liner stacks
US11929442B2 (en) 2020-01-10 2024-03-12 Newport Fab, Llc Structure and method for process control monitoring for group III-V devices integrated with group IV substrate
US11296482B2 (en) 2020-01-10 2022-04-05 Newport Fab, Llc Semiconductor structure having group III-V chiplet on group IV substrate and cavity in proximity to heating element
US11349280B2 (en) 2020-01-10 2022-05-31 Newport Fab, Llc Semiconductor structure having group III-V device on group IV substrate
US11581448B2 (en) 2021-04-01 2023-02-14 Raytheon Company Photoconductive semiconductor switch laterally fabricated alongside GaN on Si field effect transistors
US11710708B2 (en) 2021-08-19 2023-07-25 Raytheon Company On-chip EMF isolation of an integrated circuit coupled with photoconductive semiconductor switch under an on-chip faraday cage
WO2024116732A1 (ja) * 2022-11-30 2024-06-06 株式会社ジャパンディスプレイ 半導体素子

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5286985A (en) * 1988-11-04 1994-02-15 Texas Instruments Incorporated Interface circuit operable to perform level shifting between a first type of device and a second type of device
JP2002184776A (ja) * 2000-12-15 2002-06-28 Sharp Corp 半導体装置及びその製造方法
US20060284247A1 (en) * 2005-06-17 2006-12-21 Godfrey Augustine Novel method for integrating silicon CMOS and AlGaN/GaN wideband amplifiers on engineered substrates

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US693082A (en) 1900-11-10 1902-02-11 Globe Wernicke Co Perforator.
JPS6254459A (ja) * 1985-09-02 1987-03-10 Seiko Epson Corp 相補型電界効果トランジスタ
US4774205A (en) * 1986-06-13 1988-09-27 Massachusetts Institute Of Technology Monolithic integration of silicon and gallium arsenide devices
JPS645035A (en) * 1987-06-29 1989-01-10 Toshiba Corp Semiconductor device and its manufacture
US5308444A (en) * 1993-05-28 1994-05-03 At&T Bell Laboratories Method of making semiconductor heterostructures of gallium arsenide on germanium
US5512518A (en) * 1994-06-06 1996-04-30 Motorola, Inc. Method of manufacture of multilayer dielectric on a III-V substrate
US5514606A (en) * 1994-07-05 1996-05-07 Motorola Method of fabricating high breakdown voltage FETs
US5767539A (en) 1996-04-05 1998-06-16 Nec Corporation Heterojunction field effect transistor having a InAlAs Schottky barrier layer formed upon an n-InP donor layer
EP1036412A1 (en) * 1997-09-16 2000-09-20 Massachusetts Institute Of Technology CO-PLANAR Si AND Ge COMPOSITE SUBSTRATE AND METHOD OF PRODUCING SAME
US6154475A (en) 1997-12-04 2000-11-28 The United States Of America As Represented By The Secretary Of The Air Force Silicon-based strain-symmetrized GE-SI quantum lasers
US6541863B1 (en) * 2000-01-05 2003-04-01 Advanced Micro Devices, Inc. Semiconductor device having a reduced signal processing time and a method of fabricating the same
US6602613B1 (en) * 2000-01-20 2003-08-05 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
JP3616297B2 (ja) * 2000-01-21 2005-02-02 松下電器産業株式会社 半導体装置の製造方法
JP2004507084A (ja) * 2000-08-16 2004-03-04 マサチューセッツ　インスティテュート　オブ　テクノロジー グレーデッドエピタキシャル成長を用いた半導体品の製造プロセス
JP2002111050A (ja) * 2000-09-27 2002-04-12 Kyocera Corp 半導体発光装置及びそれを用いた光プリンタヘッド
US6703688B1 (en) * 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US7374106B1 (en) 2001-05-15 2008-05-20 Nicholas Sheppard Bromer Triggered flickering tag
US7057256B2 (en) 2001-05-25 2006-06-06 President & Fellows Of Harvard College Silicon-based visible and near-infrared optoelectric devices
US7301180B2 (en) * 2001-06-18 2007-11-27 Massachusetts Institute Of Technology Structure and method for a high-speed semiconductor device having a Ge channel layer
US6974735B2 (en) * 2001-08-09 2005-12-13 Amberwave Systems Corporation Dual layer Semiconductor Devices
EP1588406B1 (en) * 2003-01-27 2019-07-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures with structural homogeneity
US7304336B2 (en) * 2003-02-13 2007-12-04 Massachusetts Institute Of Technology FinFET structure and method to make the same
WO2006034271A1 (en) 2004-09-17 2006-03-30 Massachusetts Institute Of Technology Silicon based on-chip photonic band gap cladding waveguide
CN101326646B (zh) * 2005-11-01 2011-03-16 麻省理工学院 单片集成的半导体材料和器件
JP2007214538A (ja) * 2006-01-11 2007-08-23 Renesas Technology Corp 半導体装置およびその製造方法
US7286726B1 (en) 2006-03-31 2007-10-23 Intel Corporation Integrated active electrical waveguide for optical waveguide modulators
US8063397B2 (en) * 2006-06-28 2011-11-22 Massachusetts Institute Of Technology Semiconductor light-emitting structure and graded-composition substrate providing yellow-green light emission
US20080070355A1 (en) * 2006-09-18 2008-03-20 Amberwave Systems Corporation Aspect ratio trapping for mixed signal applications

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5286985A (en) * 1988-11-04 1994-02-15 Texas Instruments Incorporated Interface circuit operable to perform level shifting between a first type of device and a second type of device
JP2002184776A (ja) * 2000-12-15 2002-06-28 Sharp Corp 半導体装置及びその製造方法
US20060284247A1 (en) * 2005-06-17 2006-12-21 Godfrey Augustine Novel method for integrating silicon CMOS and AlGaN/GaN wideband amplifiers on engineered substrates

Also Published As

Publication number Publication date
EP2380195B1 (en) 2018-09-12
JP2012516037A (ja) 2012-07-12
EP2380195A1 (en) 2011-10-26
US7834456B2 (en) 2010-11-16
WO2010085458A1 (en) 2010-07-29
US20100181674A1 (en) 2010-07-22
JP5603882B2 (ja) 2014-10-08
TW201044554A (en) 2010-12-16

Similar Documents

Publication Publication Date Title
TWI479643B (zh) 矽基底上所形成之互補金氧半導體（ｃｍｏｓ）及iii-v族裝置之電接點
US10566430B2 (en) Field effect transistor devices having gate contacts formed in active region overlapping source/drain contacts
CN101996874B (zh) 半导体器件及半导体器件制造方法
US8569803B2 (en) BEOL compatible FET structrure
US8415751B2 (en) Method to reduce contact resistance of N-channel transistors by using a III-V semiconductor interlayer in source and drain
US7994550B2 (en) Semiconductor structures having both elemental and compound semiconductor devices on a common substrate
US10854734B1 (en) Manufacturing method of semiconductor device
US10930510B2 (en) Semiconductor device with improved contact resistance and via connectivity
US20210184005A1 (en) High power device with self-aligned field plate
US11705486B2 (en) Isolation structure for active devices
US7843039B2 (en) Stress-modified device structures, methods of fabricating such stress-modified device structures, and design structures for an integrated circuit
TWI692039B (zh) 半導體裝置的製作方法
US20240087980A1 (en) Etching-damage-free intermetal dielectric layer with thermal dissipation feature
US11784224B2 (en) Lateral bipolar transistor structure with base over semiconductor buffer and related method
US20230187510A1 (en) Angled via for tip to tip margin improvement
US11094900B2 (en) Semiconductor device and method for fabricating the same
US20220108951A1 (en) Substrate with a buried conductor under an active region for enhanced thermal conductivity and rf shielding
US20220406608A1 (en) Semiconductor structure and method for forming the same
US20160322384A1 (en) Semiconductor structure having logic region and analog region
US20180269105A1 (en) Bonding of iii-v-and-si substrates with interconnect metal layers
CN113078098A (zh) 半导体结构及其制造方法
CN112993027A (zh) 半导体结构及其形成方法