TWI471073B - 線路基板及其製作方法 - Google Patents

線路基板及其製作方法 Download PDF

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TWI471073B
TWI471073B TW98146204A TW98146204A TWI471073B TW I471073 B TWI471073 B TW I471073B TW 98146204 A TW98146204 A TW 98146204A TW 98146204 A TW98146204 A TW 98146204A TW I471073 B TWI471073 B TW I471073B
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layer
electroless plating
insulating layer
circuit substrate
dielectric layer
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TW201124026A (en
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Tzyy Jang Tseng
Chang Ming Lee
Wen Fang Liu
Cheng Po Yu
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Unimicron Technology Corp
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Priority to US12/718,226 priority patent/US8247705B2/en
Priority to JP2010100677A priority patent/JP5165723B2/ja
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/38Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/386Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive
    • H05K3/387Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive for electroless plating
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601Process or apparatus
    • C23C18/1633Process of electroless plating
    • C23C18/1646Characteristics of the product obtained
    • C23C18/165Multilayered product
    • C23C18/1653Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0104Properties and characteristics in general
    • H05K2201/0129Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0137Materials
    • H05K2201/0145Polyester, e.g. polyethylene terephthalate [PET], polyethylene naphthalate [PEN]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0137Materials
    • H05K2201/0154Polyimide
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126Assembling bases
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • Y10T29/49156Manufacturing circuit on or in base with selective destruction of conductive paths
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • Y10T29/49165Manufacturing circuit on or in base by forming conductive walled aperture in base
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24273Structurally defined web or sheet [e.g., overall dimension, etc.] including aperture
    • Y10T428/24322Composite web or sheet

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Description

線路基板及其製作方法
本發明是有關於一種線路基板及其製作方法,且特別是有關於一種提高製程能力的高密度線路基板及其製作方法。
目前細線路、高密度的線路基板的製作方法,是使用半加成方法形成所需的線路層,而半加成方法依絕緣材料特性不同主要區分為ABF(Ajinomoto build-up film)膜及非ABF膜的半加成法。
ABF膜表面經粗化後可直接製作導電層,後續再實施半加成的微影、電鍍、去膜以及蝕刻等步驟,以形成微細線路的線路層。但受限於絕緣材料必須為ABF膜,因此成本高。
利用非ABF膜的製作方法是在其表面先壓合一薄銅層,後續再實施半加成的微影、電鍍、去膜以及蝕刻等步驟,以形成微細線路的線路層。但受限於薄銅層不易附著在非ABF膜上,造成利用非ABF膜的製程能力較使用ABF膜的製程能力低。故目前的半加成方法,除了特殊材料的ABF膜可在無底銅的情況下進行電鍍之外,其他的作法仍以底銅加上電鍍銅為主。
本發明提供一種線路基板及其製作方法,以提高製程能力。
本發明提供一種線路基板及其製作方法,不需使用特殊材料的ABF膜,以降低成本。
本發明提供一種線路基板的製作方法,包括下列步驟。首先,形成一介電層於一基板的至少一表面上。形成一絕緣層於介電層上。接著,移除部分絕緣層以及介電層,以形成至少一盲孔於介電層以及絕緣層中。形成一化學鍍層於盲孔的內壁上以及未移除的絕緣層上,其中絕緣層與化學鍍層之間的接合能力大於介電層與化學鍍層之間的接合能力。之後,電鍍一圖案化導電層,以覆蓋化學鍍層。
本發明提供一種線路基板,包括一基板、一介電層、一絕緣層、一化學鍍層以及一圖案化導電層。介電層配置於基板的至少一表面上。絕緣層配置於介電層上。化學鍍層覆蓋部分絕緣層以及至少一盲孔的內壁上,其中盲孔形成於介電層以及絕緣層中,絕緣層與化學鍍層之間的接合能力大於介電層與化學鍍層之間的接合能力。圖案化導電層配置於化學鍍層上及盲孔中。
在本發明之一實施例中,上述介電層為熱硬化性樹脂。
在本發明之一實施例中,上述介電層的材質包括環氧樹脂或玻纖環氧樹脂。
在本發明之一實施例中,上述絕緣層為熱可塑性樹脂。
在本發明之一實施例中,上述絕緣層的材質包括聚碳酸酯、聚酯或聚醯亞胺樹脂。
在本發明之一實施例中,上述形成絕緣層於介電層上之後,更包括對絕緣層進行一表面粗化處理。
在本發明之一實施例中,上述形成絕緣層的方法包括塗佈或噴印。
在本發明之一實施例中,上述形成至少一盲孔的方法包括雷射成孔。
在本發明之一實施例中,上述形成至少一盲孔時,更包括顯露出位於盲孔下方的一電性連接墊,電性連接墊位於基板的表面上。
在本發明之一實施例中,上述電鍍圖案化導電層之前,更包括形成一圖案化光阻層於化學鍍層上。
在本發明之一實施例中,上述電鍍圖案化導電層之後,更包括移除圖案化光阻層以及未被圖案化導電層覆蓋的化學鍍層。
在本發明之一實施例中,上述化學鍍層的材質選自銅、鎳、銀、鉻及錫所組成的群組中其中一種金屬。
在本發明之一實施例中,上述圖案化導電層的材質包括銅。
在本發明之一實施例中,上述基板的表面具有一電性連接墊,而圖案化導電層經由盲孔與電性連接墊電性連接。
基於上述,本發明的線路基板及其製作方法中,先形成一絕緣層於介電層上,且絕緣層與化學鍍層之間的接合能力大於介電層與化學鍍層之間的接合能力,之後再形成化學鍍層於絕緣層上,以提高製程能力。
為讓本發明之上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
圖1A~圖1F為本發明一實施例之線路基板的製作方法的流程圖。圖2為本發明一實施例之線路基板的示意圖。
線路基板的製作方法包括下列步驟。請先參考圖1A,形成一介電層110於一基板100的二表面100a、100b上。基板100例如是由多層圖案化線路層(未繪示)以及多層圖案化介電層(未繪示)相互堆疊而成的電路板,或是由其他絕緣材料所構成的載板,基板100的表面100a、100b上例如具有圖案化線路104或電性連接墊102,其材質可為銅。介電層110可為熱硬化性樹脂,其可經由塗佈半固化態的膠片於基板110的一表面上,並加熱到硬化溫度,以使具有流體的形變特性之半固化態的膠片凝固為不可流動的固化態的膠片。介電層110的材質例如是起始狀態為液態之環氧樹脂或玻纖環氧樹脂或其他起始狀態為液態之不可逆高分子材質。
接著,請參考圖1B及圖1C,形成一絕緣層120於介電層110上,並移除部分絕緣層120以及介電層110,以形成至少一盲孔C於介電層110以及絕緣層120中。絕緣層120為熱可塑性樹脂,其可經由塗佈或噴印的方式形成。因此,絕緣層120被加熱時即軟化成液態樹脂,冷卻時硬化為固化態的樹脂。此外,形成絕緣層120於介電層110上之前,還可對介電層110進行一表面粗化處理,以使固化態的介電層110與絕緣層120之間的結合力增強,避免產生層間的剝離。
上述形成至少一盲孔C的方法例如是雷射成孔,而雷射成孔之後可進行除膠渣的步驟,以清潔盲孔C內殘留的膠材。在本實施例中,雷射光穿透介電層110以及絕緣層120之後,可顯露出位於盲孔C下方的一電性連接墊102。此外,絕緣層120的材質可選用聚碳酸酯、聚酯或聚醯亞胺樹脂,或是其他初始狀態為固態,但受熱可熔化並可於冷卻之後仍可回復至初始狀態的熱塑性高分子材質。另外,形成絕緣層120於介電層110上之後,更可對絕緣層120進行一表面粗化處理,以利後續進行半加成法。
接著,請參考圖1D及圖1E,形成一化學鍍層130於盲孔C的內壁上以及未移除的絕緣層120上,並且電鍍一圖案化導電層140,以覆蓋化學鍍層130。值得注意的是,絕緣層120為熱可塑性樹脂,而介電層110為熱硬化性樹脂,若直接形成化學鍍層130於介電層110上,受限於化學鍍層130附著於熱硬化性樹脂的能力較低,故製程能力無法提高。因此,本發明有鑑於絕緣層120與化學鍍層130之間的接合能力大於介電層110與化學鍍層130之間的接合能力,先形成一絕緣層120於介電層110上,之後再形成化學鍍層130於絕緣層120上,以提高製程能力。在本實施例中,化學鍍層130的材質可選自銅、鎳、銀、鉻及錫所組成的群組中其中一種金屬,本發明對此不加以限制。
此外,在電鍍圖案化導電層140之前,可先形成一圖案化光阻層150於化學鍍層130上,之後再電鍍一導電材料於未被圖案化光阻層150覆蓋的化學鍍層130上(也就是圖案化光阻層150的開口152中),以形成所需的圖案化導電層140。在本實施例中,圖案化導電層140可填滿於盲孔C中,並與盲孔C下方的電性連接墊102電性連接。圖案化導電層的材質例如為銅。
接著,請參考圖1F,電鍍圖案化導電層140之後,更可移除圖案化光阻層150以及未被圖案化導電層140覆蓋的化學鍍層130,以形成具有一線路圖案的線路層。移除化學鍍層130的方法包括蝕刻,而化學鍍層130被蝕刻之後成為具有相同線路圖案的化學鍍層130a。雖然上述的實施例中,繪示在基板100的二表面上形成二介電層110、二絕緣層120以及二化學鍍層130,並進行雙面電鍍,以同時形成所需的二圖案化導電層140,但上述製程可單面或雙面進行,本發明對此不加以限制。
如圖2所示,線路基板10具有一基板100、二介電層110、二絕緣層120、二化學鍍層130a以及一圖案化導電層140。此二介電層110分別配置於基板100的相對二表面100a、100b上。此二絕緣層120分別配置於二介電層110。二化學鍍層130a分別覆蓋部分二絕緣層120以及至少一盲孔C的內壁上,其中盲孔C可形成於一介電層110以及相對應之絕緣層120中,且絕緣層120與化學鍍層130a之間的接合能力大於介電層110與化學鍍層130a之間的接合能力。此二圖案化導電層140分別配置於化學鍍層130a上及盲孔C中,以形成一具有線路圖案的線路層。此外,基板100的一表面100a上例如具有一電性連接墊102,而圖案化導電層140可經由盲孔C與電性連接墊102電性連接。雖然在上述的實施例中,線路基板10具有二介電層110、二絕緣層120以及二化學鍍層130a以及二圖案化導電層140,但上述結構可為單面或雙面,本發明對此不加以限制。
綜上所述,本發明的線路基板及其製作方法中,先形成一絕緣層於介電層上,且絕緣層與化學鍍層之間的接合能力大於介電層與化學鍍層之間的接合能力,之後再形成化學鍍層於絕緣層上,以提高製程能力。因此,本發明不需受限於絕緣材料必須為ABF膜,同樣可於粗化後進行化學電鍍或浸鍍以形成化學鍍層,後續再實施半加成的微影、電鍍、去膜以及蝕刻等步驟,因此成本較低。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10...線路基板
100...基板
100a、100b...表面
102...電性連接墊
104...圖案化線路
110...介電層
120...絕緣層
130...化學鍍層
140...圖案化導電層
150...圖案化光阻層
152...開口
130a...化學鍍層
C...盲孔
圖1A~圖1F為本發明一實施例之線路基板的製作方法的流程圖。
圖2為本發明一實施例之線路基板的示意圖。
100...基板
102...電性連接墊
110...介電層
120...絕緣層
130...化學鍍層
140...圖案化導電層
150...圖案化光阻層
152...開口
C...盲孔

Claims (8)

  1. 一種線路基板的製作方法,包括:形成一介電層於一基板的至少一表面上,其中該介電層為熱硬化性樹脂;形成一絕緣層於該介電層上,其中該絕緣層為熱可塑性樹脂,其中形成該絕緣層於該介電層上之後,更包括對該絕緣層進行一表面粗化處理;移除部分該絕緣層以及該介電層,以形成至少一盲孔於該介電層以及該絕緣層中;形成一化學鍍層於該盲孔的內壁上以及未移除的該絕緣層上,其中該絕緣層與該化學鍍層之間的接合能力大於該介電層與該化學鍍層之間的接合能力;以及電鍍一圖案化導電層,以覆蓋該化學鍍層。
  2. 如申請專利範圍第1項所述之線路基板的製作方法,其中該介電層的材質包括環氧樹脂或玻纖環氧樹脂。
  3. 如申請專利範圍第1項所述之線路基板的製作方法,其中該絕緣層的材質包括聚碳酸酯、聚酯或聚醯亞胺樹脂。
  4. 如申請專利範圍第1項所述之線路基板的製作方法,其中形成該絕緣層的方法包括塗佈或噴印。
  5. 如申請專利範圍第1項所述之線路基板的製作方法,其中形成該至少一盲孔的方法包括雷射成孔。
  6. 如申請專利範圍第1項所述之線路基板的製作方法,其中形成該至少一盲孔時,更包括顯露出位於該盲孔 下方的一電性連接墊,該電性連接墊位於該基板的該表面上。
  7. 如申請專利範圍第1項所述之線路基板的製作方法,其中電鍍該圖案化導電層之前,更包括形成一圖案化光阻層於該化學鍍層上。
  8. 如申請專利範圍第1項所述之線路基板的製作方法,其中電鍍該圖案化導電層之後,更包括移除該圖案化光阻層以及未被該圖案化導電層覆蓋的該化學鍍層。
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