TWI462195B - 半導體晶片封裝總成之方法及用於抵銷引線指變形之裝置 - Google Patents
半導體晶片封裝總成之方法及用於抵銷引線指變形之裝置 Download PDFInfo
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- TWI462195B TWI462195B TW98109958A TW98109958A TWI462195B TW I462195 B TWI462195 B TW I462195B TW 98109958 A TW98109958 A TW 98109958A TW 98109958 A TW98109958 A TW 98109958A TW I462195 B TWI462195 B TW I462195B
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- Prior art keywords
- lead
- heat sink
- proximal ends
- fingers
- wire
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims description 35
- 238000000034 method Methods 0.000 title claims description 29
- 125000006850 spacer group Chemical group 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 230000000712 assembly Effects 0.000 claims description 6
- 238000000429 assembly Methods 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 4
- 238000012546 transfer Methods 0.000 claims description 4
- 230000008878 coupling Effects 0.000 claims description 3
- 238000010168 coupling process Methods 0.000 claims description 3
- 238000005859 coupling reaction Methods 0.000 claims description 3
- 230000017525 heat dissipation Effects 0.000 claims 1
- 230000008901 benefit Effects 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 239000010970 precious metal Substances 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000010079 rubber tapping Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L23/495—Lead-frames or other flat leads
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Die Bonding (AREA)
- Measurement Of The Respiration, Hearing Ability, Form, And Blood Characteristics Of Living Organisms (AREA)
Description
本發明係關於電子半導體晶片封裝總成及製造。更特定言之,本發明係關於製造工具及方法,其係用於防止及用於校正在半導體晶片封裝製造中的線接合期間造成之引線指變形。
在具引線之半導體晶片封裝中,一晶片大體上係使用一永久黏著劑貼附至一引線框架。在一些情況下,係需要藉由改良用於使熱自晶片離開至一封裝之一外部表面的路徑以提升該封裝之熱效能。在許多此等情況中,(例如)藉由熔接、分接或膠黏一散熱器至引線框架之晶片設置部分來將該散熱器併入至引線框架結構係為人已知。在其他情況中,一散熱器係鉚接在引線框架上的定位中,且一晶片係直接設置至散熱器表面。不論何種情況,由於其熱傳導性質,散熱器典型係由金屬(例如銅或銅合金)製成。在一些例子中,為了增加其熱傳導,散熱器係比晶片大,其在一平行於引線指之近端的平面中延伸。晶片、引線指及至少部分位於引線指下之散熱器的此類型配置係用於許多應用中,但其並非沒有問題。
一半導體晶片封裝內之電連接通常係藉由自晶片表面上之接合墊至引線指之近端的接合線製成。引線指典型自鄰近一接近該晶片之引線框架中的空隙的一端,延伸至在其中可造成電連接至外部環境之封裝外部處的一遠端。在一典型線接合程序期間,一球焊墊係使用熱、壓力且在許多情況下之超音波振動形成在晶片的一接合墊上。該線接著被拉至一引線指的近端,且一縫接合亦使用熱、壓力及通常超音波振動之一些組合在該處形成。
線接合設備大體上包括一熱區塊,其係由一剛性材料製成,用於在線接合期間提供熱及支撐該引線框架。根據一線接合程序,熱區塊被加熱至一預定溫度。一包括一引線框架、晶片及散熱器之引線框架總成,係置於一設於熱區塊中之空腔內且典型係藉由一關聯夾穩固在定位。線接合係接著製成自晶片至引線指且之後將該總成自熱區塊移除用於進一步處理,如囊封及最終分開。在許多應用中,在線接合期間支撐引線指之近端僅係將引線框架總成置入至一熱區塊的一支撐空腔內的事宜。
本發明係針對克服或至少減少在本文中所指之先前技術中存在之問題,及有用於一或多個迄今未預見至之優點,用於提供經改良的熱區塊,及其用於改良半導體晶片封裝總成之製造的相關方法。
在實現本發明之原理時,根據其較佳具體實施例,本發明提供新穎且有用之改良,用於製造在半導體晶片封裝總成中使用之引線框架;及相關裝置。在一些半導體晶片封裝中,引線指的近端係與一散熱器的表面平行地懸置。當置於一用於線接合之普通熱區塊空腔內時,此一引線框架總成係支撐在散熱器處,但與散熱器平行地懸置之引線指的近端係缺少橫向支撐。在線接合期間,引線指之懸置近端係藉由來自接合工具之壓力的施加偏轉「向下」,(例如)在與線接合之相反方向中。在一些情況下,經偏轉引線指在線接合期間接觸下方散熱器。然而,由於引線框架材料之機械性質(其典型係由例如鋁、銅或合金的金屬製成),引線框架具有一些容量以在接合工具的壓力被移除後朝向其原始形狀彈回。因此,在許多情況中,偏轉問題可能相對較次要,或甚至可被忽視。然而,在其他情況中,引線指之近端朝向其原始位置之返回有時不完全,因此此項技術中已知係提供在引線指及下方散熱器間之額外間隙,以致足夠距離係仍在引線指不完全彈回至其原始位置之事件中維持。在引線指及散熱器間提供經增加的間隙可導致較厚之封裝總成,其在大多數應用中係不符合需要。藉由減少此間隙使厚度最小化可能導致電問題及有缺陷的封裝總成。從電效能之觀點,係需要使接合線維持短。從成本之觀點,較短之線(其典型係從貴金屬製成)導致較低材料成本。因此,因為需要較長接合線,該問題不會藉由縮短引線指之近端以減少其對於偏轉所致的變形之敏感性的簡單手段而有助於解決方案。
關於間隙問題之裝配程序及缺陷的經驗、觀察、分析及仔細研究已導致本申請者決定在一些範例中,尤其係其中多個線接合係自一晶片形成至一在散熱器上懸置之單一引線指的該等應用,間隙問題可能會更經常遭遇。已觀察至在此等情況下,此一引線指之重複偏轉的效應可能會累積,結果多線接合引線指的近端因線接合程序變得永久變形。當封裝之幾何形狀包括一在與多接合引線指的近端平行之平面中延伸的散熱器時,由於在線接合期間藉由施加至引線指之壓力造成的變形,可使在一些情況下之多接合引線指的近端接觸(或幾乎接觸)散熱器。在此等情況下,可能導致不合需要之干擾、電容或甚至短路。本申請者已發展用於在封裝裝配期間減輕引線指變形的工具及技術。一般而言,本發明提供經改良之熱區塊及其使用之方法,用於確保在半導體晶片封裝總成中之引線指及下方散熱器間的適當間隙。本發明亦提供其中可確保在引線指及散熱器間之一選定間隙的封裝總成。
根據本發明之一態樣,一種用於裝配一半導體晶片封裝之方法的較佳具體實施例包括以下步驟:提供一金屬引線框架總成,該金屬引線框架總成具有一引線框架、一附接散熱器;及一附接半導體晶片。該引線框架之引線指各具有一近端,其係用於容納一或多個接合線。該等引線指的近端界定一平行於該散熱器的一表面的平面。一熱區塊之一線接合空腔係用來支撐該等引線指的近端,而接合線係附接地耦合晶片上的接合墊至引線指的近端。其後,熱區塊之一間隔空腔係用來調整在引線指的線接合近端及散熱器的表面間之間隙。
根據本發明的另一態樣,本發明之一較佳方法包括使用一熱區塊之一線接合空腔支撐引線指的近端,而附接該晶片之多個接合線耦合接合墊至一單一引線指的近端之步驟。
根據本發明之又另一態樣,一用於裝配一半導體晶片封裝之熱區塊包括一剛體,其具有經調適用於在線接合期間支撐一引線框架總成的一或多個線接合空腔。線接合空腔係組態成用以在線接合期間固持包括於引線框架總成中之一散熱器的表面緊靠引線框架總成之引線指的近端用於其支撐。該熱區塊亦包括一間隔空腔,其經調適在線接合之後使用,以便調整在引線指之線接合近端及散熱器的表面間之間隙。
根據本發明又另一態樣,一半導體晶片封裝具體實施例包括一引線框架總成,其具有一金屬引線框架及一附接散熱器。該引線框架之引線指各具有一近端;該等引線指的近端界定一平行於該散熱器之一表面的平面。一附接至引線框架之半導體晶片具有接合墊,其藉由接合線耦合至引線指之近端,至少一引線指係用一些接合線耦合至一些接合墊。引線指之線接合近端及散熱器的表面間之間隙係全部大約相等。
本發明具有包括但不限於以下各項之一或多項的優點:減少封裝結構中之厚度;增加製程中之產量及可靠性;改良封裝中之熱效能;及減少成本。本發明之此等及其他特性、優點及益處,可藉由熟習此項技術人士在仔細考慮與附圖有關的本發明之代表性具體實施例的詳述時瞭解。
儘管本文討論造成及使用本發明的各種範例性具體實施例,應瞭解本發明提供可在各種各樣特定背景中體現之本發明概念。應理解本發明可採用各種類型及材料之半導體封裝總成及相關製程實現而無須改變本發明的原理。為了清楚之目的,不包括熟習半導體晶片、封裝及製造技術之技術人士所熟悉之功能及系統的詳述。
一般而言,本發明提供熱區塊用於改良線接合,及使用其的方法,尤其係在其中線接合期間中之引線指偏轉可能為一潛在關注事項之應用。本發明之特性就減少完成封裝總成中之缺陷、改良熱效能、減少總成厚度、改良電效能;及減少成本方面係有利。
首先參考圖1,其說明一用於半導體晶片封裝之總成的本發明之熱區塊10的範例之俯視圖。熱區塊10較佳係由金屬或其他剛性熱傳導材料製成。熱區塊10係組態成用以容納一引線框架總成(未顯示),以便提供實體支撐至引線框架總成的表面及在線接合期間促進轉移熱至引線框架總成。熱區塊較佳係具有經加工之容納通道12,其經調適用於容納加熱器及/或熱電偶,用於維持選定之熱位準。空腔14、16係組態成用以容納引線框架總成之晶片設置部分,(例如)晶片漿片或散熱器。現亦參考圖2,熱區塊10之一剖面側視圖(沿圖1之線2取得)顯示空腔14、16係不相等之深度。一線接合空腔14較佳係具有一相對較淺深度D1,且一間隔空腔16較佳係具有一相對較深深度D2
。較佳係,真空埠18、20可分別提供至線接合空腔14及間隔空腔16。真空埠18、20若使用時係與一或多個關聯真空來源(未顯示)通連以便促進在裝配程序期間於空腔14、16中施加真空力。
現主要參考圖3A及3B,剖面部分側視圖描述一熱區塊10之範例性具體實施例,其在本發明之一較佳方法中的步驟之執行中支撐一引線框架總成34。一引線框架32提供一結構骨架,其用於引線框架總成34及最終用於該封裝。引線框架32具有接近一晶片38且向外延伸用於他處之可能電連接的之引線指36。一散熱器40較佳係具有一表面41,其係適用於容納晶片38的永久設置,及在平行於藉由引線指36的近端42界定之平面的一平面中延伸。或者,在一些情況下,取決於引線框架總成設計,引線框架之一部分(例如)或一晶片漿片或晶粒襯墊(未在圖3A及3B之較佳具體實施例中顯示)可被插入晶片及散熱器間。無論如何,如圖3A及3B中顯示,引線指36之近端42外伸於散熱器40之表面41的一部分。在圖3A中,熱區塊10係顯示使用一線接合空腔14以支撐引線框架總成34用於線接合。線接合空腔14係組態以致可使散熱器40載於引線指36的近端42上,在一接合線44附接期間之力施加期間提供對於引線指36的近端42之支撐。較佳係,線接合程序包括用於首先附接一接合線44至晶片38上之接合墊46及其後在引線指36的近端42上形成一接合的步驟。較佳係,線接合空腔14的深度D1係選定以便在線接合期間定位及固持散熱器40及引線指36的近端42於接觸中。在一些情況下,多個線接合可自一些接合墊(如46)形成至引線指36的相同近端42。如在箭頭48處顯示,可行使一如真空或彈簧力之力以便確保引線指36之近端42及散熱器40間之穩固接觸。一夾50較佳係在線接合期間穩固地固持引線框架總成34定位在熱區塊10中。彈簧或真空力可在外部產生。或者,引線框架可經組態以有助於在處理期間於所需方向中提供一彈簧力。
如圖3B中所述,繼線接合之後,線接合引線框架總成35較佳係自熱區塊10之線接合空腔14移動至間隔空腔16。間隔空腔16係組態成用以確保該正確間距係維持或復原至一線接合引線框架總成35。間距空腔16與線接合空腔14深度D1相比係相對深度D2
(圖3A)。該線接合引線框架總成35係使用一外部夾50a夾在熱區塊10上之定位中,且一如真空或彈簧力的力(藉由箭頭48a指示)較佳係行使以將散熱器40拉離開引線指36的近端42。因此,在線接合完成後,散熱器40表面41及引線指36的近端42間之間隙C
可被永久調整或再調整。尤其係,間隙C
可藉由彎曲引線指,或藉由彎曲引線框架的其他部分,或散熱器來調整。
參考圖4A至4C之系列,其說明本發明之一較佳方法的發展之範例之概念圖。在圖4A中,一熱區塊10係顯示具有一引線框架總成陣列37,其係準備用於進一步的封裝製造步驟。引線框架總成陣列37典型具有一些個別引線框架32,其係配置在一適用於製造一些完成半導體晶片封裝之陣列中。在此特定範例中,個別引線框架32係配置成列用於依串接式處理。引線框架32具有散熱器40,其係如顯示用鉚釘60貼附至引線框架32,或使用黏著劑或此項技術中
已知之其他永久附接貼附至一晶片漿片。一晶片38係貼附至散熱器40,或至插入晶片漿片(未顯示)。晶片38亦可在引線框架32係置於熱區塊10中後附接,只要其係在線接合前附接。熱區塊10包括線接合空腔14,用於接受陣列37之引線框架總成34,其包括引線框架32、散熱器40及附接晶片38。本發明之特徵係引線框架總成34具有引線指36,其中其近端42係懸置於散熱器40上。
如圖4B中說明,引線框架總成34較佳係定位在線接合空腔14中,以便當接合線44係使用此項技術中已知之標準線接合工具附接時支撐引線指36的近端42。較佳地,此係使用線接合室之預選定深度D1達成,且在一些情況下可藉由一向上力之行使來協助,該向上力例如一藉由一關聯真空幫浦(未顯示)在一真空埠18處提供的真空力,或藉由引線框架32本身之組態提供的彈簧力,其確保使散熱器40穩固接觸以在接合線44之附接期間當向下壓力係行使在近端42上時支撐引線指之外伸近端42。較佳係,複數個個別引線指36具有附接之多個接合線44。
其後,如圖4C中顯示那樣,線接合引線框架總成35係前進至間距空腔16,較佳係施加一向下力(如,一在埠20處施加之真空力或彈簧力),以便建立(或再建立)在引線指36之近端42及散熱器40的下方表面41間之有利間隙。較佳係,置於引線框架37之頂部上的一或多個夾穩固地固持引線框架32至熱區塊10。該等夾係自此等簡化視圖中省略。繼線接合及間距調整之後,引線框架陣列37典型係置於一
塊模中用於囊封及最終切割。
圖5係描述一半導體晶片封裝總成51之本發明的較佳具體實施例之範例的俯視圖。如顯示,本發明有利在於多個接合線(例如52)可線接合至一單一引線指36之近端42而非不可接受地減少引線指36及散熱器40下方表面間之間隙。封裝總成51較佳係用可固化介電質模化合物囊封件54囊封,例如此項技術中已知之塑膠或環氧樹脂。雖然變化係可能,但可固化介電質模化合物囊封件54典型併入晶片38、大多數引線指32及頂部表面41(如圖式中定向)及散熱器40之側,使引線指36的之遠端56及散熱器40的底部表面58曝露。較佳係使引線指36之近端42及晶片38間之空隙G係盡可能小如電氣上可實施者,因為其大體上需要使接合線44之長度最小化。圖6係圖5之封裝51沿線6取得的一部分之特寫圖,其提供一舉例說明具有多個52接合線44自晶片38上之接合墊46附接至一引線指36的近端42之較佳配置的替代視圖。引線指36及散熱器40間之間隙C
係藉由使用如本文描述之熱區塊維持在預定可接受容限內。
應理解本發明提供一較薄封裝,其係用於一給定散熱器厚度及/或致能將一較厚散熱器用於一給定封裝厚度。此外,本發明之增強可使在晶片及引線指之近端間的空隙之減少可能。在一些應用中,此繼而可致能使用較短接合線、改良電效能、節省貴金屬線及減少成本。
本發明之方法及裝置確保在引線指的近端及鄰近散熱器間之適當間隙,將具有一或多個有用優點賦予引線框架及
封裝總成,優點包括(但不限於)經改良電性質、減少厚度、經改良熱效能、增加耐久性及減少成本。雖然本發明已參考某些說明性具體實施例及特定優點描述,但本文所述並非意欲視為限制。例如,所示及描述之具體實施例中的步驟或材料之變化或組合可用於特定情況而不脫離本發明。熟習此項技術者在參考圖式、說明及申請專利範圍後將明白本發明之說明性具體實施例及其他優點及具體實施例的各種修改及組合。
10‧‧‧熱區塊
12‧‧‧通道
14‧‧‧空腔
16‧‧‧空腔/間隔空腔
18‧‧‧真空埠
20‧‧‧真空埠
32‧‧‧引線框架
34‧‧‧引線框架總成
35‧‧‧線接合引線框架總成
36‧‧‧引線指
37‧‧‧引線框架總成陣列
38‧‧‧晶片
40‧‧‧散熱器
41‧‧‧表面
42‧‧‧近端
44‧‧‧接合線
46‧‧‧接合墊
48‧‧‧箭頭
48a‧‧‧箭頭
50‧‧‧夾
50a‧‧‧外部夾
51‧‧‧半導體晶片封裝總成
52‧‧‧多個接合線可固化介電質模化合物囊封
54‧‧‧件
56‧‧‧遠端
58‧‧‧底部表面
60‧‧‧鉚釘
本發明自考慮以上詳述及附圖中可更加清楚,圖式中:圖1係一用於根據本發明之半導體晶片封裝的總成中之熱區塊的較佳具體實施例之範例的俯視圖;圖2係一圖1中介紹之熱區塊的較佳具體實施例之剖面側視圖;圖3A係一在本發明之較佳具體實施例的範例中之半導體封裝總成及熱區塊之剖面部分側視圖;圖3B係一在本發明之較佳具體實施例的範例中之半導體封裝總成及熱區塊之剖面部分側視圖;圖4A係一在本發明之一方法的較佳具體實施例之步驟中的一範例中之半導體封裝總成及熱區塊之俯視圖;圖4B係一在本發明之一方法的較佳具體實施例之步驟中的一範例中之半導體封裝總成及熱區塊之俯視圖;圖4C係一在本發明之一方法的較佳具體實施例之步驟中的一範例中之半導體封裝總成及熱區塊之俯視圖;
圖5係一描述一半導體封裝總成之本發明的較佳具體實施例之範例的俯視圖;及圖6係一在圖5中說明之半導體封裝總成的較佳具體實施例之範例的經選定部分之詳細俯視圖。
圖式係未按比例,且所示及討論之具體實施例的一些特徵係經簡化或放大用於說明原理及特性,以及本發明之預期及未預期優點。
10...熱區塊
14...空腔
18...真空埠
32...引線框架
34...引線框架總成
36...引線指
38...晶片
40...散熱器
41...表面
42...近端
44...接合線
46...接合墊
48...箭頭
50...夾
Claims (16)
- 一種用於裝配一半導體晶片封裝之方法,該方法包括以下步驟:提供一引線框架總成,該引線框架總成進一步包括:一金屬引線框架;一附接散熱器;及一具有接合墊之附接半導體晶片,其中該引線框架進一步包括複數個引線指,各引線指具有一近端用於容納一或多個接合線,該等引線指之該等近端界定一平行於該散熱器的一表面之平面,該等引線指亦具有一遠端用於電連接至該封裝外部;在使用一熱區塊之一線接合空腔支撐該等引線指的該等近端時,附接耦合該半導體晶片之複數個接合墊的複數個接合線至引線指的複數個近端;及之後,使用該熱區塊之一間隔空腔,調整在該等引線指之該等線接合近端及該散熱器的表面間之該間隙。
- 如請求項1之方法,其進一步包括用於囊封該晶片、接合線、該等引線指之近端及該散熱器之平行表面於介電質模化合物內之步驟。
- 如請求項1之方法,其進一步包括以下步驟:在使用一熱區塊之一線接合空腔支撐該等引線指的該等近端時,附接耦合該半導體晶片之複數個接合墊之複數個接合線至一單一引線指的該近端。
- 如請求項1之方法,其進一步包括在線接合期間在該線接合空腔內施加一真空力之步驟,以造成該散熱器之該表面支撐該等引線指的該等近端。
- 如請求項1之方法,其進一步包括在線接合期間在該線接合空腔內施加一彈簧該力之步驟,以造成該散熱器之表面支撐該等引線指的該等近端。
- 如請求項1之方法,其進一步包括在該間隔空腔內施加一真空力之步驟,以便調整該散熱器之該表面與該等引線指的該等近端間之該間隙。
- 如請求項1之方法,其進一步包括在該間隔空腔內施加一彈簧力之步驟,以便調整該散熱器之該表面與該等引線指的該等近端間之該間隙。
- 一種用於裝配一具有一引線框架總成之半導體晶片封裝之熱區塊,該熱區塊包括:一剛體,該剛體具有一或多個線接合空腔,其經調適用於在線接合期間藉由固持該引線框架總成之一散熱器的表面緊靠該引線框架總成之該等引線指的該等近端來支撐該引線框架總成;及一間隔空腔,其經調適用於調整在該等引線指之該等線接合近端及該散熱器的該表面間之該間隙。
- 如請求項8之熱區塊,其中該線接合空腔包括一深度,其經調適用於強迫該散熱器之該表面接觸一經插入引線框架總成之該等引線指的該等近端。
- 如請求項8之熱區塊,其中該間隔空腔包括一深度,其經選定用於強迫該散熱器之該表面遠離該等引線指的該等近端以調整其間的該間隙。
- 如請求項8之熱區塊,其中該間隔空腔包括一深度,其經選定用於強迫該等引線指之該等近端遠離該散熱器之該表面以調整其間的該間隙。
- 如請求項8之熱區塊,其進一步包括一真空埠,該真空埠係用於在線接合期間將一真空力傳達至該線接合空腔,以強迫該散熱器之該表面緊靠該等引線指的該等近端。
- 如請求項8之熱區塊,其進一步包括一真空埠,該真空埠係用於將一真空力傳達至該間隔空腔,以強迫支撐在該間隔空腔內之一散熱器之表面繼線接合之後遠離該等引線指的該等近端。
- 如請求項8之熱區塊,其進一步經組態用以在線接合期間將一機械力傳輸至支撐在該線接合空腔內之一引線框架總成,以強迫該散熱器之該表面緊靠該等引線指的該等近端。
- 如請求項8之熱區塊,其進一步經組態以傳輸一機械力用於傳達一真空力至該間隔空腔,以強迫該散熱器之該表面繼線接合之後遠離該等引線指的該等近端。
- 一種半導體晶片封裝,其包括:一引線框架總成,其進一步包括一金屬引線框架;及一散熱器,其係附接至該引線框架,該引線框架具有複數個引線指,各引線指具有一近端用於容納一或多個線接合,該等引線指的該等近端界定一平行於該散熱器之一表面的平面,該等引線指亦具有一遠端用於電連接該封裝外部;一半導體晶片,其係附接至該引線框架總成,該晶片具有接合墊;複數個接合線,其係耦合複數個該等接合墊至複數個該等引線指之該等近端;其中一或多個引線指係用複數個接合線耦合至複數個接合墊;且其中該等引線指之該等線接合近端及該散熱器的該表面間之該間隙係全部大約相等。
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US8138027B2 (en) | 2008-03-07 | 2012-03-20 | Stats Chippac, Ltd. | Optical semiconductor device having pre-molded leadframe with window and method therefor |
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