TWI459560B - 單體整合式場效電晶體（fet）及蕭特基二極體、半導體結構、及溝道mos障壁蕭特基（tmbs)整流器 - Google Patents

單體整合式場效電晶體（fet）及蕭特基二極體、半導體結構、及溝道mos障壁蕭特基（tmbs)整流器 Download PDF

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TWI459560B
TWI459560B TW096145647A TW96145647A TWI459560B TW I459560 B TWI459560 B TW I459560B TW 096145647 A TW096145647 A TW 096145647A TW 96145647 A TW96145647 A TW 96145647A TW I459560 B TWI459560 B TW I459560B
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fet
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channel
schottky
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Fred Session
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Fairchild Semiconductor
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Description

單體整合式場效電晶體(FET)及蕭特基二極體、半導體結構、及溝道MOS障壁蕭特基(TMBS)整流器 發明領域 相關申請案之交叉參考
此申請案係主張2006年12月6日提申的美國臨時專利案60/868,884之利益，其揭示對於所有用途被完整合併於本文中以供參考。
此申請案亦有關2004年12月29日提申之共同讓渡的美國申請案11/026,276，其揭示對於所有用途被完整合併於本文中以供參考。
 發明背景
本發明係有關半導體功率裝置技術且更特別有關單體整合式溝道FET及蕭特基二極體裝置及溝道MOS障壁蕭特基(TMBS)整流器及其製造方法。
在其中使蕭特基二極體整合於一溝道閘極結構之功率裝置結構(譬如，TMBS整流器或單體整合性溝道閘極FET及蕭特基二極體裝置)中，已知的蕭特基接觸蝕刻技術係產生將導致不良障壁金屬階梯覆蓋率及高漏電流之拓樸結構。這些技術係基於其中需要對於下屬材料的選擇性之標準接點蝕刻製程。一種此技術顯示於第1A-1B圖中。
如第1A及1B圖所示，裝置的蕭特基二極體區中，進行一選擇性介電蝕刻以形成如藉由留存的介電部分116所界定之蕭特基接觸開口。因為蕭特基區中的所產生地形不適 合形成障壁金屬，進行一矽的選擇性軟蝕刻以改良地形。然而，軟蝕刻製程將：(1)添加另一製程步驟，(2)導致源極接點132的過切因此使源極金屬更接近通路區，及(3)不利地影響源極接點的金屬充填特徵。並且，可從第1B圖看出，雖然地形被軟蝕刻略為改良，障壁金屬122仍有不良的階梯覆蓋率。
因此，需要一顯著地改良蕭特基接觸區域中的地形且盡量降低漏電流之技術。
 發明概要
根據本發明的一實施例，一單體整合式溝道FET及蕭特基(Schottky)二極體係包括複數個延伸至一半導體層的一FET區及一蕭特基區內之溝道。一位於蕭特基區中之溝道係包括一用於襯墊溝道側壁之介電層，及一具有與該溝道相鄰之半導體區的一頂表面實質地共面之一頂表面之傳導性電極。一互連層係電性接觸蕭特基區中之半導體層藉以與半導體層形成一蕭特基接觸。
一實施例中，一位於FET區中之溝道係包括一用於襯墊溝道的下側壁及底部之屏蔽介電層，一配置於溝道的一底部分中之屏蔽電極，一位於屏蔽電極上方之間電極介電層，及一用於襯墊上溝道側壁之閘極介電層。閘極介電層係薄於屏蔽介電層。FET區中之溝道進一步包括間電極介電層上方之一閘極電極。
另一實施例中，一位於蕭特基區中之溝道只包括一傳 導性電極。
根據本發明的另一實施例，一用於形成一單體整合式溝道FET及蕭特基二極體之方法係包括下列步驟。複數個溝道形成於一半導體層的一FET區及一蕭特基區中。一凹入傳導性電極形成於各溝道中。藉由移除半導體層的至少一部分及一溝道中之一凹入傳導性電極的一部分使得蕭特基區中之半導體層的一頂表面及凹入傳導性電極的一頂表面實質地共面藉以將一接點開口形成於蕭特基區中。
一實施例中，形成接點開口之後，一電性接觸半導體層的表面之互連層係形成為藉以形成與半導體層之一蕭特基接觸。
另一實施例中，形成接點開口之前，一介電層形成於半導體層上方，且形成一接點開口之步驟進一步包括移除介電材料的一部分。
另一實施例中，介電層的部分、半導體層的至少一部分及一溝道中之一傳導性電極的部分皆利用一用於以實質相同速率來蝕刻介電層及半導體基材之蝕刻製程被移除。
另一實施例中，介電層的部分、半導體層的至少一部分及一溝道中之一傳導性電極的部分皆利用一在介電層與半導體層之間具有低選擇性之蝕刻製程被移除。
另一實施例中，形成一接點開口之前，一保護層形成於介電層上方，接著移除保護層的至少一部分以界定接點開口。
可參照圖式及說明書的其餘部分來進一步瞭解此處所 揭露之本發明的優點及本質。
圖式簡單說明
第1A-1B圖為描繪一已知蕭特基接觸蝕刻技術之簡化橫剖視圖；第2A-2F圖為根據本發明的一實施例之一用於形成一單體整合式經屏蔽閘極FET及蕭特基二極體之製程的不同階段之簡化橫剖視圖；第3圖顯示一單體整合式溝道閘極FET及蕭特基二極體之簡化橫剖視圖，其中使用根據本發明的一實施例之蕭特基接觸蝕刻技術來獲得蕭特基區中之一實質平面互連層；第4圖顯示一TMBS整流器的簡化橫剖視圖，其中使用根據本發明的一實施例之蕭特基接觸蝕刻來獲得一實質平面互連層；及第5圖為比較使用根據本發明的一實施例之低選擇性蝕刻技術製造的單體整合式溝道閘極FET及蕭特基二極體裝置之汲極-源極洩漏vs.使用習知蝕刻技術所製造的單體整合式溝道閘極FET及蕭特基二極體裝置之圖形。
 較佳實施例之詳細說明
根據本發明的一實施例，揭露一具有實質降低的介電質對於矽選擇性之蕭特基接觸蝕刻製程，其不需要中間步驟(諸如軟蝕刻)。降低的選擇性係導致一較平面化(亦即降低的拓樸結構)的表面。此降低的拓樸結構轉而導致形成一可供顯著降低汲極-源極洩漏(一實施例中為10倍)之實質平 面障壁金屬。本發明的其他特徵結構及優點揭露於下文。
第2A-2F圖為根據本發明的一實施例之一用於形成一單體整合式經屏蔽閘極FET及蕭特基二極體之製程的不同階段之簡化橫剖視圖。第2A-2F圖中，顯示蕭特基二極體區位於圖中右側且顯示FET區位於左側。請瞭解只有裝置之主動區的一小部分顯示於第2A-2F圖中，且可能有許多種整合蕭特基二極體及FET之方式。類似於第2A-2F圖所示者之許多蕭特基區一般係以一部份依據蕭特基二極體區域的所想要百分比而定之預定頻率散佈遍及裝置的主動區。雖顯示一給定蕭特基區中的三個溝道，更多或更少個溝道可形成於蕭特基區中。
第2A圖中，溝道201延伸至半導體區202內。一實施例中，半導體區為一形成於一高度摻雜基材(未圖示)上方之輕度摻雜n-型磊晶層，且溝道201終止於磊晶層中。另一實施例中，溝道201延伸至基材內且終止於基材中。第2A圖中，利用已知技術形成一用於襯墊溝道側壁及底部之屏蔽介電層204(譬如，包含氧化物)。屏蔽電極206(譬如，包含經摻雜或未摻雜多晶矽)隨後利用習知方法形成於各溝道的一底部分中。
第2B圖中，間電極介電質208(譬如，包含氧化物)利用已知方法在各溝道中形成於屏蔽電極206上方。第2C圖中，一凹入閘極電極212(譬如，包含經摻雜或未摻雜多晶矽)利用習知技術在各溝道中形成於間電極介電質208上方。第2D圖中，一介電層216(譬如，包含BPSG、未摻雜氧化物、及 PSG之一或多者)形成於結構上方。FET區中，源極接點開口232利用已知罩幕技術形成於介電層216中。經由源極接點開口曝露之矽表面隨後係凹入以形成重體部接點開口，如圖所示。
第2E圖中，利用習知技術形成一只在蕭特基區上方具有開口之罩幕層226(譬如，包含光阻)。罩幕層226因此覆蓋所有FET區。利用一以與其蝕刻下屬的矽實質相同之速率來蝕刻介電層216之蝕刻製程，介電層216的經曝露部分及下屬的矽之一部分係被移除藉以在蕭特基區中獲得一平面表面。根據其中介電層216包含BPSG之本發明的一實施例，第2E圖中的蝕刻製程係設計成在矽與氧化物之間具有從極小選擇性到沒有選擇性。可看出，第2E圖所描繪的蝕刻製程不需要一分離的平面化媒體(諸如旋覆玻璃)或CMP，且身為一局部化蝕刻(亦即，限於蕭特基區)且因此並非全面蝕刻。
可以數種方式達成介電質對於矽選擇性之降低。一實施例中，修改氣體比值以盡量減少或消除將抑制矽蝕刻速率之聚合化氣體。另一實施例中，自由氟濃度在電漿中增高以增強矽蝕刻速率。可利用諸如氧、SF6(六氟化硫)及/或NF3(三氟化氮)等氣體添加物達成此作用。亦可藉由增加RF輸送頻率來增加自由氟濃度以更好地解離蝕刻劑氣體。另一實施例中，操縱壓力及功率使蝕刻成為較非物理性且較為化學性的製程。可藉由降低晶圓上的RF偏壓來達成此作用。可使用這些技術任一者或其一組合來降低介電質對於矽選擇性。部分實施例中，使用10KHz及3GHz之間(譬 如，400KHz的標稱值)的RF輸送頻率、10mTorr至1Torr之間(譬如，600mTorr的標稱值)的製程壓力、100Watt至2000Watt(譬如，400Watt的標稱值)的輸入功率、40sccm至100sccm(譬如，80sccm的標稱值)之間的主蝕刻劑氣流、及0sccm至100sccm之間(譬如，20sccm的標稱值)的氧、氮或氟添加、及0℃至100℃(譬如，20℃的標稱值)的製程溫度之不同組合以抵達所想要的選擇性。
第2F圖中，一正形性障壁金屬層222利用已知技術形成於結構上方。可看出，障壁金屬222在蕭特基區中實質呈平面。一實施例中，障壁金屬222包含一雙層的鈦-鎢及鈦-矽化物。一傳導層224(譬如，包含鋁)隨後形成於障壁金屬222上方。傳導層224連同障壁金屬層222一起形成源極互連件。可看出源極互連件係電性接觸重體部區220及源極區218但絕緣於FET區中之閘極電極212。蕭特基區中，形成蕭特基二極體而其中源極互連件係接觸溝道之間的台面區202。源極互連件亦接觸蕭特基區溝道中之閘極電極212。因此，蕭特基區中之閘極電極212在操作期間被電性偏壓至源極電位。
包括體部區214、重體部區220及源極區218之FET的不同區被包括在第2F圖中只用以顯示完整的裝置，且因此未反映使其形成之製程順序。亦即，體部區、重體部區及源極區可在製程的任何適當階段形成。
第3圖為一單體整合式溝道閘極FET及蕭特基二極體之簡化橫剖視圖，其中可有利地使用根據本發明的一實施例 之蕭特基接觸蝕刻技術來獲得蕭特基區中的一實質平面障壁金屬層。包括一閘極電極312而無下屬屏蔽電極之溝道301係終止於漂移區302中。或者，溝道301可延伸至且終止於漂移區302下屬之一高度摻雜基材(未圖示)中。如圖所示，各溝道301包括沿著溝道的一底部分之一厚底介電質(譬如，包含氧化物)以降低閘極至汲極電容，及一用於襯墊溝道側壁之較薄閘極介電質(譬如，包含閘極氧化物)。或者，一具有相對較均勻厚度之閘極介電層沿著溝道側壁及底部延伸。利用連同先前實施例所述的相同蕭特基接觸蝕刻製程及其變異來達成蕭特基區中之一實質平面表面。因此在蕭特基區中獲得一實質平面障壁金屬322。
請注意雖然第2A-2F及3圖所描繪的實施例顯示一n-通路FET，可藉由使不同半導體區的極性反轉來獲得p-通路FET。並且，在漂移區202及302身為一延伸於一基材上方的磊晶層之實施例中，獲得MOSFET其中基材及磊晶層為相同傳導類型，且獲得IGBT其中基材具有與磊晶層相反的傳導類型。其只是根據本發明使用蕭特基接觸蝕刻以獲得平面表面及優越洩漏效能之數項溝道FET裝置。此處所揭露的蕭特基接觸蝕刻技術及其變異可用來形成許多其他類型的結構及裝置以獲得類似的優點及特徵結構。譬如，不同類型及結構的功率裝置揭露於2004年12月29日提申的上述美國專利申請案11/026,276中。熟習該技術者將瞭解如何將一蕭特基二極體整合在這些裝置中，特別是譬如美國專利申請案11/026,276的第1、2A、3A、3B、4A、4C、5C、9B、 9C、10-12、及24圖顯示之溝道閘極、經屏蔽閘極、及電荷平衡裝置中。熟習該技術者將鑒於此揭示進一步知道如何在形成此等整合式FET及蕭特基二極體裝置時併入此處所揭露的蕭特基接觸蝕刻或其變異。
第4圖顯示一TMBS整流器的簡化橫剖視圖，其中使用上述的蕭特基接觸蝕刻技術以獲得一實質平面障壁金屬408。各溝道401襯墊有一絕緣層406(譬如，包含氧化物)且充填有一傳導性電極406(譬如，包含經摻雜或未摻雜多晶矽)。傳導性電極406被電性連接且因此偏壓至與包含導體410(譬如，包含鋁)及障壁金屬層408(譬如，包含一雙層的鈦-鎢及鈦-矽化物)之頂側互連層相同的電位。第2F、3及4圖所示的裝置之操作係為該技藝熟知且因此不予描述。
第5圖為比較根據本發明的一實施例利用低選擇性蝕刻技術所製造的單體整合式溝道閘極FET及蕭特基二極體裝置之汲極-源極洩漏vs.利用習知蝕刻技術所製造的單體整合式溝道閘極FET及蕭特基二極體裝置之圖形。第5圖圖形中的垂直軸線代表源極-汲極洩漏而水平軸線代表不同群組的裝置。利用低選擇性蝕刻所形成的裝置之資料點已被圈起。可看出，相較於使用習知蝕刻技術之裝置者，使用低選擇性蝕刻的裝置之源極-汲極洩漏係實質地較低(相差6或更大的因數)。
下表列出其中不使用軟蝕刻、使用10秒軟蝕刻、及使用20秒軟蝕刻之三種習知裝置的源極-汲極洩漏值。表中亦顯示根據本發明的一實施例對於使用低選擇性蝕刻技術所 製造的一裝置之對應的源極-汲極洩漏值。可看出，即便進行20秒的軟蝕刻，低選擇性蝕刻製程仍產生遠為更好的洩漏效能。
因此，已描述用於平面化一蕭特基接觸結構之低選擇性蝕刻技術而不需要中間步驟，諸如使用一平面化媒體(譬如，旋覆玻璃)或CMP等。介電質(譬如，氧化物)以與下屬的矽相同或接近相同之速率被蝕刻藉以降低蕭特基接觸區域中的拓樸結構。降低的拓樸結構導致較好的障壁金屬階梯覆蓋率。因此達成一實質較低的源極-汲極漏電流而無需軟蝕刻。
雖然此處顯示及描述數項特定實施例，本發明的實施例不在此限。譬如，雖然第2A-2F圖顯示蕭特基區溝道在結構上與FET區溝道相同，本發明不在此限。一實施例中，蕭特基區溝道利用已知技術被形成為只包括一傳導性電極(譬如，延伸至接近溝道頂部之屏蔽電極)。因此，本發明的範圍不應參照上文描述來決定，而應參照申請專利範圍及其完整均等範圍來決定。
116‧‧‧介電部分
122‧‧‧障壁金屬
132‧‧‧源極接點
201，301，401‧‧‧溝道
202‧‧‧半導體區，台面區
204‧‧‧屏蔽介電層
206‧‧‧屏蔽電極
208‧‧‧間電極介電質
212‧‧‧凹入閘極電極
214‧‧‧體部區
216‧‧‧介電層
218‧‧‧源極區
220‧‧‧重體部區
222‧‧‧正形性障壁金屬層
224‧‧‧傳導層
226‧‧‧罩幕層
302‧‧‧漂移區
312‧‧‧閘極電極
322‧‧‧實質平面障壁金屬
406‧‧‧傳導性電極
408‧‧‧障壁金屬層
410‧‧‧導體
第1A-1B圖為描繪一已知蕭特基接觸蝕刻技術之簡化橫剖視圖；第2A-2F圖為根據本發明的一實施例之一用於形成一 單體整合式經屏蔽閘極FET及蕭特基二極體之製程的不同階段之簡化橫剖視圖；第3圖顯示一單體整合式溝道閘極FET及蕭特基二極體之簡化橫剖視圖，其中使用根據本發明的一實施例之蕭特基接觸蝕刻技術來獲得蕭特基區中之一實質平面互連層；第4圖顯示一TMBS整流器的簡化橫剖視圖，其中使用根據本發明的一實施例之蕭特基接觸蝕刻來獲得一實質平面互連層；及第5圖為比較使用根據本發明的一實施例之低選擇性蝕刻技術製造的單體整合式溝道閘極FET及蕭特基二極體裝置之汲極-源極洩漏vs.使用習知蝕刻技術所製造的單體整合式溝道閘極FET及蕭特基二極體裝置之圖形。
201‧‧‧溝道
202‧‧‧半導體區，台面區
204‧‧‧屏蔽介電層
206‧‧‧屏蔽電極
208‧‧‧間電極介電質
212‧‧‧凹入閘極電極
214‧‧‧體部區
216‧‧‧介電層
218‧‧‧源極區
220‧‧‧重體部區
222‧‧‧正形性障壁金屬層
224‧‧‧傳導層

Claims (33)

  1. 一種單體整合式場效電晶體(FET)及蕭特基(Schottky)二極體，包含：一FET溝道，其配置於一半導體層之一FET區中，該FET區包含至少一FET；一蕭特基溝道，其配置於該半導體層之一蕭特基區中，該蕭特基區與該FET區不同並且包含一至該半導體層的蕭特基接觸，該蕭特基溝道包括一襯墊該蕭特基溝道一側壁的介電層及一具有與該蕭特基溝道相鄰之該半導體層的一頂表面呈實質共面之一頂表面的傳導性電極；及一互連層，其電性接觸於該蕭特基區中之半導體層以界定出對該半導體層的該蕭特基接觸。
  2. 如申請專利範圍第1項之單體整合式FET及蕭特基二極體，其中該介電層為一第一介電層且該傳導性電極為一第一傳導性電極，該FET溝道包括一襯墊該FET溝道之一側壁之一第二介電層及一第二傳導性電極，該互連層電性接觸於該第一傳導性電極但電性絕緣於該第二傳導性電極。
  3. 如申請專利範圍第1項之單體整合式FET及蕭特基二極體，其中相鄰該蕭特基溝道之該半導體層的該頂表面相對於該FET區中之該半導體層的一頂表面係為較低。
  4. 如申請專利範圍第1項之單體整合式FET及蕭特基二極體，其中該介電層為一第一介電層及該傳導性電極為一 第一傳導性電極，該FET溝道包括一襯墊該FET溝道一側壁之一第二介電層，以及一具有一高於該第一傳導性電極的該頂表面之頂表面的一第二傳導性電極。
  5. 如申請專利範圍第1項之單體整合式FET及蕭特基二極體，其中該FET區包括：一井區，其配置於該半導體層中；配置於該井區中之一源極區，該源極區與該FET溝道相鄰，且具有一與該井區之傳導類型相反的一傳導類型；及配置於該井區中之一重體部區，該重體部區具有與該井區之該傳導類型相同的一傳導類型，以及比該井區之摻雜濃度更高的一摻雜濃度，該互連層電性接觸於該源極區及該重體部區。
  6. 如申請專利範圍第5項之單體整合式FET及蕭特基二極體，其中該FET包括一溝道金屬氧化物半導體場效電晶體(MOSFET)，該半導體層包括一配置於一基材上之磊晶層，該磊晶層具有比該基材之摻雜濃度更低的一摻雜濃度，該井區配置於該磊晶層中，且該磊晶層及該基材具有相同的一傳導類型，此等傳導類型與該井區之該傳導類型相反。
  7. 如申請專利範圍第5項之單體整合式FET及蕭特基二極體，其中該FET包括一溝道絕緣閘雙極電晶體(IGBT)，該半導體層包括一配置於一基材上之磊晶層，該磊晶層具有一比該基材之摻雜濃度更低的一摻雜濃度，該井區 配置於該磊晶層中，並且該磊晶層具有與該井區之該傳導類型相反且與該基材之一傳導類型相反的一傳導類型。
  8. 如申請專利範圍第1項之單體整合式FET及蕭特基二極體，其中該FET溝道包括：一屏蔽介電層，其襯墊該FET溝道的一下側壁及一底部表面；一屏蔽電極，其配置於該溝道的一底部分中；一間電極介電層，其配置於該屏蔽電極上；一閘極介電層，其襯墊該FET溝道的一上側壁，該閘極介電層薄於該屏蔽介電層；及一閘極電極，其配置於該間電極介電層上。
  9. 如申請專利範圍第8項之單體整合式FET及蕭特基二極體，其中該蕭特基溝道包括僅一個傳導性電極。
  10. 如申請專利範圍第1項之單體整合式FET及蕭特基二極體，其中該蕭特基溝道及該FET溝道各包括：一屏蔽介電層，其襯墊一下溝道側壁及一底部溝道表面；一屏蔽電極，其配置於該屏蔽介電層內；一間電極介電層，其配置於該屏蔽電極上；一閘極介電層，其襯墊一上溝道側壁，該閘極介電層薄於該屏蔽介電層；及一閘極電極，其配置於該間電極介電層上。
  11. 如申請專利範圍第1項之單體整合式FET及蕭特基二極 體，其中該介電層為一第一介電層，該FET溝道包括：一第二介電層，其襯墊該FET溝道之一側壁及一底部表面，該第二介電層沿著該FET溝道之該底部表面係厚於沿著該FET溝道之該側壁；及一凹入閘極電極。
  12. 一種半導體結構，包含：一第一溝道，其配置於一半導體層的一第一區中，該第一區包含一溝道場效電晶體(FET)，該第一溝道具有一第一傳導性電極配置於其中，該第一傳導性電極的一頂表面相對於該半導體層的該第一區之一頂表面呈凹入；及一第二溝道，其配置於該半導體層的一第二區中，該第二區與該第一區不同並且包含一整流器，該第二溝道具有一第二傳導性電極配置於其中，該第二傳導性電極具有一與該半導體層的該第二區之一頂表面呈實質共面之頂表面，在半導體結構中，該半導體層的該第一區之該頂表面高於該半導層的該第二區之該頂表面。
  13. 一種溝道MOS障壁蕭特基(TMBS)整流器，其包含：複數個溝道，其配置於一半導體層中，該複數個溝道之一溝道包括：一介電層，其墊襯該溝道之一側壁；及一傳導性電極，其具有一與相鄰該溝道之該半導體層的一頂表面呈實質共面之頂表面；及一互連層，包括一正形性(conformal)障壁金屬 層，該互連層接觸該半導體層藉以形成對該半導體層之蕭特基接觸。
  14. 如申請專利範圍第13項之TMBS整流器，其中該正形性障壁金屬層直接接觸該傳導性電極。
  15. 如申請專利範圍第13項之TMBS整流器，其中該正形性障壁金屬層為實質平面。
  16. 如申請專利範圍第13項之TMBS整流器，其中該互連層包括一金屬層，其配置於該正形性障壁層上且直接接觸該正形性障壁層。
  17. 一種半導體結構，包含：一場效電晶體(FET)溝道，其位於一半導體層之一FET區中，該FET區包含至少一FET，該FET溝道具有一FET傳導性電極於其中，該FET傳導性電極具有一相對於與FET區中之FET溝道關聯之一源極區之一頂表面為凹入的頂表面；及一蕭特基溝道，其位於該半導體層之一蕭特基區中，該蕭特基區與該FET區不同並且包含一至該半導體層的蕭特基接觸，該蕭特基溝道具有一蕭特基傳導性電極於其中，該蕭特基溝道中之蕭特基傳導性電極具有一與蕭特基區中一台面區之頂表面呈實質共面之頂表面，該台面區之該頂表面形成至少一部分的一蕭特基接觸，該FET區之該源極區的該頂表面高於該蕭特基區之該台面區的該頂表面。
  18. 如申請專利範圍第17項之半導體結構，其中該半導體層 的該FET區包括一溝道FET，而該半導體層的該蕭特基區包括一整流器。
  19. 如申請專利範圍第17項之半導體結構，該FET區包含：一井區，其延伸至該半導體層中，該源極區被配置於該井區中相鄰於該FET溝道，該源極區與該井區為相反的傳導類型；一重體區，其配置於該井區中，該重體區與該井區為一相同傳導類型，但比該井區具有更高的摻雜濃度；及一互連層，其電性接觸於該源極區及該重體區。
  20. 如申請專利範圍第17項之半導體結構，其中該FET區包括一溝道絕緣閘雙極二極體(IGBT)，該半導體層包括：一磊晶層，其延伸於一基材上方，該磊晶層具有比基材更低之摻雜濃度；及一井區，其延伸於該基材中，且具有與該磊晶層之傳導類型相反的傳導類型，該井區與該基材具有相同的一傳導類型。
  21. 如申請專利範圍第17項之半導體結構，其中該FET溝道包括：一屏蔽介電層，其襯墊該FET溝道的一下側壁及一底部區；一屏蔽電極，其配置於該FET溝道之底部區中；一間電極介電層，其配置於該屏蔽電極頂側； 一閘極介電層，其襯墊該FET溝道之一上側壁，該閘極介電層薄於該屏蔽介電層；及一閘極電極，其配置於該間電極介電層頂側。
  22. 如申請專利範圍第17項之半導體結構，其中該FET溝道包括一襯墊該FET溝道一側壁之介電層。
  23. 如申請專利範圍第17項之半導體結構，其中該蕭特基溝道包括僅一個傳導性電極。
  24. 如申請專利範圍第17項之半導體結構，其中該FET區包括：一介電層，其襯墊該FET溝道之一側壁及該FET溝道之一底部區，該介電層沿著該底部區比沿著該側壁更厚。
  25. 一種溝道MOS障壁蕭特基(TMBS)整流器，包含：一溝道，其延伸至一半導體層中；一介電層，其襯墊該溝道一側壁；一傳導性電極，其具有與相鄰該溝道之該半導體層的一頂表面為共面之一頂表面；及一互連層，其包括接觸該半導體層的該頂表面之一正形性障壁金屬層，藉以形成對該半導體層的頂表面之一蕭特基接觸，該正形性障壁層延伸於傳導性電極上方，且直接接觸傳導性電極之至少一部分。
  26. 如申請專利範圍第25項之TMBS整流器，進一步包含：一第二傳導性電極，其具有與相鄰該溝道之該半導體層的該頂表面為共面之一頂表面，該正形性障壁層直 接接觸該傳導性電極及該第二傳導性電極二者。
  27. 如申請專利範圍第25項之TMBS整流器，其中該正形性障壁金屬層為實質平面。
  28. 如申請專利範圍第25項之TMBS整流器，進一步包含：一第二傳導性電極，其具有與相鄰該溝道之該半導體層的該頂表面為共面之一頂表面，該第二傳導性電極具有與該半導體層之頂表面呈共面之一頂表面。
  29. 如申請專利範圍第25項之TMBS整流器，其中該互連層包括一金屬層於該正形性障壁層上方且直接接觸該正形性障壁層。
  30. 如申請專利範圍第25項之TMBS整流器，其中該傳導性電極被配置於該溝道內。
  31. 如申請專利範圍第25項之TMBS整流器，進一步包含：一場效電晶體(FET)區；及一蕭特基區，包括：該溝道、該介電層及該傳導性電極，該FET區具有一高於該蕭特基區之一台區的一頂表面之源極區的一頂表面。
  32. 如申請專利範圍第31項之TMBS整流器，其中該蕭特基區只包括僅一個傳導性電極。
  33. 如申請專利範圍第31項之TMBS整流器，其中該FET區包括：一FET溝道，其延伸至該半導體層中；及一介電層，其襯墊該FET溝道一側壁及該FET溝道 一底部區，該介電層沿著該底部區厚於沿著該側壁。
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