TWI458004B - 薄化晶圓的方法 - Google Patents

薄化晶圓的方法 Download PDF

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TWI458004B
TWI458004B TW100100620A TW100100620A TWI458004B TW I458004 B TWI458004 B TW I458004B TW 100100620 A TW100100620 A TW 100100620A TW 100100620 A TW100100620 A TW 100100620A TW I458004 B TWI458004 B TW I458004B
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wafer
adhesive
thinning
chemical
spraying
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TW201205654A (en
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Yu Liang Lin
Weng Jin Wu
Jing Cheng Lin
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Taiwan Semiconductor Mfg
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Weting (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Description

薄化晶圓的方法
本發明大體而言關於積體電路製造製程，且特別關於控制於薄晶圓處理(thin wafer handling)期間所產生之缺陷的方法。
積體電路係形成於半導體晶圓上。之後將半導體晶圓切割成晶片。積體電路的形成包括許多製程步驟，例如沈積、化學機械研磨(chemical mechanical polish,CMP)、電鍍等。因此，晶圓被運送於不同設備之間。
積體電路製造工業所面臨的挑戰為，為了改善成本效率，晶圓變得越來越大。於此際，晶圓也變得越來越薄。因此，薄晶圓遭受破損，特別是在運送與化學機械研磨製程期間，於此期間，機械應力(mechanical stress)可被提供於晶圓上。
為了減少破損之可能性，薄晶圓需要被增強。在一般製程中，為了執行薄化，首先將一載體結合至晶圓，且之後將晶圓薄化，例如，藉由一晶背研磨(backside grinding)步驟。介於載體與晶圓之間的結合係藉由一黏著劑來執行。在晶圓薄化製程之後，可於晶圓上執行額外之製程步驟。額外之製程步驟可包括乾蝕刻、物理氣相沈積(physical vapor deposition,PVD)、電漿輔助化學氣相沈積(plasma-enhanced chemical vapor deposition,PECVD)，其處理步驟包括電漿的使用。電漿與黏著劑露出之部分互相作用，且可導致氣泡產生於黏著劑中。所產生之氣泡可對晶圓提供向上力(upward force)，且向上力不均勻地被提供至分別之晶圓的不同部分。因此，在之後的製程步驟中，不利地影響著晶圓之總晶圓厚度變異(total wafer thickness variation,TTV)。此外，氣泡可導致黏著劑的一些部分被推至高於晶圓之頂部表面的平面，並且影響其後的製造製程。
在本發明的一態樣中，一種方法包括藉由一黏著劑結合一晶圓於一載體上與執行一薄化製程於該晶圓上。於該執行該薄化製程的步驟之後，移除該黏著劑未被該晶圓覆蓋的一部份，而不移除該黏著劑被該晶圓覆蓋的部份。
也揭露其他實施例。
為了讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉較佳實施例，並配合所附圖示，作詳細說明如下：
依照實施例提供控制於薄晶圓處理(thin wafer handling)中所產生之缺陷的新方法。以圖解說明實施例之中間階段。遍及不同之圖式與說明實施例中，使用相同之標號來表示相同之元件。
參見第1A與第1B圖，晶圓20被提供，並藉由黏著劑32結合至載體30。在一實施例中，晶圓20為一元件晶圓(device wafer)包括半導體基底22與積體電路24於其中。積體電路24可包括主動元件，例如電晶體，與被動元件，例如電阻器、電容器與其類似物。穿基板通孔(through substrate via,TSV)26可形成於晶圓20中。穿基板通孔26延伸進入半導體基底22，且電性耦接至積體電路24。在一實施例中，半導體基底22為一矽基底，然而其也可由其他半導體材料所形成。
依照一實施例，如於第1A圖中所示，晶圓20之正表面20a面朝下以接觸黏著劑32。因此，晶圓20之背表面20b也可為半導體基底22之背表面。所以晶圓20之隨後的薄化製程為一晶背研磨(backside grinding)製程。在如於第1B圖中所示的替代實施例中，晶圓20之正表面20a面朝上，其中晶圓20之隨後的薄化製程可為一化學機械研磨(chemical mechanical polish,CMP)。
晶圓20也可為另一形式的晶圓，例如一插入晶圓(interposer wafer)，其沒有主動元件，例如電晶體於其中。然而，被動元件，例如電阻器與電容器可形成於晶圓20中。或者，晶圓20可為一封裝基底(package substrate)之晶圓。
黏著劑32可包括橡膠、壓克力、矽膠或其組合。此外，黏著劑32可為一紫外光(ultra-violet,UV)黏著劑，當暴露於一紫外光下時，其可喪失黏著力。載體30可為一玻璃晶圓，然而，也可使用其他形式之常用載體。
參見第2圖，藉由一晶圓薄化製程將晶圓20薄化，其可為一化學機械研磨製程或晶背研磨製程。在其中執行一晶背研磨的實施例中，在晶圓薄化製程之後，穿基底通孔26可被露出。在一實施例中，在晶圓薄化製程期間，也將黏著劑32之部分進行研磨，且晶圓20之表面20c與黏著劑32之剩餘部分的平坦之頂部表面32a成水平。其觀察到剩餘黏著劑32包括未被晶圓20覆蓋之部分，與直接位於晶圓20下並被晶圓20覆蓋的部分。
之後，移除黏著劑32未被晶圓20覆蓋之部分。再如於第2圖中所繪示，例如以橫穿晶圓20之一中心的旋轉軸，將經薄化之晶圓20進行旋轉。使用噴嘴40以噴灑化學藥品42至黏著劑32上。噴嘴42可位於一固定位置。隨著晶圓20的旋轉，可將化學藥品42噴灑至所有環繞晶圓20之黏著劑32的露出部分。化學藥品42可被使用來移除黏著劑32，且可包括用以溶解黏著劑32的一溶劑(及/或稀釋劑(thinner))。在一示範實施例中，化學藥品42包括一溶劑、酒精或一稀釋劑。隨著晶圓20的旋轉，被溶解之黏著劑32與化學藥品42一起被旋出。
第3圖顯示在化學藥品42的噴灑之後所產生的結構。黏著劑32的表面32a(第2圖)至少於尺寸上被縮小，且可實質上被消除。然而，黏著劑32直接位於晶圓20下並被晶圓20覆蓋的部分未被移除。黏著劑32之剩餘部分的側壁32b可為傾斜的，且傾斜角α，其為介於黏著劑32之側壁32b與垂直線33之間的角度，可為介於約40度與約80度之間，然而，傾斜角α也可較大或較小。垂直線33為垂直於晶圓20的主要表面20c與載體30的主要表面30a。因此，如於第2圖中所示，噴嘴40可以傾斜角β噴灑化學藥品42，例如，傾斜角β介於約15度與約70度之間。噴嘴40也可以垂直向下方向來噴灑化學藥品42。沒有底切(undercut)，或實質上沒有底切形成於黏著劑32直接位於晶圓20下的部分中。因此，晶圓20被黏著劑32良好地支持著。
之後可執行額外之製程於晶圓20上，其製程可包括一化學機械研磨、一沈積、一乾蝕刻及/或其類似製程。這些製程可包含電漿的使用。第4圖顯示用以蝕刻基底22以使穿基底通孔26可突出於表面20c外的一示範乾蝕刻步驟，其中箭號表示電漿。其觀察到因為黏著劑32實質上沒有任何與晶圓20之表面20c在相同平面的頂部表面，所以降低了由於在黏著劑中之電漿而產生氣泡的可能性。此外，即使產生氣泡，氣泡也不可能導致晶圓20的不平衡(unevenness)。
其觀察到隨著實施例的使用，沒有觀察到總晶圓厚度變異(total wafer thickness variation,TTV)的降低。實驗顯示在執行如於第4圖中所示的電漿製程之前，一樣本晶圓之總晶圓厚度變異為約6.75 μm。在電漿製程之後，總晶圓厚度變異為約4.13 μm。相較而言，若不使用實施例，且黏著劑32的露出表面不被移除並遭受電漿，則在電漿製程之前與之後所測量的總晶圓厚度變異分別為6.1 μm與17.16 μm，其指出電漿製程導致在分別之樣本晶圓之總晶圓厚度變異中的顯著降低。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
20‧‧‧晶圓
20a‧‧‧晶圓20之正表面
20b‧‧‧晶圓20之背表面
20c‧‧‧晶圓20之表面
22‧‧‧半導體基底
24‧‧‧積體電路
26‧‧‧穿基板通孔(through substrate via,TSV)
30‧‧‧載體
30a‧‧‧載體30的主要表面
32‧‧‧黏著劑
32a‧‧‧黏著劑32之剩餘部分的平坦之頂部表面
32b‧‧‧黏著劑32之剩餘部分的側壁
33‧‧‧垂直線
40‧‧‧噴嘴
42‧‧‧化學藥品
α、β‧‧‧傾斜角
第1A、1B及2~4圖為依據實施例之晶圓薄化製程中間製程的剖面圖。
20．．．晶圓
20c．．．晶圓20之表面
22．．．半導體基底
24．．．積體電路
26．．．穿基板通孔(through substrate via,TSV)
30．．．載體
32．．．黏著劑

Claims (9)

  1. 一種薄化晶圓的方法，包括：藉由一黏著劑結合一晶圓於一載體上，其中該晶圓露出部分的該黏著劑；執行一薄化製程於該晶圓上；於該執行該薄化製程的步驟之後，移除該黏著劑未被該晶圓覆蓋的一部份，其中該黏著劑被該晶圓覆蓋的一部份不被移除；以及於該移除的步驟之後，對該晶圓執行一製程步驟，隨著電漿使用於該製程步驟中，其中於該製程步驟期間藉由該黏著劑該晶圓結合著該載體，且其中該製程步驟係擇自實質上由一沈積與一乾蝕刻所組成之群組。
  2. 如申請專利範圍第1項所述之薄化晶圓的方法，其中該移除的步驟包括噴灑一化學藥品至該黏著劑未被該晶圓覆蓋的該部份，且其中該化學藥品被設置來溶解該黏著劑。
  3. 如申請專利範圍第2項所述之薄化晶圓的方法，更包括在執行該噴灑該化學藥品的步驟之時，同時旋轉該晶圓，其中用以噴灑該化學藥品的一噴嘴為位於一固定位置。
  4. 如申請專利範圍第2項所述之薄化晶圓的方法，其中該化學藥品係擇自實質上由一溶劑、酒精、一稀釋劑與其組合所組成之群組。
  5. 如申請專利範圍第1項所述之薄化晶圓的方法，其中在開始該移除的步驟之時，該黏著劑包括一表面與 該晶圓的一表面呈水平，且其中於該移除的步驟之後，該黏著劑的該表面至少在尺寸上被縮小。
  6. 如申請專利範圍第5項所述之薄化晶圓的方法，其中於該移除的步驟之後，該黏著劑的該表面實質上被消除。
  7. 如申請專利範圍第1項所述之薄化晶圓的方法，其中於該移除的步驟之後，該黏著劑的一剩餘部分包括具有一傾斜角介於約40度與約80度之間的一傾斜側壁，以介於該傾斜側壁與一垂直於該載體之一主要表面的線之間來測量該傾斜角。
  8. 如申請專利範圍第1項所述之薄化晶圓的方法，其中於該移除的步驟之後，沒有底切形成於該黏著劑中並直接延伸於該晶圓下。
  9. 如申請專利範圍第3項所述之薄化晶圓的方法，其中於該噴灑該化學藥品的步驟期間，用以噴灑該化學藥品的該噴嘴為以一固定傾斜角位於一固定位置。
TW100100620A 2010-07-22 2011-01-07 薄化晶圓的方法 TWI458004B (zh)

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US12/841,874 US8722540B2 (en) 2010-07-22 2010-07-22 Controlling defects in thin wafer handling

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