TWI446499B - 具方向性電性連接之半導體覆晶裝置及其使用之基板 - Google Patents

具方向性電性連接之半導體覆晶裝置及其使用之基板 Download PDF

Info

Publication number
TWI446499B
TWI446499B TW100126463A TW100126463A TWI446499B TW I446499 B TWI446499 B TW I446499B TW 100126463 A TW100126463 A TW 100126463A TW 100126463 A TW100126463 A TW 100126463A TW I446499 B TWI446499 B TW I446499B
Authority
TW
Taiwan
Prior art keywords
substrate
electrical connection
chip device
spacer
flip chip
Prior art date
Application number
TW100126463A
Other languages
English (en)
Other versions
TW201306205A (zh
Inventor
Hian Hang Mah
Original Assignee
Powertech Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Priority to TW100126463A priority Critical patent/TWI446499B/zh
Priority to US13/450,188 priority patent/US8546942B2/en
Publication of TW201306205A publication Critical patent/TW201306205A/zh
Application granted granted Critical
Publication of TWI446499B publication Critical patent/TWI446499B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0286Programmable, customizable or modifiable circuits
    • H05K1/029Programmable, customizable or modifiable circuits having a programmable lay-out, i.e. adapted for choosing between a few possibilities
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16104Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/16105Disposition relative to the bonding area, e.g. bond pad the bump connector connecting bonding areas being not aligned with respect to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1705Shape
    • H01L2224/17051Bump connectors having different shapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171Disposition
    • H01L2224/17104Disposition relative to the bonding areas, e.g. bond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81194Lateral distribution of the bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81401Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/81411Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81444Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81894Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/81895Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81902Pressing the bump connector against the bonding areas by means of another connector by means of another bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5382Adaptable interconnections, e.g. for engineering changes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/10295Metallic connector elements partly mounted in a hole of the PCB
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10674Flip chip
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/17Post-manufacturing processes
    • H05K2203/173Adding connections between adjacent pads or conductors, e.g. for modifying or repairing
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means

Description

具方向性電性連接之半導體覆晶裝置及其使用之基板
本發明係有關於半導體裝置,特別係有關於一種具方向性電性連接之半導體覆晶裝置及其使用之基板。
覆晶接合已經是一種普遍熟知的晶片接合技術,晶片上設有凸塊,再以凸塊接合至基板之接墊,不需要打線空間,故能符合微小化與高密度端子之要求。然而,習知打線方式可利用銲線在基板上接點互換來改變晶片原本銲墊的功能,而凸塊與接墊之間為點對點的結合,在覆晶接合過程不能調整凸塊的功能,當需要製作不同功能腳位的半導體覆晶裝置時,基板的線路必須重新設計。
有鑒於此,本發明之主要目的係在於提供一種具方向性電性連接之半導體覆晶裝置及其使用之基板,結合了覆晶接合與打線連接之優點,能在製程中彈性改變半導體覆晶裝置的腳位功能,使基板具有共用性以製成不同功能之半導體覆晶裝置。
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明主要揭示一種具方向性電性連接之半導體覆晶裝置,係主要包含一晶片與一基板。該晶片係具有至少一第一凸塊與複數個第二凸塊。該基板係具有一上表面,該基板在該上表面設置有複數個水平狀之凸塊接墊,該基板內係更設有至少一方向性導接機構,係由複數個相互電性絕緣之端點以及一突出於該上表面之可撓性豎立墊片所構成,其中該些端點之配置位置係以該可撓性豎立墊片為中心而圍繞該可撓性豎立墊片。其中,當該晶片之該些第二凸塊接合於該些凸塊接墊,該第一凸塊係以一特定水平方向壓制該可撓性豎立墊片,使得該可撓性豎立墊片曲折變形,進而選擇性導接至該些端點之其中之一。本發明另揭示該半導體覆晶裝置所使用之基板。
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。
在前述的具方向性電性連接之半導體覆晶裝置中,該基板係可更具有一下表面、複數個設於該下表面之第一外接墊以及複數個設於該下表面之第二外接墊,該些第一外接墊係電性連接至對應之該些端點,該些第二外接墊係電性連接至該些凸塊接墊。
在前述的具方向性電性連接之半導體覆晶裝置中,該些端點係可包含複數個第一導通孔,並且該些端點於該下表面之一端係連接至該些第一外接墊。
在前述的具方向性電性連接之半導體覆晶裝置中,該基板係可更具有複數個第二導通孔,該些第二導通孔之兩端係分別連接至該些第二外接墊與該些凸塊接墊。
在前述的具方向性電性連接之半導體覆晶裝置中,該基板之該上表面係可形成有一墊片凹陷區,以容納已曲折變形之該可撓性豎立墊片。
在前述的具方向性電性連接之半導體覆晶裝置中,該墊片凹陷區係可由一防焊層之開口所構成。
在前述的具方向性電性連接之半導體覆晶裝置中,該第一凸塊係可對準於該可撓性豎立墊片並與每一之該些端點有一水平距離,該水平距離係不大於該可撓性豎立墊片之突出高度。
以下將配合所附圖示詳細說明本發明之實施例,然應注意的是,該些圖示均為簡化之示意圖,僅以示意方法來說明本發明之基本架構或實施方法,故僅顯示與本案有關之元件與組合關係,圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製,某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理,以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計,詳細之元件佈局可能更為複雜。
依據本發明之第一具體實施例,一種具方向性電性連接之半導體覆晶裝置100舉例說明於第1圖之在第一方向性電性連接狀態之截面示意圖與第2圖之在第二方向性電性連接狀態之截面示意圖。該半導體覆晶裝置100係主要包含一晶片110與一基板120,該晶片110與該基板120之立體示意圖可參見第4圖。該晶片110係具有至少一第一凸塊與複數個第二凸塊。該基板120係具有一上表面121,該基板120在該上表面121設置有複數個水平狀之凸塊接墊123。另,本發明所揭示該半導體覆晶裝置100使用之基板120可參閱第3圖之截面示意圖。
該晶片110係為半導體材質並佈設有各式所需要的積體電路於其主動表面,該第一凸塊111與該些第二凸塊112係作為該晶片110內部積體電路之對外端子。該基板120係作為該晶片110之承載體,該基板120可為印刷電路板或陶瓷電路板,亦可為一預模導線架。此外,當該半導體覆晶裝置100運用於一半導體封裝產品,該基板120係可更具有一下表面122、複數個設於該下表面122之第一外接墊124以及複數個設於該下表面122之第二外接墊125,該些第一外接墊124係電性連接至對應之該些端點131、132,該些第二外接墊125係電性連接至該些凸塊接墊123。
並且,該基板120內係更設有至少一方向性導接機構130,係由複數個相互電性絕緣之端點131、132以及一突出於該上表面121之可撓性豎立墊片133所構成。其中,該些端點131、132之配置位置係以該可撓性豎立墊片133為中心而圍繞該可撓性豎立墊片133。換言之,以該可撓性豎立墊片133所設置位置之中心點作為一預設圓之中心,該些端點131、132分佈在該預設圓之圓周,使每一端點131、132至該可撓性豎立墊片133的距離大致為相同。在本實施例中,該可撓性豎立墊片133係可為一銅片,其表面可電鍍金層或錫層。在覆晶接合之間,該可撓性豎立墊片133不電性連接至該些端點131、132。在更具體結構中,該些端點131、132係可包含複數個第一導通孔,並且該些端點131、132於該下表面122之一端係連接至該些第一外接墊124。更具體地,該基板120係可更具有複數個第二導通孔126,該些第二導通孔126之兩端係分別連接至該些第二外接墊125與該些凸塊接墊123。因此,此一上述構造可以省略在該基板120之該上表面121之線路結構,並且在該基板120之該下表面122之線路結構亦可以省略或簡化。
當該晶片110之該些第二凸塊112接合於該些凸塊接墊123,該第一凸塊111係以一特定水平方向壓制該可撓性豎立墊片133,使得該可撓性豎立墊片133曲折變形,進而選擇性導接至該些端點131、132之其中之一。此外,該第一凸塊111之形狀與材質可與該些第二凸塊112實質相同,以降低凸塊設置成本。在本實施例中,如第4圖所示,該第一凸塊111係為指狀凸塊(即長邊不小於寬邊之二倍),其材質可為成本較低之銅。較佳地,該第一凸塊111之突出端面邊緣可為弧狀,以便於導滑下壓該可撓性豎立墊片133。
在本實施例中,可參閱第5圖,在該晶片110下降到一適當高度但尚不接觸到該基板120之該些凸塊接墊123,使該第一凸塊111低於該可撓性豎立墊片133之突出高度H。之後,該晶片110為依照第一水平方向D1由圖中左往右方式水平移動,使該第一凸塊111壓制該可撓性豎立墊片133往右彎折並進一步下壓以接合至被選擇之端點131,其餘端點132則保持電性絕緣,即連接未選擇的端點132的第一外接墊124則為空腳位,同時該些第二凸塊112亦接合至該些凸塊接墊123,達到該晶片110之固定,即構成如第1圖所示之半導體覆晶裝置100。該些第二凸塊112對該些凸塊接墊123之接合關係可為銲料連接或是金屬鍵合,例如金-金鍵合、金-錫鍵合或是錫-銅鍵合;利用該可撓性豎立墊片133之彈性,該第一凸塊111與該可撓性豎立墊片133之電性連接關係可為電性接觸即可,或少量的銲料接合;該可撓性豎立墊片133在彎折之後對被選擇之端點131之電性連接關係可為銲料接合。
另可參閱第6圖,在該晶片110下降到一適當高度但尚不接觸到該基板120之該些凸塊接墊123,該晶片110為依照第二水平方向D2由圖中右往左方式水平移動,使該第一凸塊111壓制該可撓性豎立墊片133往左彎折並進一步下壓以接合至被選擇之端點132,而連接未選擇的端點131的第一外接墊124則為空腳位,同時該些第二凸塊112亦接合至該些凸塊接墊123,達到該晶片110之固定,即構成如第2圖所示之半導體覆晶裝置100’。較佳地,該第一凸塊111係可對準於該可撓性豎立墊片133並與每一之該些端點131、132有一水平距離S,該水平距離S係不大於該可撓性豎立墊片133之突出高度H,以確保已曲折變形之該可撓性豎立墊片133可導接至被選定之端點131、132。
因此,以上所述兩種半導體覆晶裝置100與100’雖元件相同,但利用覆晶接合過程中的操作調整,使該晶片110電性連接至外接墊的關係卻不相同,便產生了製造上的彈性。因此,本發明結合了覆晶接合與打線連接之優點,能在製程中彈性改變半導體覆晶裝置的腳位功能,使該基板120具有共用性以製成不同功能之半導體覆晶裝置100與100’。
較佳地,該基板120之該上表面121係可形成有一墊片凹陷區127,以容納已曲折變形之該可撓性豎立墊片133,可避免該可撓性豎立墊片133被過度彎折而斷裂。其中,該墊片凹陷區127係可由一防焊層之開口所構成,以降低該墊片凹陷區127之形成成本。在本實施例中,該防焊層係為形成於該上表面121之第一防焊層128,該第一防焊層128係具有一開口,以構成該墊片凹陷區127。另,運用在封裝產品時,該基板120之該下表面122亦可形成一第二防焊層129,以保護該下表面122但顯露出該些第一外接墊124與該些第二外接墊125。
以上所述,僅是本發明的較佳實施例而已,並非對本發明作任何形式上的限制,雖然本發明已以較佳實施例揭露如上,然而並非用以限定本發明,任何熟悉本項技術者,在不脫離本發明之技術範圍內,所作的任何簡單修改、等效性變化與修飾,均仍屬於本發明的技術範圍內。
100、100’...具方向性電性連接之半導體覆晶裝置
110...晶片
111...第一凸塊
112...第二凸塊
120...基板
121...上表面
122...下表面
123...凸塊接墊
124...第一外接墊
125...第二外接墊
126...第二導通孔
127...墊片凹陷區
128...第一防焊層
129...第二防焊層
130...方向性導接機構
131、132...端點
133...可撓性豎立墊片
D1...第一水平方向
D2...第二水平方向
H...可撓性豎立墊片之突出高度
S...第一凸塊至端點之水平距離
第1圖:依據本發明之一較佳實施例,一種具方向性電性連接之半導體覆晶裝置在第一方向性電性連接狀態之截面示意圖。
第2圖:依據本發明之一較佳實施例,一種半導體覆晶裝置在第二方向性電性連接狀態之截面示意圖。
第3圖:依據本發明之一較佳實施例,繪示第1圖之半導體覆晶裝置所使用之基板之截面示意圖。
第4圖:依據本發明之一較佳實施例,繪示該半導體覆晶裝置之第一凸塊與可撓性豎立墊片之立體示意圖。
第5圖:依據本發明之一較佳實施例,繪示在第1圖中半導體覆晶裝置在包含第一水平方向移動之覆晶接合時之截面示意圖。
第6圖:依據本發明之一較佳實施例,繪示在第2圖中半導體覆晶裝置在包含第二水平方向移動之覆晶接合時之截面示意圖。
110...晶片
111...第一凸塊
112...第二凸塊
120...基板
121...上表面
122...下表面
123...凸塊接墊
124...第一外接墊
125...第二外接墊
126...第二導通孔
127...墊片凹陷區
128...第一防焊層
129...第二防焊層
130...方向性導接機構
131、132...端點
133...可撓性豎立墊片
D1...第一水平方向
H...可撓性豎立墊片之突出高度

Claims (10)

  1. 一種具方向性電性連接之半導體覆晶裝置,包含:一晶片,係具有至少一第一凸塊與複數個第二凸塊;以及一基板,係具有一上表面,該基板在該上表面設置有複數個水平狀之凸塊接墊,該基板內係更設有至少一方向性導接機構,係由複數個相互電性絕緣之端點以及一突出於該上表面之可撓性豎立墊片所構成,其中該些端點之配置位置係以該可撓性豎立墊片為中心而圍繞該可撓性豎立墊片;其中,當該晶片之該些第二凸塊接合於該些凸塊接墊,該第一凸塊係以一特定水平方向壓制該可撓性豎立墊片,使得該可撓性豎立墊片曲折變形,進而選擇性導接至該些端點之其中之一。
  2. 根據申請專利範圍第1項之具方向性電性連接之半導體覆晶裝置,其中該基板係更具有一下表面、複數個設於該下表面之第一外接墊以及複數個設於該下表面之第二外接墊,該些第一外接墊係電性連接至對應之該些端點,該些第二外接墊係電性連接至該些凸塊接墊。
  3. 根據申請專利範圍第2項之具方向性電性連接之半導體覆晶裝置,其中該些端點係包含複數個第一導通孔,並且該些端點於該下表面之一端係連接至該些第一外接墊。
  4. 根據申請專利範圍第3項之具方向性電性連接之半導體覆晶裝置,其中該基板係更具有複數個第二導通孔,該些第二導通孔之兩端係分別連接至該些第二外接墊與該些凸塊接墊。
  5. 根據申請專利範圍第1項之具方向性電性連接之半導體覆晶裝置,其中該基板之該上表面係形成有一墊片凹陷區,以容納已曲折變形之該可撓性豎立墊片。
  6. 根據申請專利範圍第5項之具方向性電性連接之半導體覆晶裝置,其中該墊片凹陷區係由一防焊層之開口所構成。
  7. 根據申請專利範圍第1項之具方向性電性連接之半導體覆晶裝置,其中該第一凸塊係對準於該可撓性豎立墊片並與每一之該些端點有一水平距離,該水平距離係不大於該可撓性豎立墊片之突出高度。
  8. 一種具方向性電性連接之半導體覆晶裝置之基板,係具有一上表面,該基板在該上表面設置有複數個水平狀之凸塊接墊,該基板內係更設有至少一方向性導接機構,係由複數個相互電性絕緣之端點以及一突出於該上表面之可撓性豎立墊片所構成,其中該些端點之配置位置係以該可撓性豎立墊片為中心而圍繞該可撓性豎立墊片。
  9. 根據申請專利範圍第8項之具方向性電性連接之半導體覆晶裝置之基板,其中該基板之該上表面係形成有一墊片凹陷區,以容納已曲折變形之該可撓性豎立墊片。
  10. 根據申請專利範圍第9項之具方向性電性連接之半導體覆晶裝置之基板,其中該墊片凹陷區係由一防焊層之開口所構成。
TW100126463A 2011-07-26 2011-07-26 具方向性電性連接之半導體覆晶裝置及其使用之基板 TWI446499B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW100126463A TWI446499B (zh) 2011-07-26 2011-07-26 具方向性電性連接之半導體覆晶裝置及其使用之基板
US13/450,188 US8546942B2 (en) 2011-07-26 2012-04-18 Flip-chip semiconductor device having anisotropic electrical interconnection and substrate utilized for the package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW100126463A TWI446499B (zh) 2011-07-26 2011-07-26 具方向性電性連接之半導體覆晶裝置及其使用之基板

Publications (2)

Publication Number Publication Date
TW201306205A TW201306205A (zh) 2013-02-01
TWI446499B true TWI446499B (zh) 2014-07-21

Family

ID=47596565

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100126463A TWI446499B (zh) 2011-07-26 2011-07-26 具方向性電性連接之半導體覆晶裝置及其使用之基板

Country Status (2)

Country Link
US (1) US8546942B2 (zh)
TW (1) TWI446499B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11189988B2 (en) * 2019-06-10 2021-11-30 Lumentum Operations Llc Electrically isolating vertical-emitting devices

Also Published As

Publication number Publication date
US20130026625A1 (en) 2013-01-31
US8546942B2 (en) 2013-10-01
TW201306205A (zh) 2013-02-01

Similar Documents

Publication Publication Date Title
US9111818B2 (en) Packaging substrate
US9607963B2 (en) Semiconductor device and fabrication method thereof
KR20120091691A (ko) 휨 방지용 접합패턴을 갖는 반도체 소자 및 그 제조방법
JP2008131035A (ja) バンプ付き半導体チップ及びそれを備える半導体パッケージ
CN106298731B (zh) 电路板和包括该电路板的半导体封装件
TWI485829B (zh) Lead frame and wafer flip chip package using this lead frame
US10573614B2 (en) Process for fabricating a circuit substrate
TWI527186B (zh) 半導體封裝及其製造方法
US20130334684A1 (en) Substrate structure and package structure
KR20080054347A (ko) 반도체 장치 및 그 제조 방법
JP2011171411A (ja) 半導体装置の製造方法
TWI566352B (zh) 封裝基板及封裝件
TWI446499B (zh) 具方向性電性連接之半導體覆晶裝置及其使用之基板
TWI394252B (zh) 封裝基板結構
JP2005109088A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
CN105374805A (zh) 一种多芯片封装结构
TWI581392B (zh) 電子封裝組件
TWI483351B (zh) 半導體裝置及其製法
KR101534849B1 (ko) 플립칩 패키지 및 그 제조방법
KR20150090504A (ko) 패키지 기판
US8530754B2 (en) Printed circuit board having adaptable wiring lines and method for manufacturing the same
JP2006245396A (ja) 半導体装置及びその製造方法
KR200278534Y1 (ko) 칩 크기 패키지
TWI505422B (zh) 分散晶片角隅應力之窗口型球格陣列封裝構造
TWI492358B (zh) 半導體封裝件及其製法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees