TWI445110B - 分析半導體積體電路裝置之錯誤的方法及其系統 - Google Patents

分析半導體積體電路裝置之錯誤的方法及其系統 Download PDF

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Publication number
TWI445110B
TWI445110B TW096136266A TW96136266A TWI445110B TW I445110 B TWI445110 B TW I445110B TW 096136266 A TW096136266 A TW 096136266A TW 96136266 A TW96136266 A TW 96136266A TW I445110 B TWI445110 B TW I445110B
Authority
TW
Taiwan
Prior art keywords
wafer
error
defect
analogy
characteristic
Prior art date
Application number
TW096136266A
Other languages
English (en)
Chinese (zh)
Other versions
TW200822261A (en
Inventor
李鍾弦
Original Assignee
三星電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三星電子股份有限公司 filed Critical 三星電子股份有限公司
Publication of TW200822261A publication Critical patent/TW200822261A/zh
Application granted granted Critical
Publication of TWI445110B publication Critical patent/TWI445110B/zh

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2894—Aspects of quality control [QC]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56008—Error analysis, representation of errors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0403—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals during or with feedback to manufacture
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/40—Response verification devices using compression techniques
    • G11C2029/4002—Comparison of products, i.e. test results of chips or with golden chip
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5002—Characteristic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C2029/5606—Error catch memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
TW096136266A 2006-09-29 2007-09-28 分析半導體積體電路裝置之錯誤的方法及其系統 TWI445110B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060096065A KR100827440B1 (ko) 2006-09-29 2006-09-29 반도체 집적 회로 장치의 불량 분석 방법 및 시스템

Publications (2)

Publication Number Publication Date
TW200822261A TW200822261A (en) 2008-05-16
TWI445110B true TWI445110B (zh) 2014-07-11

Family

ID=39260994

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096136266A TWI445110B (zh) 2006-09-29 2007-09-28 分析半導體積體電路裝置之錯誤的方法及其系統

Country Status (4)

Country Link
US (1) US7733719B2 (enExample)
JP (1) JP5393965B2 (enExample)
KR (1) KR100827440B1 (enExample)
TW (1) TWI445110B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI588673B (zh) 2016-04-27 2017-06-21 亦思科技股份有限公司 半導體製程錯誤分析方法以及電腦程式產品

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US7552762B2 (en) * 2003-08-05 2009-06-30 Stream-Flo Industries Ltd. Method and apparatus to provide electrical connection in a wellhead for a downhole electrical device
KR100809340B1 (ko) * 2007-01-15 2008-03-07 삼성전자주식회사 반도체 집적 회로 장치의 불량 분석 방법 및 시스템
KR101529880B1 (ko) * 2008-10-31 2015-06-19 삼성전자주식회사 에러 추정 방법 및 정정 방법
JP2012018052A (ja) * 2010-07-07 2012-01-26 Toshiba Corp 半導体装置の不良解析システム及び方法
CN102385843A (zh) * 2011-08-11 2012-03-21 上海华碧检测技术有限公司 一种液晶面板显示驱动芯片的电性分析方法
US9277186B2 (en) * 2012-01-18 2016-03-01 Kla-Tencor Corp. Generating a wafer inspection process using bit failures and virtual inspection
TWI606531B (zh) 2017-03-30 2017-11-21 義守大學 適用於三維晶片的缺陷測試方法及系統
KR102589004B1 (ko) 2018-06-18 2023-10-16 삼성전자주식회사 반도체 불량 분석 장치 및 그것의 불량 분석 방법
US11934094B2 (en) * 2021-03-23 2024-03-19 International Business Machines Corporation Mask fingerprint using mask sensitive circuit

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JP3639636B2 (ja) * 1995-04-25 2005-04-20 株式会社ルネサステクノロジ 半導体ウェハの不良解析装置及び不良解析方法
US6009545A (en) * 1995-04-25 1999-12-28 Mitsubishi Denki Kabushiki Kaisha System for analyzing a failure in a semiconductor wafer by calculating correlation coefficient between collated data of defects per prescribed unit and failures per prescribed unit
JP2734416B2 (ja) * 1995-07-24 1998-03-30 日本電気株式会社 故障モードの特定方法及び装置
EP0853243A3 (en) 1997-01-13 1999-07-28 Schlumberger Technologies, Inc. Method and apparatus for detecting defects in wafers
JP3995768B2 (ja) * 1997-10-02 2007-10-24 株式会社ルネサステクノロジ 不良解析方法及びその装置
US6185707B1 (en) 1998-11-13 2001-02-06 Knights Technology, Inc. IC test software system for mapping logical functional test data of logic integrated circuits to physical representation
US6553521B1 (en) * 2000-02-24 2003-04-22 Infineon Technologies, Richmond L.P. Method for efficient analysis semiconductor failures
JP2002183554A (ja) * 2000-12-14 2002-06-28 Mitsubishi Electric Corp メモリデバイス販売装置、およびメモリデバイス販売方法
US6610550B1 (en) * 2002-04-03 2003-08-26 Advanced Micro Devices Method and apparatus for correlating error model with defect data
JP2003315415A (ja) 2002-04-23 2003-11-06 Mitsubishi Electric Corp 半導体デバイス解析システム
KR20050020012A (ko) * 2003-08-20 2005-03-04 삼성전자주식회사 웨이퍼 검사 장치 및 검사 방법
KR100748552B1 (ko) * 2004-12-07 2007-08-10 삼성전자주식회사 반도체 장치의 불량 분석을 위한 분석 구조체 및 이를이용한 불량 분석 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI588673B (zh) 2016-04-27 2017-06-21 亦思科技股份有限公司 半導體製程錯誤分析方法以及電腦程式產品

Also Published As

Publication number Publication date
KR100827440B1 (ko) 2008-05-06
KR20080029532A (ko) 2008-04-03
TW200822261A (en) 2008-05-16
JP5393965B2 (ja) 2014-01-22
JP2008091902A (ja) 2008-04-17
US7733719B2 (en) 2010-06-08
US20080080277A1 (en) 2008-04-03

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