TWI438831B - 形成淺接合的技術 - Google Patents
形成淺接合的技術 Download PDFInfo
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- TWI438831B TWI438831B TW097113025A TW97113025A TWI438831B TW I438831 B TWI438831 B TW I438831B TW 097113025 A TW097113025 A TW 097113025A TW 97113025 A TW97113025 A TW 97113025A TW I438831 B TWI438831 B TW I438831B
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- 238000000034 method Methods 0.000 title claims description 62
- 239000004065 semiconductor Substances 0.000 claims description 85
- 239000002019 doping agent Substances 0.000 claims description 65
- 238000010884 ion-beam technique Methods 0.000 claims description 51
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- 239000007943 implant Substances 0.000 claims description 38
- 150000001793 charged compounds Chemical class 0.000 claims description 36
- 238000005468 ion implantation Methods 0.000 claims description 36
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- 239000013078 crystal Substances 0.000 claims description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims 4
- 235000012431 wafers Nutrition 0.000 description 74
- 238000002513 implantation Methods 0.000 description 39
- 150000002500 ions Chemical class 0.000 description 35
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 26
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- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/02—Details
- H01J37/04—Arrangements of electrodes and associated parts for generating or controlling the discharge, e.g. electron-optical arrangement, ion-optical arrangement
- H01J37/08—Ion sources; Ion guns
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02592—Microstructure amorphous
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26593—Bombardment with radiation with high-energy radiation producing ion implantation at a temperature lower than room temperature
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/20—Positioning, supporting, modifying or maintaining the physical state of objects being observed or treated
- H01J2237/2001—Maintaining constant desired temperature
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/30—Electron or ion beam tubes for processing objects
- H01J2237/317—Processing objects on a microscale
- H01J2237/31701—Ion implantation
Description
本揭露內容大體而言有關於半導體製造,且更特定而言,有關於形成淺接合(shallow junction)的技術。
離子植入(Ion implantation)是一種藉由利用受激離子(energized ion)直接轟擊基板而向基板內沈積化學物質(chemical species)之製程。在半導體製造中,離子植入機(ion implanter)主要用於摻雜製程(doping process),摻雜製程改變目標材料之傳導類型和水準。在積體電路(integrated circuit,IC)基板和其薄膜結構中之精確摻雜分佈對於正常的IC效能常常是至關重要的。為了達成所要的摻雜分佈,可能以不同的劑量和在不同的能量植入一或多種離子物質。
圖1描繪了一種傳統的離子植入機系統100,其中可根據本揭露內容之一實施例來實施低溫離子植入之技術。如大多數離子植入機系統的典型情況,離子植入機系統100設於高真空環境中,離子植入機系統100可包括離子源102,其藉由電源101偏壓至一定電位;以及,複合系列之束線組件(complex series of beam-line component),離子束10穿過複合系列之束線組件。該系列之束線組件可包括(例如)提取電極(extraction electrode)104、90°磁分析儀(90° magnet analyzer)106、第一减速(D1)階段(first deceleration(D1)stage)108、70°磁准直儀(70° magnet
collimator)110以及第二减速(D2)階段(second deceleration(D2)stage)112。很像操縱光束之光學透鏡系列,束線組件可在使離子束10朝向目標晶圓轉向之前過濾並聚焦離子束10。在離子植入期間,目標晶圓通常安裝於壓板114上,壓板114可藉由有時被“台板(roplat)”的裝置在一個或多個維度(例如,平移、旋轉和傾斜)移動。
隨著半導體元件之持續小型化,對超淺接合的需求不斷增加。舉例而言,已做出巨大的努力來產生更好地活化、更淺且更陡的源極-汲極延伸接合(source-drain extension junction)來滿足現代互補金屬氧化物半導體(complementary metal-oxide-semiconductor,CMOS)元件之需要。
為了在結晶矽晶圓(crystalline silicon wafer)中產生陡的超淺接合,例如,可能會需要晶圓表面之非晶化。一般而言,相對較厚的非晶矽(amorphous silicon)層可能是較佳的,因為薄非晶矽層可允許更顯著的通道效應(channeling)和因此更深的植入態摻雜劑原子深度分佈(as-implanted dopant atoms depth distribution)和在超過非晶-結晶界面之末端(end-of-range,EOR)區中之更嚴重的植入後損傷。因此,更薄的非晶層可能會導致更深的接合深度,陡峭程度更低的摻雜分佈、摻雜劑的不充分活化以及退火後更多的末端缺陷,其皆表示在現代CMOS元件小型化中之主要障礙,尤其是對於源極-汲極延伸摻雜。可利用預先非晶化植入(pre-amorphization implant,PAI)製程來達成矽晶圓之非
晶化。至今,已在PAI製程中使用了矽、鍺或惰性氣體原子離子以及某些外來分子離子物質(exotic molecular ion species)。
為了進一步確保形成淺且陡的接合,通常執行低熱預算退火(low-thermal-budget anneal)作為較佳的植入後製程,其中晶圓的溫度在非常短的時間斜坡上升(ramp up)至較高的水準(例如,在5秒內上升到1000℃)。亦可采用雷射器或閃光燈進行植入後退火。然而,只使用無擴散退火(diffusion-less anneal)可能不足以防止所有經離子植入之摻雜劑向晶圓內更深處擴散。一種被稱作暫態增强擴散(transient enhanced diffusion,TED)之製程可使大量特定摻雜劑(例如,硼、磷)進一步擴散至晶圓內,該製程藉由在摻雜劑植入期間所產生的過量矽間隙而驅動。可能暫時地以數量級增加離子植入摻雜劑之擴散係數(diffusion coefficient)直至退火消除(anneal out)植入損傷。已發現諸如碳(C)和氟(F)之特定物質可藉由减小間隙與摻雜劑原子之間的相互作用而减輕TED效應。一種現有辦法採用叢集植入製程(cluster implantation process)來將碳置放於矽晶圓內以便减輕TED效應。然而,此辦法不僅需要專屬叢集植入設備(proprietary cluster implantation equipment),而且還需要外來專屬烴分子(exotic,proprietary hydrocarbon molecule)作為饋料。另一種辦法使用原子物質作為共同植入材料。
鑒於上文所述,需要提供形成淺接合的技術,其克服
上述不足和缺點。
本發明揭露了形成淺接合的技術。在一個特定示範性實施例中,該技術可實現為形成淺接合之方法。此方法可包括生成包括分子離子之離子束,分子離子基於由下列各物所構成的群族中選出的一種或多種物質:二鍺烷(Ge2
H6
)、氮化鍺(Ge3
N4
)、鍺-氟化合物(GeFn
,其中n=1、2或3)以及其它含鍺化合物。此方法亦可包括使離子束衝擊半導體晶圓以在摻雜劑被離子植入至半導體晶圓內之前非晶化半導體晶圓之至少一部份。
根據此特定示範性實施例之其它方面,此方法還可包括以下步驟:在半導體晶圓上執行第一離子植入以將摻雜劑置入至半導體晶圓之非晶化部份內,以及在半導體晶圓上執行第二離子植入以將一或多種共同植入物質置放於半導體晶圓中,利用分子離子來植入該或該等共同植入物質,分子離子基於由下列各物所構成的群族中選出的一或多種物質:CF、CF2
、Zn
Cx
Fy
以及Cx
Hy
Zn
,其中Z表示除了碳或氫之外的一或多種原子物質。
根據此特定示範性實施例之另外的方面,此方法還可包括以下步驟:在半導體晶圓上執行第一離子植入以將一或多種共同植入物質置放於半導體晶圓中,利用分子離子植入該或該等共同植入物質,分子離子是基於由下列各物所構成的群族中選出的一或多種物質:CF、CF2
、Zn
Cx
Fy
以及Cx
Hy
Zn
,其中Z表示除了碳或氫之外的一或多種原子
物質;以及,在半導體晶圓上執行第二離子植入以將摻雜劑置入於半導體晶圓之非晶化部份內。
根據此特定示範性實施例之額外方面,此方法還可包括在半導體晶圓上執行離子植入以將摻雜劑置入至半導體晶圓之非晶化部份內,其中,至少在離子植入開始時,半導體晶圓之溫度實質上低於室溫。半導體晶圓之溫度可低於攝氏零度。可在離子植入之前將半導體晶圓預冷至所要的溫度。或者,在離子植入之至少一部份期間,可將半導體晶圓之溫度維持在所要溫度。
在另一特定示範性實施例中,技術可被實現為形成淺接合之方法。此方法可包括生成包括分子離子之離子束,分子離子基於由下列各物所構成之群族中選出的一或多種物質:Zn
Cx
Fy
與Cx
Hy
Zn
,其中Z表示除了碳或氫之外的一或多種離子物質。此方法還可包括使離子束衝擊半導體晶圓以在摻雜劑被離子植入至半導體晶圓內之前非晶化半導體晶圓之至少一部份。
根據此特定示範性實施例之其它方面,藉由離子束之衝擊還可使由碳和氟所構成之群族中選出的一或多種共同植入物質置放於半導體晶圓之一或多個預定部位內。
根據此特定示範性實施例之另外的方面,此方法還可包括在半導體晶圓上執行低溫離子植入以將摻雜劑置入至半導體晶圓之非晶化部份內。
在又一特定示範性實施例中,該技術可實現為形成淺接合之裝置。該裝置可包括離子源總成(ion source
assembly),其用以生成包括分子離子之離子束,分子離子基於由下列各物所構成之群族中選出的一或多種物質:二鍺烷(Ge2
H6
)、氮化鍺(Ge3
N4
)、鍺-氟化合物(GeFn
,其中n=1、2或3)以及其它含鍺化合物。該裝置還可包括一或多個束線組件,其用以使離子束衝擊半導體晶圓以在將摻雜劑離子植入至半導體晶圓內之前非晶化半導體晶圓之至少一部份。
根據此特定示範性實施例之其它方面,該裝置還可經組態以在半導體晶圓上執行低溫離子植入以將摻雜劑置入至半導體晶圓之非晶化部份內。
在再一特定示範性實施例中,技術可被實現為形成淺接合之裝置。該裝置可包括離子源總成,其用以生成包括分子離子之離子束,分子離子基於由下列各物所構成之群族中選出的一或多個物質:Zn
Cx
Fy
與Cx
Hy
Zn
,其中Z表示除了碳或氫之外的一或多種離子物質。該裝置亦可包括一或多個束線組件以使離子束衝擊半導體晶圓以在將摻雜劑離子植入至半導體晶圓內之前非晶化半導體晶圓之至少一部份。
根據此特定示範性實施例之其它方面,藉由離子束之衝擊還可使由碳和氟構成的群族中選出的一或多種共同植入物質置放於半導體晶圓中之一或多個預定部位中。
根據此特定示範性實施例之另外的方面,該裝置還可經組態以在半導體晶圓上執行低溫離子植入來將摻雜劑置入至半導體晶圓之非晶化部份內。
在另外的特定示範性實施例中,技術可被實現為形成淺接合之方法。此方法可包括生成包括分子離子之離子束,分子離子基於一或多種含碳或含氟分子,含碳或含氟分子由下個各物所構成的群族中選出:CF、CF2
、Zn
Cx
Fy
以及Cx
Hy
Zn
,其中x、y和n各為正整數,且其中Z表示除了碳、氟或氫之外的一或多種原子物質。此方法還可包括使離子束衝擊半導體晶圓以將由碳和氟所構成之群族中選出的一或多種共同植入物質置放於半導體晶圓中的預定部位。
根據此特定示範性實施例之其它方面,此方法還可包括在半導體晶圓上執行低溫離子植入以將摻雜劑置入至半導體晶圓內。
現將參看如附圖所示之本發明的示範性實施例來更詳細地描述本揭露內容。雖然在下文中參看示範性實施例來描述本揭露內容,但應瞭解本揭露內容並不限於此。可使用本文之教示內容的熟習此項技術者將認識到如本文所述之本揭露內容之範疇內的額外的實施方式、修改和實施例,以及其它的使用領域,而且關於此等方面有效地利用本揭露內容。
本揭露內容之實施例可通過一種或多種輔助離子植入製程來减少離子植入摻雜劑之不當遷移。在摻雜劑植入之前,可利用自一或多種含鍺分子所生成的分子離子束來在目標晶圓上執行預先非晶化離子植入(pre-amorphization
implantation,PAI)。除了摻雜劑植入之外,含碳分子離子或含氟分子離子可經共同植入以將碳或氟物質置放到目標晶圓之所要部份內以减輕TED效應。在某些實施例中,若采用適當分子離子物質,PAI和共同植入步驟可合並為一個步驟。
本文所揭露之技術並不限於束線離子植入機,而是可適用於其它類型的離子植入機,諸如彼等用於電漿摻雜(plasma doping,PLAD)或電漿浸沒離子植入(plasma immersion ion implantation,PIII)之離子植入機。
參看圖2,其展示了說明根據本揭露內容之一實施例形成淺接合之示範性方法的流程圖。
在步驟202,可生成基於二鍺烷(digermane,Ge2
H6
)、氮化鍺(germanium nitride,Ge3
N4
)或其它類似的含鍺和/或含矽化合物之分子離子。此等分子離子的生成可發生於間熱式陰極(indirectly-heated cathode,IHC)離子源或另一種離子源中。然後可提取分子離子以形成分子離子束。Ge2
H6
和/或Ge3
N4
較佳地優於常用的氟化鍺(GeF4
),因為後者傾向於造成離子源維護問題或縮短離子源壽命。
在步驟204,利用分子離子束在目標晶圓(例如,結晶矽晶圓)上執行預先非晶化植入(PAI),分子離子束包含鍺或含矽物質。可控制分子離子束之能量和劑量以便非晶化目標晶圓之一部份。非晶化部份可自目標晶圓之表面延伸至預定深度。PAI步驟打破了目標晶圓之非晶化部份中之結晶結構,藉以减輕離子植入摻雜劑之通道效應。亦可使
用PAI步驟來控制目標晶圓中之損傷分佈,而損傷分佈可能會影響植入後擴散、摻雜劑活化和成品元件效能之其它方面,諸如漏電流(leakage current)。利用分子離子束之PAI可能優於利用原子離子束之PAI,此歸因於更高的生產率(由於更高的有效束電流(effective beam current)或更少的處理步驟的結果)、更快的損傷累積以及其它處理優勢。
在步驟206,可執行離子植入以將摻雜劑物質置入至目標晶圓內。摻雜劑植入可涉及一或多種摻雜劑物質和不同配方(recipe)(即,能量、劑量、角度)。摻雜劑通常被植入至目標晶圓之非晶化部份內。
視情况,在步驟210,可冷却或預冷目標晶圓以適應摻雜劑之低溫植入。舉例而言,可實施溫度管理系統(temperature management system)以在摻雜劑植入期間保持目標晶圓實質上低於室溫。選擇性地或此外,可在摻雜劑植入開始之前將目標晶圓和/或其壓板預冷至較低溫度。
在步驟208,可共同植入含碳分子或含氟分子以將碳或氟(“共同植入物質”)置放於目標晶圓內。較佳地,此等共同植入物質位於末端區域附近以形成EOR損傷與摻雜劑原子之間的障壁。因此經共同植入之共同植入物質可幫助防止TED效應向目標晶圓內更深處驅動摻雜劑。
含碳或含氟共同植入物質可包括(但不限於):CF、CF2
、Zn
Cx
Fy
以及Cx
Hy
Zn
,其中x、y和n各為正整數。其中,Z可表示單個原子或一組原子(諸如,N、Si、NH4
)。Cx
Hy
Zn
之實例可包括C9
H14
Si和C7
H17
N。選擇Z是因為其
對於整個離子植入製程具有益或因為其對於該製程並沒有作用。若Z對該製程造成任何損害,但若該損害可藉由其它優勢彌補,則仍可選擇Z。選擇特定Z元素/組合物的一個標準在於改良離子束生成,諸如允許在標準離子源中操作而不是需要專門的源極。
藉由與摻雜劑物質分開植入,可優化共同植入物質之分佈。舉例而言,碳硼烷(carborane,C2
B10
H12
)植入(利用500 eV之硼等效能量(boron equivalent energy))具有非常類似於硼分佈之植入態碳分佈(as-implanted carbon profile)。若執行更高能量(例如,6 keV)之第二碳植入以將碳置放於硼摻雜劑與自PAI步驟之EOR損傷之間,則可達成退火後硼分佈之進一步减少。
根據其它實施例,可有利地選擇包含共同植入物質與所要摻雜劑物質之饋料分子。舉例而言,在饋料Zn
Cx
Fy
或Cx
Hy
Zn
中,若Z原子或原子組經選擇包含諸如硼(B)之摻雜劑原子,則共同植入步驟亦將使摻雜劑原子同時植入,藉此可能减少摻雜劑植入步驟。
還應注意的是,步驟206並不是必須在步驟208之前。共同植入步驟(步驟208)可與摻雜劑植入步驟(步驟206)同時發生或在摻雜劑植入步驟(步驟206)之前發生,或根本就不發生。
在步驟212中,可執行目標晶圓之植入後處理。植入後處理通常涉及快速熱退火(rapid thermal anneal)或脈衝雷射退火(pulsed laser anneal)。植入後退火可修復由PAI步驟
所造成的晶體損傷且同時活化離子植入摻雜劑。
圖3展示了根據本揭露內容之一實施例形成淺接合之另一示範性方法的流程圖。
在步驟302,可生成基於Zn
Cx
Fy
、Cx
Hy
Zn
或其它類似分子(其中x、y和n各為正整數)之分子離子。饋料Zn
Cx
Fy
或Cx
Hy
Zn
可經選擇具有足夠的分子量且包含碳或氟物質中之至少一者。此等分子離子之生成可較佳地發生於習知離子源中,諸如IHC離子源,但亦可使用其它類型的離子源。Cx
Hy
Zn
的一個實例為碳硼烷(C2
B10
H12
)。然後可提取分子離子以形成分子離子束。
在步驟304,可利用分子離子束在目標晶圓(例如,結晶矽晶圓)上執行預先非晶化植入(PAI)。可控制分子離子束之能量和劑量使得目標晶圓之一部份被非晶化。此外,分子離子束可同時使碳或氟物質(“共同植入物質”)置放於目標晶圓中以便减輕TED效應。即,可將PAI步驟和共同植入步驟有效地組合為一個步驟(步驟304)。或者,可利用分子離子束之不同劑量、能量和/或角度以兩個或兩個以上的步驟執行PAI製程,以便可達成所要的共同植入物質分佈。
在步驟306,可執行離子植入以將摻雜劑物質置入至目標晶圓內。摻雜劑植入可涉及一種或多種摻雜劑物質和不同的配方(即,能量、劑量、角度)。摻雜劑通常被植入於目標晶圓之非晶化部份內。視情况,在步驟308,可冷却或預冷目標晶圓以適應摻雜劑之低溫植入。
最後,在步驟310,可執行目標晶圓之植入後處理以修復晶格損傷並活化摻雜劑。
圖4展示了在矽晶圓402經歷根據本揭露內容之一實施例之示範性處理步驟時矽晶圓402之一部份。圖4中的(a)展示了在進行任何離子植入之前之矽晶格402,其中矽晶格可能是完整的。矽晶圓402藉由圖案化光阻層401遮蔽以屏蔽無需摻雜的區域。圖4中的(b)展示了在預先非晶化植入(PAI)之後的矽晶圓402,(例如)藉由包含矽、鍺或如上文所述之其它分子化合物之分子離子束進行預先非晶化植入(PAI)。由於PAI步驟之結果,矽晶圓402之一部份可能已變得非晶化,產生非晶矽區域404。圖4中的(c)展示了在矽晶圓402進一步經歷摻雜劑植入步驟和碳共同植入步驟之後的矽晶圓402。如圖所示,摻雜劑植入步驟已將摻雜劑406置入至非晶矽區域404內,摻雜劑植入步驟可基於原子離子束或分子離子束。此外,基於上述的含碳共同植入物質的碳共同植入步驟已將含碳物質408置放於靠近非晶矽區域404與下面的矽晶圓402之結晶矽區域之間的邊界處。圖4中的(d)展示了在矽晶圓402經受植入後無擴散退火步驟之後的矽晶圓402。無擴散退火步驟將非晶矽區域404恢復到結晶態。摻雜劑406可變得活化並擴散。共同植入碳物質408可幫助限制摻雜劑406在淺表面區域(404)。
根據本揭露內容之實施例,如上文所述,許多烴物質(Cn
Hm
,其中n和m為正整數)可適用於PAI或共同植入製
程(或PAI加上共同植入之組合製程)。至今,自電子衝擊型離子源(electron-impact type ion source)所產生之某些外來專屬烴分子已被用作低能量碳植入之饋料。然而,更佳地,可在標準離子源(諸如IHC型、Bernas型、或Freeman型離子源)中生成所要的烴分子離子(Cn
Hm
)。或者可使用射頻(radio frequency,RF)或微波動力離子源(microwave powered ion source)來生成所要的烴分子離子。
如本文所描述之形成淺接合的技術可有利地與低溫離子植入技術組合。舉例而言,可預冷或持續地冷却目標晶圓使得在PAI、共同植入以及摻雜劑植入步驟中之任何步驟期間其溫度實質上保持低於室溫。
本揭露內容並不限於本文所描述之具體實施例之範疇。實際上,通過前文之描述與附圖,除了本文所描述之彼等內容之外的本揭露內容之各種實施例和修改對於一般熟習此項技術者將顯而易見。因此,此等其它實施例和修改預期屬於本揭露內容之範疇內。另外,雖然出於特定目的,在特定環境中特定實施例之情形下描述了本揭露內容,但本領域一般技術人員將認識到,其並不用於限制本揭露內容為該等實施例並且可出於多種目的在多種環境下有益地實施本揭露內容。因此,應考慮到如本文所描述之本揭露內容之全部範疇與精神來理解下文所陳述之申請專利範圍。
10‧‧‧離子束
100‧‧‧離子植入機系統
101‧‧‧電源
102‧‧‧離子源
104‧‧‧提取電極
106‧‧‧90°磁分析儀
108‧‧‧第一减速(D1)階段
110‧‧‧70°磁准直儀
112‧‧‧第二减速(D2)階段
114‧‧‧壓板
401‧‧‧經圖案化之光阻層
402‧‧‧矽晶圓
404‧‧‧非晶矽區域
406‧‧‧摻雜劑
408‧‧‧碳物質
圖1展示了傳統離子植入機系統。
圖2展示了說明根據本揭露內容之一實施例形成淺接合之示範性方法的流程圖。
圖3展示了根據本揭露內容之一實施例形成淺接合之另一示範性方法的流程圖。
圖4展示了根據本揭露內容之一實施例在矽晶圓經歷示範性處理步驟時矽晶圓的一部份。
401‧‧‧圖案化光阻層
402‧‧‧矽晶圓
404‧‧‧非晶矽區域
406‧‧‧摻雜劑
408‧‧‧碳物質
Claims (29)
- 一種形成淺接合之方法,包括:生成包括分子離子之離子束,所述分子離子基於由氮化鍺與GeFn 所構成群族中選出的一或多種物質,其中n=1、2或3;以及使所述離子束衝擊半導體晶圓。
- 如申請專利範圍第1項所述之形成淺接合之方法,其中所述離子束之衝擊在摻雜劑被離子植入至所述半導體晶圓內之前非晶化所述半導體晶圓之至少一部份。
- 如申請專利範圍第1項所述之形成淺接合之方法,還包括:在所述半導體晶圓上執行第一離子植入,以將摻雜劑置入至所述半導體晶圓內;以及在所述半導體晶圓上執行第二離子植入,以將一或多個共同植入物質置放於所述半導體晶圓中,利用所述分子離子來植入所述一或多個共同植入物質,所述分子離子基於由CF、CF2 、Zn Cx Fy 以及Cx Hy Zn 所構成之群族中選出之一或多種物質,其中Z表示除了碳或氫之外的一或多個原子物質。
- 如申請專利範圍第1項所述之形成淺接合之方法,還包括:在所述半導體晶圓上執行第一離子植入,以將一或多個共同植入物質置放於所述半導體晶圓中,利用所述分子離子來植入所述一或多個共同植入物質,所述分子離子基 於由CF、CF2 、Zn Cx Fy 以及Cx Hy Zn 所構成群族中選出之一或多種物質,其中Z表示除了碳或氫之外的一或多個原子物質;以及在所述半導體晶圓上執行第二離子植入,以將摻雜劑置入至所述半導體晶圓內。
- 如申請專利範圍第1項所述之形成淺接合之方法,還包括在所述半導體晶圓上執行離子植入,以將摻雜劑置入至所述半導體晶圓內,其中至少在所述離子植入開始時,所述半導體晶圓之溫度實質上低於室溫。
- 如申請專利範圍第5項所述之形成淺接合之方法,其中所述半導體晶圓之所述溫度低於攝氏零度。
- 如申請專利範圍第5項所述之形成淺接合之方法,其中在進行所述離子植入之前,預冷所述半導體晶圓之所述溫度至所要溫度。
- 如申請專利範圍第5項所述之形成淺接合之方法,其中在所述離子植入之至少一部份期間將所述半導體晶圓維持在所要溫度範圍。
- 如申請專利範圍第1項所述之形成淺接合之方法,其中在所述離子束之衝擊期間,所述半導體晶圓在實質上低於室溫之溫度範圍。
- 一種形成淺接合之方法,包括:生成包括分子離子之離子束,所述分子離子基於Zn Cx Fy ,其中Z表示除了碳或氫之外的一或多個原子物質;以及 使所述離子束衝擊半導體晶圓。
- 如申請專利範圍第10項所述之形成淺接合之方法,其中所述離子束之衝擊在摻雜劑被離子植入至所述半導體晶圓內之前非晶化所述半導體晶圓之至少一部份。
- 如申請專利範圍第11項所述之形成淺接合之方法,其中所述離子束之衝擊還使由碳和氟所構成的群族中選出之一或多個共同植入物質置放於所述半導體晶圓中之一或多個預定部位中。
- 如申請專利範圍第11項所述之形成淺接合之方法,還包括在所述半導體晶圓上執行低溫離子植入,以將所述摻雜劑置入至所述半導體晶圓之非晶化部份內。
- 如申請專利範圍第10項所述之形成淺接合之方法,其中所述離子束之衝擊使一或多個共同植入物質置放於所述半導體晶圓內。
- 如申請專利範圍第14項所述之形成淺接合之方法,其中所述一或多個共同植入物質是由碳和氟所構成的群族中選出的。
- 如申請專利範圍第15項所述之形成淺接合之方法,其中所述一或多個共同植入物質被置放於所述半導體晶圓內的末端區域中。
- 如申請專利範圍第10項所述之形成淺接合之方法,在所述離子束之衝擊期間,所述半導體晶圓在實質上低於室溫之溫度範圍。
- 一種形成淺接合之裝置,包括: 離子源總成,用以生成包括分子離子之離子束,所述分子離子基於由氮化鍺與GeFn ,其中n=1、2或3;以及一或多個組件,用以使所述離子束衝擊半導體晶圓。
- 如申請專利範圍第18項所述之形成淺接合之裝置,其中所述離子束之衝擊在摻雜劑被離子植入至所述半導體晶圓內之前非晶化所述半導體晶圓之至少一部份。
- 如申請專利範圍第18項所述之形成淺接合之裝置,還經組態以在所述離子束之衝擊期間維持所述半導體晶圓在實質上低於室溫之溫度範圍。
- 如申請專利範圍第19項所述之形成淺接合之裝置,還經組態以在所述半導體晶圓上執行低溫離子植入,以將摻雜劑置入於所述半導體晶圓之非晶化部份內。
- 一種形成淺接合之裝置,包括:離子源總成,用以生成包括分子離子之離子束,所述分子離子基於Zn Cx Fy ,其中Z表示除了碳或氫之外的一或多個原子物質;以及一或多個組件,用以使所述離子束衝擊半導體晶圓。
- 如申請專利範圍第22項所述之形成淺接合之裝置,其中所述離子束之衝擊還使由碳和氟所構成群族中選出之一或多個共同植入物質置放於所述半導體晶圓中之一或多個預定部位中。
- 如申請專利範圍第22項所述之形成淺接合之裝置,其中所述離子束之衝擊還使一或多個共同植入物質置放於所述半導體晶圓內。
- 如申請專利範圍第24項所述之形成淺接合之裝置,其中所述一或多個共同植入物質是由碳和氟所構成的群族中選出的。
- 如申請專利範圍第25項所述之形成淺接合之裝置,其中所述一或多個共同植入物質被置放於所述半導體晶圓內的末端區域中。
- 如申請專利範圍第22項所述之形成淺接合之裝置,其中所述離子束之衝擊在摻雜劑被離子植入至所述半導體晶圓內之前非晶化所述半導體晶圓之至少一部份。
- 如申請專利範圍第22項所述之形成淺接合之裝置,還經組態以在所述離子束之衝擊期間將所述半導體晶圓維持在實質上低於室溫之溫度範圍。
- 如申請專利範圍第22項所述之形成淺接合之裝置,還經組態以在所述半導體晶圓上執行低溫離子植入,以將摻雜劑置入至所述半導體晶圓之非晶化部份內。
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US7935942B2 (en) * | 2006-08-15 | 2011-05-03 | Varian Semiconductor Equipment Associates, Inc. | Technique for low-temperature ion implantation |
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2007
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- 2008-04-04 CN CN2008800152420A patent/CN101681820B/zh active Active
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US7642150B2 (en) | 2010-01-05 |
KR101492533B1 (ko) | 2015-02-12 |
JP2010524263A (ja) | 2010-07-15 |
CN101681820A (zh) | 2010-03-24 |
US20080108208A1 (en) | 2008-05-08 |
CN101681820B (zh) | 2013-01-09 |
TW200847245A (en) | 2008-12-01 |
KR20100015939A (ko) | 2010-02-12 |
WO2008124554A1 (en) | 2008-10-16 |
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