TWI433294B - Method and apparatus for manufacturing three - dimensional integrated circuit - Google Patents

Method and apparatus for manufacturing three - dimensional integrated circuit Download PDF

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Publication number
TWI433294B
TWI433294B TW099106838A TW99106838A TWI433294B TW I433294 B TWI433294 B TW I433294B TW 099106838 A TW099106838 A TW 099106838A TW 99106838 A TW99106838 A TW 99106838A TW I433294 B TWI433294 B TW I433294B
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Taiwan
Prior art keywords
wafers
substrate
temporary
transfer
regions
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TW099106838A
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English (en)
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TW201108386A (en
Inventor
Masahiko Sugiyama
Mitsumasa Koyanagi
Takafumi Fukushima
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Tokyo Electron Ltd
Univ Tohoku
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Publication of TW201108386A publication Critical patent/TW201108386A/zh
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Publication of TWI433294B publication Critical patent/TWI433294B/zh

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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Description

三維積體電路之製造方法及裝置
本發明係關於一種將晶片層積於支撐基板所形成之三維積體電路之製造方法以及裝置。
關於積體電路之積集度，已知有預測積集度將以1年成長2倍的速度增加的摩爾定律。半導體之微細加工技術的進步則支撐著摩爾定律。但是，現今微細加工技術已進展到奈米的世界，想要如同過去般之速度來讓微細加工技術產生進步便變得困難。因此，亦有人認為摩爾定律在下一個世代或下下一個世代便會到達極限。隨著微細加工技術進步的困難度，關於三維積體電路之技術便開始受到注目。
如圖1(a)所示，習知系統LSI1係在一個晶片2上形成有微處理器、邏輯電路、各種記憶體、輸出入介面電路、通訊控制用電路等機能區塊3的二維積體電路。相對地，如圖1(b)所示，三維積體電路4係將系統LSI1之各機能區塊3分割，而層積呈三維狀態的積體電路。層積機能區塊3時，各層晶片5係薄膜化至例如數μm數百μm左右。該三維積體電路4係具有可縮短配線長度、可將元件個數高密度化、可將訊號處理速度高速化、可降低消耗電力等優點。其已應用在CMOS圖像感測器，今後，亦預計將導入至NAND、DRAM、邏輯等積體電路。
關於用以實現三維積體電路的技術，已知有於晶圓上交替反複地交互進行FEOL(Front End Of Line)步驟與BEOL(Back End Of Line)步驟的方法、將晶片層積至其他晶片的方法(以下稱作Chip on Chip法)，將晶圓相互貼合以進行層積的方法(以下稱作Wafer on wafer法)、以及於晶圓上層積複數個晶片的方法(以下稱作Chip on wafer法)。
前述反複進行FEOL與BEOL的方法係反複地交互反複地進行於晶圓上形成電晶體等元件的FEOL、以及以配線將該等元件相互接續的BEOL。藉由反複進行前述步驟，可於晶圓上形成三維積體電路。但是，該方法會有於BEOL之後難以進行FEOL的步驟上之問題。又，當反複進行之FEOL與BEOL中任一步驟產生缺陷時，其整體便會變成不良品，而會有良率下降的問題。
前述Chip on Chip法中，係不使用晶圓而將由晶圓切割出的晶片層積在其他晶片。由於能僅針對被稱作KGD(Known Good Die)之良品的晶片進行層積，故可提高良率。KGD係可保證特性與信賴性的晶粒(die=chip)。但是，由於是進行晶片等級之層積，因此會有製造產能明顯下降的問題。
前述Wafer on wafer法係將已形成有元件之晶圓進行晶圓等級的層積。即，能以晶圓尺寸來進行製程，故可提高產能。但是，由於晶圓包含有不良品之晶片(晶圓中之晶片的良率並非100%)，因此當晶圓層積越多次，則生產出不良品的可能性便越高。其結果便會造成良率下降。
前述Chip on wafer法係在晶圓上排列有晶片，且於晶圓上之晶片上再層積其他晶片。最後於晶圓上形成多數個三維積體電路。與Chip on Chip法相同地，能僅針對良品之晶片進行層積，故可提高良率。但是，藉由使用晶圓雖然能相較於Chip on Chip法而提高產能，然而於晶圓上排列晶片時，數千片晶片必需要以機器人一片一片地挾起並定位至晶圓上，故無法提高太多產能。而且，以機械性地來定位晶片，即使定位精度良好也僅為1μm左右，故亦無法提高太多定位精度。
為了解決Chip on wafer法之前述問題，本發明人係提出使用自我組織化功能來將晶片定位至支撐基板的三維積體電路之製造方法(參考專利文獻1)。該三維積體電路之製造方法係利用水的表面張力來讓多數個晶片自動地定位至轉印用基板。接著，將暫時接著有多數個晶片之轉印用基板反轉，一口氣將多數個晶片從轉印用基板移轉至支撐基板。
具體說明，如圖2所示，於晶片6內面形成有因表面張力而膨漲呈凸透鏡狀的水膜8(S1)。於轉印用基板7之暫時接著區域7a亦形成因表面張力而膨漲呈凸透鏡狀的水膜8(S1)。其次，使用晶片接合器(bonder)來將晶片6以概略之定位精度載置在轉印用基板7之暫時接著區域7a(S2)。如此一來，可藉由水之表面張力來讓晶片6自動地定位至轉印用基板7之暫時接著區域7a(S3)。其次，使用押抵板9將晶片6押抵至轉印用基板7。藉此，讓晶片6與轉印用基板7之間的微細間隙處留住水，同時將不必要之水排出(S4)。藉由存在於晶片6與轉印用基板7之間的間隙處之水的吸著力，將晶片6暫時接著於轉印用基板7。其次，將暫時接著有多數個晶片6之轉印用基板7進行反轉(S5)。此時，晶片6會因為水之吸著力而接著於轉印用基板7。其次，讓轉印用基板7朝向支撐基板10接近，將晶片6正式接著於支撐基板10(S6)。將晶片6正式接著於支撐基板時，係藉由加熱晶片6來將晶片6與轉印用基板7之間的水蒸發。因此，可從轉印用基板7將多數個晶片6剝離(S7)。藉由以上，便可將暫時接著於轉印用基板7之晶片6移轉至支撐基板10。
專利文獻1：日本國內公表WO2006/77739(參照段落0149~0164)。
前述使用了自我組織化功能之三維積體電路的製造方法中，如果能將多數個晶片正確地定位於轉印用基板，便能如Wafer on Wafer法中晶圓之相同方式來處理轉印用基板，而能以晶圓尺寸來進行製程。因此，能如同Wafer on wafer法般地提高產能。另一方面，如果無法將多數個晶片正確地定位於轉印用基板，便無法如Wafer on Wafer法中晶圓之相同方式來處理轉印用基板。因此，雖然是「將晶片暫時接著於轉印用基板」，仍需使得該等不會產生位置偏移般地進行接著。
但是，前述三維積體電路之製造方法中，晶片與轉印用基板係藉由存在於該等之間的間隙處之水的吸著力來進行暫時接著。藉由水之吸著力來進行晶片與轉印用基板之接著時，其接著力並不充足。例如將轉印用基板反轉或搬送時，有可能會使得被正確地定位在轉印用基板處之晶片產生位置偏移。但是，將晶片過度強力地固定於轉印用基板之情況，反倒是在欲將晶片移轉至支撐基板時，會導致晶片無法從轉印用基板處剝離。
於是，本發明之目的係提供一種能不會產生位置偏移般地將晶片暫時接著至轉印用基板，又，可在欲將晶片移轉至支撐基板時，能從轉印用基板確實地將晶片剝離的三維積體電路之製造方法及裝置。
為了解決前述問題，本發明一樣態的三維積體電路之製造方法，係將晶片層積於支撐基板以形成三維積體電路，並具備有下列步驟：將液體塗佈在轉印用基板所形成之複數個暫時接著區域；於各別分離至該複數個暫時接著區域的複數個液滴上，將複數個晶片釋放，利用液體之表面張力來讓各晶片定位至各暫時接著區域；讓於該各晶片與該各暫時接著區域之間的液體蒸發，藉以使得該各晶片暫時接著至該各暫時接著區域；讓暫時接著有該複數個晶片的該轉印用基板接近至支撐基板，將該複數個晶片中暫時接著至該轉印用基板之面的相反側，接著至該支撐基板之複數個正式接著區域處抑或層積於複數個正式接著區域的複數個層積晶片處，使得該各晶片與該支撐基板抑或該支撐基板上之各層積晶片之間的接著力會較該各晶片與該轉印用基板之間的接著力更強的方式來批次式地進行正式接著；以及藉由將該轉印用基板自該支撐基板處分離，在該複數個晶片仍接著至該支撐基板處抑或該支撐基板上之該複數個層積晶片處之情況下，來使得該複數個晶片自該轉印用基板處剝離。
本發明之其他樣態的三維積體電路之製造裝置，係將晶片層積於支撐基板以形成三維積體電路，其具備有：形成複數個暫時接著區域的轉印用基板；以及將液體塗佈至轉印用基板所形成之複數個暫時接著區域的液體塗佈機構；其中，於各別分離至該複數個暫時接著區域的複數個液滴上，將複數個晶片釋放，利用液體之表面張力來讓各晶片定位至各暫時接著區域；讓於該各晶片與該各暫時接著區域之間的液體蒸發，藉以使得該各晶片暫時接著至該各暫時接著區域；讓暫時接著有該複數個晶片的該轉印用基板接近至支撐基板，將該複數個晶片中暫時接著至該轉印用基板之面的相反側，接著至該支撐基板之複數個正式接著區域處抑或層積於複數個正式接著區域的複數個層積晶片處，使得該各晶片與該支撐基板抑或該支撐基板上之各層積晶片之間的接著力會較該各晶片與該轉印用基板之間的接著力更強的方式來批次式地進行正式接著；以及藉由將該轉印用基板自該支撐基板處分離，在該複數個晶片仍接著至該支撐基板處抑或該支撐基板上之該複數個層積晶片處之情況下，來使得該複數個晶片自該轉印用基板處剝離。
將晶片暫時接著於轉印用基板時，藉由將存在於晶片與轉印用基板之間處的液體蒸發，可讓晶片與轉印用基板之間固體接著。因此，能以不會產生位置偏移般地將晶片暫時接著於轉印用基板。又，使得晶片與支撐基板(或層積晶片)之間的接著力較晶片與轉印用基板之間的接著力更強，藉此，將晶片從轉印用基板移轉至支撐基板(或層積晶片)時，便能將晶片確實地從轉印用基板剝離。
以下，根據添附圖式來詳細地說明本發明之一實施形態的三維積體電路之製造方法。構成三維積體電路之支撐基板係沿縱向層積有晶片。首先，針對層積於支撐基板上的晶片進行說明。晶片係形成有微處理器、邏輯電路等的IC。為了讓沿縱向層積之複數個晶片形成電連接，晶片形成有TSV(Through Silicon Via；矽穿孔)。
如圖3所示，於晶片形成TSV之製程可分為三種類別。如圖3(a)所示之Via First方式、如圖3(b)所示之Via Last(front)方式、以及如圖3(c)所示之Via Last(back)方式等三種。
如圖3(a)所示，所謂Via First方式係在進行IC製造之前置工程以前便形成TSV。首先，於矽基板11內部形成有從其表面側至內壁面皆覆蓋有絕緣膜(SiO2 膜)的溝槽12(a1)。該溝槽12並未貫穿矽基板11，而係於途中便停止。溝槽12內部係充填多晶矽、鎢等導電性材料而形成有導電性栓塞13(a1)。其次，於矽基板11表面或內部形成CMOS等半導體元件或積體電路14(a2)。其次，以絕緣膜(SiO2 膜15)來覆蓋形成有半導體元件或積體電路14之矽基板11表面(a2)。最後，從內面側切削矽基板11，以使得導電性栓塞13從矽基板11之內面側露出(a3)。於矽基板11表面便形成有會連接至導電性栓塞13的凸塊電極16(a3)。
如3(b)所示，所謂Via Lasy(front)方式係先在矽基板11形成半導體元件或積體電路14(b1)，然後再形成TSV(b2、b3)。所謂Via First方式則係形成TSV17之順序不同。此方式中，TSV17係從矽基板11表面側所形成(b2)。又，此方式中，亦會將矽基板11削薄(b3)。
如圖3(c)所示，Via Last(back)方式中，與Via Last(front)方式相同地，係先於矽基板11形成半導體元件或積體電路14(c1)。將矽基板11削薄，並將矽基板11貼合於玻璃基板18後，從內面側形成TSV17(c2、c3)。與Via Last(front)方式之差異點在於TSV17係從矽基板11表面側形成、亦或從內面側形成。
圖4係顯示晶片20之剖面圖的一範例。於矽基板21上形成有閘極電極21a，並於閘極電極21a之兩側形成有源極區域21b及汲極區域21c。又，於矽基板21上係埋設閘極電極21a般地形成有由SiO2 所組成的絕緣層22。絕緣層22之表層部分則形成有由鎳等所組成的配線層及由金等所組成的配線層24(凸塊電極)。絕緣層22內部係埋設般地形成有由鋁等所組成之追加配線層23，以使得閘極電極21a與配線層23及24之間形成電連接。又，於矽基板21及絕緣層22係形成有連通至追加配線層22a的穿孔(via)，且覆蓋該穿孔之側壁般地形成有由SiO2 膜所組成的絕緣膜25。接著，介設有絕緣膜25般地形成電連接至追加配線層22a的導電性栓塞26。
另外，三維積體電路所使用之晶片20的尺寸會根據CMOS、記憶體等用途而不同，但例如可為5mm×5mm、10mm×10mm等。晶片之厚度為例如20μm～100μm。TSV之孔徑為例如0.5μm～100μm。
圖5係暫時接著有多數個晶片20之轉印用基板(載體基板31)的立體圖。多數個晶片20係於定位‧暫時接著在載體基板31後，轉印至支撐基板。於載體基板31表面處，係於一側面形成有複數個暫時接著區域31a，以使得多數個晶片20能排列呈特定配置之鏡像。一個暫時接著區域31a係暫時接著有一個晶片20。載體基板31係可使用矽等半導體晶圓、玻璃基板等。只要是具有能保持多數個晶片20之剛性者，亦可使用絕緣體或導電體。
暫時接著區域31a係形成為矩形。暫時接著區域31a之大小與形狀係與暫時接著於其上之晶片20的大小與形狀幾乎一致。暫時接著區域31a係由具有親水性之親水膜所劃分形成。親水性之膜可由例如SiO2 、Si3 N4 、鋁與氧化鋁之雙層膜(Al/Al2 O3 )、鉭與氧化鉭之雙層膜(Ta/Ta2 O5 )等所形成。
暫時接著區域31a周圍係由格子狀之疏水膜或疏水材料31b所包圍。疏水膜或疏水材料31b之材料係可使用具有撥水性質之材料，例如，單晶矽、多結晶矽、非晶矽、氟系樹脂、矽樹脂、鐵氟龍(註冊商標)樹脂、聚醯亞胺樹脂、光阻、蠟、BCB(Benzocyclobutene)等。
圖6係顯示於載體基板31形成親水膜31a及疏水膜31b之步驟圖的一範例。首先，於矽基板32形成SiO2 膜33(S1)。SiO2 膜33係可由熱氧化法、CVD(Chemical Vapor Deposition)法、濺鍍法等習知方法所形成。其次，於SiO2 膜33上塗佈作為感光性樹脂的光阻34(S2)。其次，將塗佈有光阻34之矽基板32安裝至曝光裝置，轉印出遮罩圖樣35。針對經曝光後之光阻34進行顯影處理(S3)。其次，依光阻34圖樣般地蝕刻SiO2 膜33(S4)。蝕刻可為乾蝕刻亦可為溼蝕刻。將光阻34剝離後，便可獲得形成有對應於暫時接著區域之圖樣的SiO2 膜33(S5)。其次，於SiO2 膜33表面形成疏水膜36(S6)，疏水膜36與光阻34相同地，可藉由將液狀疏水材料滴下至矽基板32後，使用旋轉塗佈機來將矽基板32高速迴轉的方式來形成。其次，於疏水膜36上堆積硬遮罩37(S7)。與光阻34相同地，疏水膜36會因曝光、顯影處理而溶解。為了防止疏水膜36受溶解而堆積有硬遮罩37。其次，於硬遮罩37上塗佈光阻39(S8)。其次，如圖7所示，使用遮罩圖樣41來針對光阻39進行曝光、顯影處理(S9)。其次，蝕刻硬遮罩37(S10)。其次，蝕刻SiO2 膜33上的疏水膜36(S11)。疏水膜36亦可藉由氧電漿等以進行灰化處理(Ashing)。最後將光阻39剝離，以去除硬遮罩37(S12)。
藉由以上步驟，可於矩形狀親水膜31a周圍形成有框狀的疏水膜31b。藉由於親水膜31a周圍形成疏水膜，而明確地區分親水部分與疏水部分，亦可明確親水部分之邊緣。因此，可使用水之表面張力來高精度地進行晶片20定位。
另外，於矽基板32形成SiO2 膜後，於SiO2 膜33上形成疏水膜36，亦可僅針對疏水膜36進行圖樣成形。此時，SiO2 膜33與疏水膜36之間會形成若干之段差，疏水膜36會若干地高於SiO2 膜33。
其他亦可藉由剝離法(lift off)來形成疏水膜36。即，圖6之S4中，於蝕刻SiO2 膜33後，未將光阻34去除，而於光阻34上形成疏水膜36，然後，以顯影液將光阻34溶出，藉此，可同時地去除光阻34與光阻34上之疏水膜36。
再者，亦可於載體基板31使用疏水材料之單晶矽，而於疏水材料表面僅形成有親水膜。
說明於載體基板31上針對多數個晶片進行定位之步驟。如圖8所示，於載體基板31之複數個親水膜31a上塗佈水後，便會於複數個親水膜31a上形成分離後的水滴40(S2)。
塗佈水之步驟係可採用讓液體直接接觸至載體基板31的接觸法、抑或使用噴嘴來將水噴灑至載體基板31的噴霧法。作為接觸法，可採用將載體基板31浸入至容器所盛之水中後將載體基板31從容器取出的方法、讓載體基板31面朝下方地接觸至容器所盛之水後將載體基板31抬起的方法、抑或於載體基板31上流通水的方法。作為噴霧法，可採用設置有面向載體基板31之噴嘴並從噴嘴朝向載體基板31噴灑水的方法。亦可從多數個噴嘴朝載體基板31整體表面噴灑水，抑或可從對應於親水膜31a所設置之噴嘴僅朝向親水膜31a噴灑水。此時，亦可對應親水膜31a之面積以控制噴灑的水量。
對應於親水膜31a之面積而存在有最適合用以定位的水量。載體基板31之複數個親水膜31a中，於面積相對較小之親水膜31a係塗佈有相對較少量的水，於面積相對較大之親水膜31a則塗佈有相對較多量的水。無論於接觸法或噴霧法中，皆可在欲將水塗佈至載體基板31之一面時自動地將水量調至最適當化。
如圖8所示，將水塗佈至載體基板31上時，水會擴展至親水膜31a之整體表面，而形成覆蓋親水膜31a整體表面的水滴40。該水滴40會因為其表面張力而彎曲呈凸狀。於親水膜31a周圍係藉由疏水膜31b所包圍，故水不會擴展至疏水膜31b處。
於晶片20內面預先形成具有親水性之SiO2 膜20a。其次，在分離至各親水膜31a之水滴40上將複數個晶片20釋放(S3)。如此一來，藉由水之表面張力可讓釋放至水滴40上的晶片20自動地定位至親水膜31a處。此步驟，例如可使用晶片接合器來一個一個地針對各晶片20進行釋放，抑或使用能一口氣保持多數個晶片20之保持托盤來同時將多數個晶片20釋放至多數個水滴40上。
圖9係顯示使用批次保持托盤之情況下的概略圖。使用批次保持托盤42來將多數個晶片20同時地釋放至多數個水滴40上時，相對於親水膜31a朝水平方向偏移之晶片20會因為水之表面張力而自動地定位至親水膜31a上的正確位置處。於水滴40上將晶片20釋放時，無需將晶片20定位至親水膜31a上之正確位置處，只需概略之定位即可。
再來，如圖8所示，其次，將晶片20內面與載體基板31之親水膜31a之間的水蒸發(S4)。可藉由加熱或於真空環境使水蒸發，抑或於常溫下花費特定時間使其蒸發。
當水蒸發時，晶片20與載體基板31便會固體接著。於水中，亦可添加有能讓晶片20之SiO2 膜20a及載體基板31之親水膜31a活性化的添加劑。該實施形態中，於晶片20之SiO2 膜20a及載體基板31之親水膜31a(SiO2 膜)處形成親水基(OH基)，而添加有能讓該等親水基相互結合的氫氟酸。只要能讓晶片20之SiO2 膜20a及載體基板31之親水膜31a活性化者，不限定為氫氟酸，而亦可添加氨、鹽酸與過氧化氫水與水所混合之鹽酸過水。
利用表面張力來進行定位之液體亦可使用其他無機或有機液體來替代水。例如，可使用甘油、酮、醇、S0G(Spin-On-Glass)材料等的液體。亦可使用液體狀態之樹脂，抑或使用液體狀態之樹脂與水的混合液。但是，需具有能進行定位之程度的低粘度。
當於載體基板31上將多數個晶片20定位後，便進行將多數個晶片20從載體基板31移轉至支撐基板50的轉印步驟。如圖8所示，將暫時接著有複數個晶片20之載體基板31反轉，朝向支撐基板50下降(S5)。亦可無需反轉載體基板31，而係將反轉後之支撐基板50朝向載體基板31下降。
接著，使得暫時接著於載體基板31之多數個晶片20中，暫時接著於載體基板31之面的相反側能一口氣地正式接著至支撐基板50之正式接著區域50a(S6)。於支撐基板50上已層積有晶片20之情況，晶片20便會接著至層積於支撐基板50上的層積晶片。此處，晶片20與支撐基板50(或層積晶片)之間的接著力係調整至較晶片20與載體基板31之間的接著力更強。
其次，藉由讓載體基板31從支撐基板50處分離，而在多數個晶片20接著至支撐基板50之情況下，可讓多數個晶片20從載體基板31處剝離(S7)。反複進行前述之轉印步驟，藉此可於支撐基板50上沿縱向層積複數個晶片20。於支撐基板50上層積複數個晶片20之後，只需進行晶圓切割便可獲得三維積體電路。
支撐基板50係可使用矽等半導體晶圓、玻璃基板等。只要具有能保持多數個晶片20之剛性者，亦可使用絕緣體或導電體。支撐基板50表面可形成SiO2 膜以作為正式接著區域50a。
能以下述方法來使得晶片20與載體基板31之間的接著力，較晶片20與支撐基板50之間的接著力更弱。如圖10所示，只要讓載體基板31之親水膜31a(SiO2 膜)與晶片20之SiO2 膜20a之間的接觸面積，較平行於親水膜31a之平面內之晶片20的剖面積更小，便可使得晶片20與載體基板31之間的接著力變弱。只要在載體基板31之親水膜31a處點狀設置有複數個支柱51，便可使得晶片20與載體基板31之間的接觸面積變小。該支柱51可由習知之微影技術所形成。亦可藉由於親水膜31a表面形成微小段差以縮小接觸面積的方式，來替代支柱51。
又，藉由讓支撐基板50之SiO2 膜的表面粗糙度，較載體基板31之親水膜31a的表面粗糙度更小，能使得正式接著之接著力較暫時接著之接著力更強。使用CMP(化學機械研磨)裝置，來讓支撐基板50之正式接著區域50a之表面粗糙度達例如1nm以下時，便可使得正式接著之接著力變得極為強固。另一方面，讓載體基板31之親水膜31a之表面粗糙度變粗時，便可使得暫時接著之接著力變弱。親水膜31a之SiO2 膜亦可藉由蝕刻來化學性地變得粗糙，抑或以研磨石等來機械性地變得粗糙。
再者，亦可於能剝離之犧牲層上形成載體基板31之親水膜31a。接著，亦可將晶片20從載體基板31處剝離時，在載體基版31之親水膜31a接著至晶片20的狀態下以犧牲層為分界，來將晶片20從載體基板31處剝離。犧牲層可使用會因注入藥液而溶解之樹脂或光剝離樹脂。
另外，關於晶片20與支撐基板50之間的正式接著，除了前述將晶片20之SiO2 膜20a與支撐基板50之SiO2 膜進行接著之情況外，亦可為將晶片20之電極(例如凸塊電極)與支撐基板50之電極(例如凸塊電極)進行接著之情況、以及合併使用該等方式之情況。於支撐基板50形成有除了凸塊電極之外的虛設電極時，便可增強支撐基板50與晶片20之間的正式接著之接著力。作為電極用之導電性材料，可適用例如，銦(In)與金(Au)之雙層構造(In/Au)、錫(Sn)與銀(Ag)之雙層構造(Sn/Ag)、銅(Cu)之單層構造抑或鎢(W)之單層構造。將凸塊電極相互接著之情況，亦可施加壓力或提高溫度等。
關於晶片20與層積晶片之正式接著，包含有將晶片20之SiO2 膜與層積晶片之SiO2 膜進行接著之情況、將晶片20之電極(例如凸塊電極)與層積晶片之電極(例如凸塊電極)進行接著之情況、以及合併使用該等方式之情況。
關於晶片20與載體基板31之暫時接著，除了前述將晶片20之SiO2 膜20a與載體基板31之親水膜31a(SiO2 膜)進行接著之情況外，亦包含有將晶片20之電極(例如凸塊電極)與載體基板31之電極(例如凸塊電極)進行接著之情況、以及合併使用該等方式之情況。
圖11及圖12係顯示於暫時接著時，將晶片20之凸塊電極20b與載體基板31之親水膜31a內之凸塊電極53進行暫時接著的範例。讓晶片20與載體基板31之間的水蒸發而進行自我校準後，決定晶片20之凸塊電極20b與載體基板31之凸塊電極53之間的位置，便可將該等進行暫時接著。
圖13係顯示將載體基板31之SiO2 膜與晶片20之SiO2 膜進行暫時接著之範例，晶片20即使形成有凸塊電極20b，只要在載體基板31形成有對應於凸塊電極20b之凹部55，便可讓載體基板31之SiO2 膜與晶片20之SiO2 膜進行暫時接著。同樣地，只要在支撐基板50亦形成有對應於晶片20之凸塊電極20b的凹部56，便可將支撐基板50之SiO2 膜與晶片20之SiO2 膜進行正式接著。
圖14係顯示於晶片20內面及載體基板31之親水膜31a形成有會相互囓合之擋塊52a、52b的範例。利用水之表面張力來針對晶片20與載體基板31之暫時接著區域之間進行定位時，如晶片20彎曲便會有無法將晶片正確地定位至親水膜31a之虞。依此範例，隨著水之蒸發，晶片20之擋塊52a便會進入至載體基板31之擋塊52b中，擋塊52a、52b會相互囓合以防止晶片20於親水膜31a平面內產生位置偏移。擋塊52a、52b之剖面形狀可形成矩形狀，亦可形成當晶片20逐漸靠近載體基板31則可將晶片20定位般的錐形狀。擋塊52a、52b可藉由習知之微影技術所製成。
圖15係顯示於支撐基板50上排列有一層晶片20之範例。各晶片20係具有處理器、邏輯、記憶體等功能。本範例中，複數個晶片20係於支撐基板50上呈平面狀排列，但並未於縱向進行層積。亦可如本範例般地於支撐基板50上排列有一層之晶片20。
另外，本發明並不限定於前述實施形態，在不改變本發明宗旨之範圍可進行各樣變更。例如，亦可藉由針對矽基板進行氧化處理之方式來形成SiO2 膜，以取代於載體基板表面進行微影來形成SiO2 膜之方式。氧化處理亦可使用H2 O2 處理、及使用了臭氧之氧化處理。又，亦可不針對矽基板進行氧化處理，而以自然氧化之方式來形成SiO2 膜。
將晶片定位‧暫時接著至載體基板之暫時接著區域後，亦可使用押抵板來將晶片押抵至載體基板。如使用押抵板，即使是當晶片彎曲之情況亦可將晶片之整體表面暫時接著至載體基板。
將晶片層積至支撐基板的層積晶片時，亦可於晶片與層積晶片之間設置有電氣絕緣性的接著劑，藉由該電氣絕緣性之接著劑來將晶片與層積晶片進行接著。
在將晶片貼合至支撐基板後，亦可於晶片處形成凸塊電極，抑或將預先形成有凸塊電極之晶片層積至支撐基板。
本說明書係根據2009年3月23日提出申請之日本專利申請2009-070769號。並包含有其全部內容。
1．．．LSI
2．．．晶片
3．．．機能區塊
4．．．積體電路
5．．．晶片
6．．．晶片
7．．．基板
7a．．．暫時接著區域
8．．．水膜
9．．．押抵板
10．．．支撐基板
11．．．矽基板
12．．．溝槽
13．．．栓塞
14．．．積體電路
15．．．SiO2 膜
16．．．電極
17．．．TSV
18．．．玻璃基板
20．．．晶片
20a．．．SiO2 膜
20b．．．SiO2 膜
21．．．矽基板
21a．．．閘極電極
21b．．．源極區域
21c．．．汲極區域
22．．．絕緣層
22a．．．配線層
23、24．．．配線層
25．．．絕緣膜
26．．．栓塞
31．．．載體基板
31a．．．親水膜
31b．．．疏水膜
32．．．矽基板
33．．．SiO2 膜
34．．．光阻
35．．．遮罩圖樣
36．．．疏水膜
37．．．硬遮罩
39．．．光阻
40．．．水滴
41．．．遮罩圖樣
42．．．批次保持托盤
50．．．支撐基板
50a．．．正式接著區域
51．．．支柱
52a、52b．．．擋塊
53．．．凸塊電極
55、56．．．凹部
圖1係二維積體電路與三維積體電路之比較圖(圖中(a)為二維積體電路，圖中(b)則為三維積體電路)。
圖2係習知三維積體電路之製造方法的步驟圖。
圖3係於本發明之晶片形成TSV之製程圖(圖中(a)為Via First方式，圖中(b)為Via Last(front)方式，圖中(c)為Via Last(back)等3種方式)。
圖4係本發明之三維積體電路用晶片的剖面圖。
圖5係本發明之載體基板的立體圖。
圖6係於本發明之載體基板形成親水膜及疏水膜的步驟圖。
圖7係於本發明之載體基板形成親水膜及疏水膜的步驟圖。
圖8係本發明之三維積體電路的製造方法之步驟圖。
圖9係使用批次保持托盤(tray)之情況下進行定位步驟的圖式。
圖10係於載體基板之親水膜形成支柱之範例的圖式。
圖11係將晶片之凸塊電極與載體基板之凸塊電極進行暫時接著之範例的圖式。
圖12係將晶片之凸塊電極與載體基板之凸塊電極進行暫時接著之範例的圖式。
圖13係將載體基板之SiO2 膜與晶片之SiO2 膜進行暫時接著之範例的圖式。
圖14係於晶片及載體基板形成擋塊之範例的圖式。
圖15係於支撐基板上排列有一層晶片之範例的立體圖。
20．．．晶片
20a．．．SiO2 膜
31．．．載體基板
31a．．．親水膜
40．．．水滴
50．．．支撐基板
50a．．．正式接著區域

Claims (24)

  1. 一種三維積體電路之製造方法，係將晶片層積於支撐基板以形成三維積體電路，並具備有下列步驟：將液體塗佈在轉印用基板所形成之複數個暫時接著區域；於各別分離至該複數個暫時接著區域的複數個液滴上，將複數個晶片釋放，利用液體之表面張力來讓各晶片定位至各暫時接著區域；讓於該各晶片與該各暫時接著區域之間的液體蒸發，藉以使得該各晶片暫時接著至該各暫時接著區域；讓暫時接著有該複數個晶片的該轉印用基板接近至支撐基板，將該複數個晶片中暫時接著至該轉印用基板之面的相反側，接著至該支撐基板之複數個正式接著區域處抑或層積於複數個正式接著區域的複數個層積晶片處，使得該各晶片與該支撐基板抑或該支撐基板上之各層積晶片之間的接著力會較該各晶片與該轉印用基板之間的接著力更強的方式來批次式地進行正式接著；以及藉由將該轉印用基板自該支撐基板處分離，在該複數個晶片仍接著至該支撐基板處抑或該支撐基板上之該複數個層積晶片處之情況下，來使得該複數個晶片自該轉印用基板處剝離；於該轉印基板之該各暫時接著區域、以及該各晶片 之該轉印用基板之暫時接著面係形成有SiO2 膜；該轉印用基板之該各暫時接著區域之該SiO2 膜與該各晶片之該SiO2 膜之間的接觸面積係比平行於該各暫時接著區域之平面的該各晶片之剖面積要小。
  2. 如申請專利範圍第1項之三維積體電路之製造方法，其中該液體係添加有能在當該液體蒸發時，能讓該各晶片暫時接著至該各暫時接著區域的添加劑。
  3. 如申請專利範圍第2項之三維積體電路之製造方法，其中該添加劑會使得該SiO2 膜相互接著。
  4. 如申請專利範圍第1項之三維積體電路之製造方法，其中該轉印用基板係劃定出該暫時接著區域而形成有對於該液體具有親液性的親液性膜，且包圍該暫時接著區域而形成有對於該液體具有疏液性的疏液性膜。
  5. 如申請專利範圍第1項之三維積體電路之製造方法，其中該轉印用基板之該複數個暫時接著區域中，於面積相對較小的暫時接著區域處塗佈有相對少量的液滴，且於面積相對較大的暫時接著區域處塗佈有相對多量的液滴。
  6. 如申請專利範圍第1項之三維積體電路之製造方法，其中於該將液體塗佈在轉印用基板所形成之複數個暫時接著區域的步驟時，係藉由使得液體直接 接觸至該轉印用基板、抑或藉由使用噴嘴來將液體噴塗至該轉印用基板的方式，來將該複數個液滴塗佈至該複數個暫時接著區域。
  7. 如申請專利範圍第1項之三維積體電路之製造方法，其中該轉印用基板之該暫時接著區域以及該各晶片係形成有能相互嚙合的擋塊；該擋塊在利用該液體之表面張力來將各晶片定位至各暫時接著區域時會相互卡合，以防止該各晶片相對於該各暫時接著區域而於該各暫時接著區域之平面內產生位置偏移。
  8. 一種三維積體電路之製造方法，係將晶片層積於支撐基板以形成三維積體電路，並具備有下列步驟：將液體塗佈在轉印用基板所形成之複數個暫時接著區域；於各別分離至該複數個暫時接著區域的複數個液滴上，將複數個晶片釋放，利用液體之表面張力來讓各晶片定位至各暫時接著區域；讓於該各晶片與該各暫時接著區域之間的液體蒸發，藉以使得該各晶片暫時接著至該各暫時接著區域；讓暫時接著有該複數個晶片的該轉印用基板接近至支撐基板，將該複數個晶片中暫時接著至該轉印用基板之面的相反側，接著至該支撐基板之複數個正式接著區域處抑或層積於複數個正式接著區域 的複數個層積晶片處，使得該各晶片與該支撐基板抑或該支撐基板上之各層積晶片之間的接著力會較該各晶片與該轉印用基板之間的接著力更強的方式來批次式地進行正式接著；以及藉由將該轉印用基板自該支撐基板處分離，在該複數個晶片仍接著至該支撐基板處抑或該支撐基板上之該複數個層積晶片處之情況下，來使得該複數個晶片自該轉印用基板處剝離；於該轉印用基板之該各暫時接著區域、以及該各晶片之該轉印用基板之暫時接著面係形成有SiO2 膜；該支撐基板之SiO2 膜的表面粗糙度係比該轉印用基板之該各暫時接著區域之SiO2 膜的表面粗糙度要小。
  9. 如申請專利範圍第8項之三維積體電路之製造方法，其中該液體係添加有能在當該液體蒸發時，能讓該各晶片暫時接著至該各暫時接著區域的添加劑。
  10. 如申請專利範圍第9項之三維積體電路之製造方法，其中該添加劑會使得該SiO2 膜相互接著。
  11. 如申請專利範圍第8項之三維積體電路之製造方法，其中該轉印用基板係劃定出該暫時接著區域而形成有對於該液體具有親液性的親液性膜，且包圍該暫時接著區域而形成有對於該液體具有疏液性 的疏液性膜。
  12. 如申請專利範圍第8項之三維積體電路之製造方法，其中該轉印用基板之該複數個暫時接著區域中，於面積相對較小的暫時接著區域處塗佈有相對少量的液滴，且於面積相對較大的暫時接著區域處塗佈有相對多量的液滴。
  13. 如申請專利範圍第8項之三維積體電路之製造方法，其中於該將液體塗佈在轉印用基板所形成之複數個暫時接著區域的步驟時，係藉由使得液體直接接觸至該轉印用基板、抑或藉由使用噴嘴來將液體噴塗至該轉印用基板的方式，來將該複數個液滴塗佈至該複數個暫時接著區域。
  14. 如申請專利範圍第8項之三維積體電路之製造方法，其中該轉印用基板之該暫時接著區域以及該各晶片係形成有能相互嚙合的擋塊；該擋塊在利用該液體之表面張力來將各晶片定位至各暫時接著區域時會相互卡合，以防止該各晶片相對於該各暫時接著區域而於該各暫時接著區域之平面內產生位置偏移。
  15. 一種三維積體電路之製造方法，係將晶片層積於支撐基板以形成三維積體電路，並具備有下列步驟：將液體塗佈在轉印用基板所形成之複數個暫時接著區域；於各別分離至該複數個暫時接著區域的複數個液 滴上，將複數個晶片釋放，利用液體之表面張力來讓各晶片定位至各暫時接著區域；讓於該各晶片與該各暫時接著區域之間的液體蒸發，藉以使得該各晶片暫時接著至該各暫時接著區域；讓暫時接著有該複數個晶片的該轉印用基板接近至支撐基板，將該複數個晶片中暫時接著至該轉印用基板之面的相反側，接著至該支撐基板之複數個正式接著區域處抑或層積於複數個正式接著區域的複數個層積晶片處，使得該各晶片與該支撐基板抑或該支撐基板上之各層積晶片之間的接著力會較該各晶片與該轉印用基板之間的接著力更強的方式來批次式地進行正式接著；以及藉由將該轉印用基板自該支撐基板處分離，在該複數個晶片仍接著至該支撐基板處抑或該支撐基板上之該複數個層積晶片處之情況下，來使得該複數個晶片自該轉印用基板處剝離；於該轉印用基板之該各暫時接著區域、以及該各晶片之該轉印用基板之暫時接著面係形成有SiO2 膜；該轉印用基板之該各暫時接著區域之該SiO2 膜係形成於可剝離的犧牲層上；在將該複數個晶片自該轉印用基板處剝離時，係在當該轉印用基板之該各暫時接著區域之該SiO2 膜仍接著至該各晶片的狀態下，將該複數個晶片自該 轉印用基板處剝離。
  16. 如申請專利範圍第15項之三維積體電路之製造方法，其中該液體係添加有能在當該液體蒸發時，能讓該各晶片暫時接著至該各暫時接著區域的添加劑。
  17. 如申請專利範圍第16項之三維積體電路之製造方法，其中該添加劑會使得該SiO2 膜相互接著。
  18. 如申請專利範圍第15項之三維積體電路之製造方法，其中該轉印用基板係劃定出該暫時接著區域而形成有對於該液體具有親液性的親液性膜，且包圍該暫時接著區域而形成有對於該液體具有疏液性的疏液性膜。
  19. 如申請專利範圍第15項之三維積體電路之製造方法，其中該轉印用基板之該複數個暫時接著區域中，於面積相對較小的暫時接著區域處塗佈有相對少量的液滴，且於面積相對較大的暫時接著區域處塗佈有相對多量的液滴。
  20. 如申請專利範圍第15項之三維積體電路之製造方法，其中於該將液體塗佈在轉印用基板所形成之複數個暫時接著區域的步驟時，係藉由使得液體直接接觸至該轉印用基板、抑或藉由使用噴嘴來將液體噴塗至該轉印用基板的方式，來將該複數個液滴塗佈至該複數個暫時接著區域。
  21. 如申請專利範圍第15項之三維積體電路之製造方 法，其中該轉印用基板之該暫時接著區域以及該各晶片係形成有能相互嚙合的擋塊；該擋塊在利用該液體之表面張力來將各晶片定位至各暫時接著區域時會相互卡合，以防止該各晶片相對於該各暫時接著區域而於該各暫時接著區域之平面內產生位置偏移。
  22. 一種三維積體電路之製造裝置，係將晶片層積於支撐基板以形成三維積體電路，其具備有：形成複數個暫時接著區域的轉印用基板；以及將液體塗佈至轉印用基板所形成之複數個暫時接著區域的液體塗佈機構；其中，於各別分離至該複數個暫時接著區域的複數個液滴上，將複數個晶片釋放，利用液體之表面張力來讓各晶片定位至各暫時接著區域；讓於該各晶片與該各暫時接著區域之間的液體蒸發，藉以使得該各晶片暫時接著至該各暫時接著區域；讓暫時接著有該複數個晶片的該轉印用基板接近至支撐基板，將該複數個晶片中暫時接著至該轉印用基板之面的相反側，接著至該支撐基板之複數個正式接著區域處抑或層積於複數個正式接著區域的複數個層積晶片處，使得該各晶片與該支撐基板 抑或該支撐基板上之各層積晶片之間的接著力會較該各晶片與該轉印用基板之間的接著力更強的方式來批次式地進行正式接著；以及藉由將該轉印用基板自該支撐基板處分離，在該複數個晶片仍接著至該支撐基板處抑或該支撐基板上之該複數個層積晶片處之情況下，來使得該複數個晶片自該轉印用基板處剝離；於該轉印用基板之該各暫時接著區域、以及該各晶片之該轉印用基板之暫時接著面係形成有SiO2 膜；該轉印用基板之該各暫時接著區域之該SiO2 膜與該各晶片之該SiO2 膜之間的接觸面積係比平行於該各暫時接著區域之平面的該各晶片之剖面積要小。
  23. 一種三維積體電路之製造裝置，係將晶片層積於支撐基板以形成三維積體電路，其具備有：形成複數個暫時接著區域的轉印用基板；以及將液體塗佈至轉印用基板所形成之複數個暫時接著區域的液體塗佈機構；其中，於各別分離至該複數個暫時接著區域的複數個液滴上，將複數個晶片釋放，利用液體之表面張力來讓各晶片定位至各暫時接著區域；讓於該各晶片與該各暫時接著區域之間的液體蒸發，藉以使得該各晶片暫時接著至該各暫時接著區 域；讓暫時接著有該複數個晶片的該轉印用基板接近至支撐基板，將該複數個晶片中暫時接著至該轉印用基板之面的相反側，接著至該支撐基板之複數個正式接著區域處抑或層積於複數個正式接著區域的複數個層積晶片處，使得該各晶片與該支撐基板抑或該支撐基板上之各層積晶片之間的接著力會較該各晶片與該轉印用基板之間的接著力更強的方式來批次式地進行正式接著；以及藉由將該轉印用基板自該支撐基板處分離，在該複數個晶片仍接著至該支撐基板處抑或該支撐基板上之該複數個層積晶片處之情況下，來使得該複數個晶片自該轉印用基板處剝離；於該轉印用基板之該各暫時接著區域、以及該各晶片之該轉印用基板之暫時接著面係形成有SiO2 膜；該支撐基板之SiO2 膜的表面粗糙度係比該轉印用基板之該各暫時接著區域之SiO2 膜的表面粗糙度要小。
  24. 一種三維積體電路之製造裝置，係將晶片層積於支撐基板以形成三維積體電路，其具備有：形成複數個暫時接著區域的轉印用基板；以及將液體塗佈至轉印用基板所形成之複數個暫時接著區域的液體塗佈機構；其中， 於各別分離至該複數個暫時接著區域的複數個液滴上，將複數個晶片釋放，利用液體之表面張力來讓各晶片定位至各暫時接著區域；讓於該各晶片與該各暫時接著區域之間的液體蒸發，藉以使得該各晶片暫時接著至該各暫時接著區域；讓暫時接著有該複數個晶片的該轉印用基板接近至支撐基板，將該複數個晶片中暫時接著至該轉印用基板之面的相反側，接著至該支撐基板之複數個正式接著區域處抑或層積於複數個正式接著區域的複數個層積晶片處，使得該各晶片與該支撐基板抑或該支撐基板上之各層積晶片之間的接著力會較該各晶片與該轉印用基板之間的接著力更強的方式來批次式地進行正式接著；以及藉由將該轉印用基板自該支撐基板處分離，在該複數個晶片仍接著至該支撐基板處抑或該支撐基板上之該複數個層積晶片處之情況下，來使得該複數個晶片自該轉印用基板處剝離；於該轉印用基板之該各暫時接著區域、以及該各晶片之該轉印用基板之暫時接著面係形成有SiO2 膜；該轉印用基板之該各暫時接著區域之該SiO2 膜係形成於可剝離的犧牲層上；在將該複數個晶片自該轉印用基板處剝離時，係在當該轉印用基板之該各暫時接著區域之該SiO2 膜 仍接著至該各晶片的狀態下，將該複數個晶片自該轉印用基板處剝離。
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Families Citing this family (19)

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Publication number Priority date Publication date Assignee Title
US9343436B2 (en) * 2010-09-09 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked package and method of manufacturing the same
JP2013182973A (ja) * 2012-03-01 2013-09-12 Tokyo Electron Ltd 基板の接合方法及び半導体装置
EP2701189B1 (en) * 2012-08-24 2016-01-20 Imec Substrate, fabrication method of such a substrate, method of self-assembly of such substrates and device obtained thereof
JP6027828B2 (ja) * 2012-09-14 2016-11-16 国立大学法人東北大学 素子の実装方法および光モジュールの製造方法
NL2009757C2 (en) * 2012-11-05 2014-05-08 Micronit Microfluidics Bv Method for forming an electrically conductive via in a substrate.
JP6306568B2 (ja) 2013-03-07 2018-04-04 東北マイクロテック株式会社 積層体及びその製造方法
JP6278760B2 (ja) * 2014-03-11 2018-02-14 株式会社ディスコ チップ整列方法
JP6225771B2 (ja) * 2014-03-17 2017-11-08 株式会社デンソー 半導体装置およびその製造方法
KR101596131B1 (ko) * 2014-04-25 2016-02-22 한국과학기술원 소수성 표면을 이용한 칩 패키징 방법 및 칩 패키지
JP5882510B2 (ja) * 2014-06-30 2016-03-09 太陽インキ製造株式会社 感光性ドライフィルムおよびそれを用いたプリント配線板の製造方法
US10553455B2 (en) * 2016-03-17 2020-02-04 Tokyo Electron Limited Method for aligning chip components relative to substrate by using liquid
EP3449482A4 (en) 2016-06-27 2019-12-11 Apple Inc. STORAGE SYSTEM WITH COMBINED STORAGE HIGH DENSITY, LOW BANDWIDTH AND LOW DENSITY AND HIGH BANDWIDTH
JP6842660B2 (ja) * 2017-02-10 2021-03-17 国立大学法人東北大学 基材、塗布方法及び塗布装置
FR3063832B1 (fr) * 2017-03-08 2019-03-22 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede d'auto-assemblage de composants microelectroniques
CN108122814B (zh) * 2017-10-27 2021-04-23 江西乾照光电有限公司 一种led芯片中led芯粒的分选转移方法
JP7199307B2 (ja) * 2019-05-24 2023-01-05 株式会社ディスコ 移設方法
CN110752145B (zh) * 2019-10-28 2022-03-01 清华大学 基于液体毛细力和表面张力的转印方法和转印头
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JP2024080246A (ja) * 2022-12-02 2024-06-13 タツモ株式会社 積層デバイスの製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0779152B2 (ja) * 1991-09-24 1995-08-23 日本電気株式会社 フリップチップ型半導体装置の実装方法
JP3976114B2 (ja) * 2000-05-24 2007-09-12 洋太郎 畑村 装置の製造方法、および素子基板の製造方法
US20040154733A1 (en) 2001-02-08 2004-08-12 Thomas Morf Chip transfer method and apparatus
US6790691B2 (en) * 2001-06-29 2004-09-14 Xanoptix, Inc. Opto-electronic device integration
JP2006066841A (ja) * 2004-08-30 2006-03-09 Epson Toyocom Corp シート状ウェハのダイシング及び梱包方法、ウェハの梱包物、剥離治具
JP5007127B2 (ja) 2004-12-28 2012-08-22 光正 小柳 自己組織化機能を用いた集積回路装置の製造方法及び製造装置
US7400037B2 (en) * 2004-12-30 2008-07-15 Advanced Chip Engineering Tachnology Inc. Packaging structure with coplanar filling paste and dice and with patterned glue for WL-CSP
JP2009130269A (ja) * 2007-11-27 2009-06-11 Nec Electronics Corp 半導体製造装置および半導体装置の製造方法
US8378498B2 (en) * 2010-09-09 2013-02-19 International Business Machines Corporation Chip assembly with a coreless substrate employing a patterned adhesive layer

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