TWI428274B - Process of nanotubes with internal connections - Google Patents

Process of nanotubes with internal connections Download PDF

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TWI428274B
TWI428274B TW099141452A TW99141452A TWI428274B TW I428274 B TWI428274 B TW I428274B TW 099141452 A TW099141452 A TW 099141452A TW 99141452 A TW99141452 A TW 99141452A TW I428274 B TWI428274 B TW I428274B
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layer
carbon nanotube
substrate
manufacturing
upper cladding
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TW099141452A
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TW201221467A (en
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Hsin Wei Wu
Chung Min Tsai
Tri Rung Yew
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Nat Univ Tsing Hua
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53276—Conductive materials containing carbon, e.g. fullerenes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H01L2221/1094—Conducting structures comprising nanotubes or nanowires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Carbon And Carbon Compounds (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

內連線之奈米碳管的製程方法
本發明係有關一種奈米碳管的製程方法，尤指一種內連線之奈米碳管的製程方法。
隨著半導體電路密度的增加及尺寸的縮減，各個連接金屬線之間距不斷的縮減，為了有效解決電子遷移抵制力(Electrical Migration)及阻容遲滯(RC delay)效應，其係通常應用一奈米碳管的結構，以解決上述問題，但奈米碳管的結構通常無法與金屬線有很好的連結介面與接觸阻值。
為了有效解決奈米碳管與金屬線的連結問題，中華民國專利公告第I298520號之「形成奈米碳管與金屬複合材料的電鍍互連導線的方法」，其係於金屬離子及奈米碳管的電鍍浴中對一表面具有一導電基線的基材進行電鍍，於是在該導電基線上形成奈米碳管與金屬複合材料的電鍍互連導線。其係藉由上述之技術使得導線之間具有較好的導電連接性。而中華民國專利公告第582104號之「自組裝奈米導電凸塊及其製造方法」，其係利用在奈米碳管的兩端加入數個官能基，藉由官能基與基板之特定金屬墊之金屬間的強大錯合鍵結能 力，使奈米碳管自組裝於金屬墊之上，而不同的官能基可搭配不同的金屬，以使金屬和奈米碳管間產生強大的結合力。
另外，如美國專利公告第7312531號之「Semiconductor device and fabrication method thereof」，其係揭露一種線路層的半導體裝置，其係藉由一觸媒層設置於基底與奈米碳管之間，觸媒層之材質係為鈷(Co)與M1，M1係選自由W、P、B、Bi、Ni或上述之組合。並且其揭露了一設置於奈米碳管上的頂蓋層(Top layer)，其材質係為鉭(Ta)或氮化鉭(TaN)等，該奈米碳管透過頂蓋層而可與上層的導線連接，以避免阻值高的問題。藉此可防止內連線結構中的高電阻、開路、與介電層污染或受損的問題。但這樣的設置會增加了製程的步驟，並且在進行製程時，基底介面容易因為與氧的接觸而有阻值提高的問題。
本發明之主要目的，在於提供一種解決半導體之內連線阻值高、電子遷移抵制力及阻容遲滯效應的問題。
本發明之另一目的，在於避免複雜的半導體製程，且避免進行製程時因金屬介面與氧接觸而氧化進而有增加阻值的問題，可使上層金屬層與奈米碳管間有更佳之連接介面。
為達上述目的，本發明提供一種內連線之奈米碳管的製程方法，其包含有下列步驟：
S1：於一基底上設置一絕緣層，該絕緣層上設置有一通口連通該基底。
S2：設置一包含一催化層及一上包覆層的觸媒層於該通 口的一底面以及一環繞該底面的側壁，該觸媒層係與該基底及該絕緣層連接。
S3：成長一奈米碳管於該通口內，使奈米碳管成長於該催化層和上包覆層之間，以化學氣相沉積將該奈米碳管沈積成長於該催化層上，而上包覆層則覆蓋於該奈米碳管上與相對於該基底另一側之一導線相接。
由上述說明可知，本發明透過一包含一催化層及一上包覆層之觸媒層之設置，及後續化學氣相沉積，可使奈米碳管成長於一催化層及一上包覆層之間。且因該上包覆層之保護，可避免該催化層氧化，而有利奈米碳管成長。另一方面，奈米碳管可透過該催化層及該上包覆層，分別和下層基底及上層導線相通，具有相對較低接觸阻值之特性。並藉由該觸媒層可作為金屬的阻障層，避免金屬藉由擴散或其他方式而散佈到其他材料內。製程步驟簡單，因而能夠減少半導體製程的成本。
10‧‧‧基底
11‧‧‧蝕刻停止層
20‧‧‧絕緣層
21‧‧‧通口
30‧‧‧觸媒層
31‧‧‧催化層
32‧‧‧上包覆層
40‧‧‧奈米碳管
41‧‧‧非晶碳自成長層
50‧‧‧導線
60‧‧‧D-band
61‧‧‧G-band
S1~S6‧‧‧步驟
圖1A-1F，係本發明一較佳實施例之製程步驟示意圖。
圖2，係本發明一較佳實施例之方法流程示意圖。
圖3，係本發明一較佳實施例之拉曼位移示意圖。
有關本發明之詳細說明及技術內容，現就配合圖式說明如下：請參閱「圖1A-1F」及「圖2」所示，其係分別為本發明一較佳實施例之方法流程及製程步驟示意圖，如圖所示：本 發明係為一種內連線之奈米碳管的製程方法，其包含有下列步驟：
S1：設置一蝕刻停止層11於一基底10上，其中該基底10為一導體材料，如銅金屬等，而該蝕刻停止層11之材質為氮化矽，該蝕刻停止層11係為不導電材質，且可作為銅擴散阻障之用。
S2：於該基底10上設置一絕緣層20，該絕緣層20上設置有一通口21連通該基底10，而該絕緣層20之材質於本實施例中係為二氧化矽，而該絕緣層20係透過該蝕刻停止層11與該基底10連接，蝕刻停止層11通常用以控制蝕刻時間以決定絕緣層20之通口深度，避免破壞下方基底10。
S3：設置一觸媒層30於該通口21的一底面以及一環繞該底面的側壁，該觸媒層30係與該基底10及該絕緣層20連接，其中，該觸媒層30包含一催化層31與一上包覆層32，請配合參閱「圖1C」所示。於本實施例中，該催化層31之材質可為鈷或鎳，而該上包覆層之材質為鉭。
S4：成長一奈米碳管40於該通口21內，係以化學氣相沈積法成長於該通口21內，使奈米碳管40成長於一催化層31及一上包覆層32之間。且因該上包覆層32之保護，避免該催化層31氧化，而有利奈米碳管40之成長。另一方面，奈米碳管40可透過該催化層31及該上包覆層32，分別和下層基底10及上層導線50電性連接
S5：去除非晶碳自成長層41，於奈米碳管自組裝成長後，因為組成奈米碳管40的碳源會自成長出一非晶碳自成長層 41，必須透過電漿將其去除，以利後續製程的進行。
S6：設置一導線50於具有奈米碳管40的通口21上，該導線50係與奈米碳管40表面的該上包覆層32連接。
藉由上述步驟，可將半導體中的內連線金屬透過奈米碳管40做有效的連接，而奈米碳管40透過該觸媒層30之催化層31與下層的基底10電性連接，以及透過觸媒層30的上包覆層32而與上層的導線50電性連接。
請參閱「圖3」所示，其係本發明一較佳實施例之拉曼(Raman)分析，如圖所示，D-band 60之拉曼位移(Raman shift)位於1333(cm-1)，而G-band 61位於1581(cm-1)，由此得知，其IG/ID之值為1.014，表示本發明所形成之奈米碳管的結晶性佳，顯示本發明的方法相當可行。
綜上所述，由於本發明透過將該觸媒層30設置於該通口21的該底面以及該側壁，使奈米碳管40成長於該催化層31及上包覆層32之間。且因該上包覆層32之保護，可避免該催化層31氧化，而有利奈米碳管40之成長。另一方面，奈米碳管40可透過該催化層31及該上包覆層32，分別和該下層基底10及上層導線50電性連接。因製程步驟簡單，而能夠減少半導體製程的成本。此外，藉由該觸媒層30的設置，亦能達到減少該催化層31直接與氧接觸而有阻值增加的可能。再者，該觸媒層30中的上包覆層32材質亦可做為銅擴散阻障層(Barrier layer)避免作為基底10或導線50的銅材質的擴散問題。因此本發明極具進步性及符合申請發明專利之要件，爰依法提出申請，祈鈞局早日賜准專利，實感德便。
以上已將本發明做一詳細說明，惟以上所述者，僅為本發明之一較佳實施例而已，當不能限定本發明實施之範圍。即凡依本發明申請範圍所作之均等變化與修飾等，皆應仍屬本發明之專利涵蓋範圍內。
S1~S6‧‧‧步驟

Claims (7)

  1. 一種內連線之奈米碳管的製程方法，其包含有下列步驟：於一基底上設置一絕緣層，該絕緣層上設置有一通口連通該基底；設置一觸媒層於該通口的一底面以及一環繞該底面的側壁，該觸媒層包含一催化層及一上包覆層，該觸媒層係與該基底及該絕緣層連接；成長一奈米碳管於該通口內，使該奈米碳管成長於該催化層和上包覆層之間，該上包覆層覆蓋於該奈米碳管上與相對於該基底另一側之一導線相接。
  2. 如申請專利範圍第1項所述之內連線之奈米碳管的製程方法，其中更具有一步驟：設置一蝕刻停止層於該基底上，該蝕刻停止層之材質為氮化矽。
  3. 如申請專利範圍第1項所述之內連線之奈米碳管的製程方法，其中該催化層之材質為鈷或鎳。
  4. 如申請專利範圍第1項所述之內連線之奈米碳管的製程方法，其中該上包覆層之材質為鉭。
  5. 如申請專利範圍第1項所述之內連線之奈米碳管的製程方法，其中該奈米碳管係以化學氣相沈積法成長於該通口內。
  6. 如申請專利範圍第1項所述之內連線之奈米碳管的製程方法，其中具有一步驟：去除一非晶碳自成長層，該非晶碳自成長層係為該奈米碳管自行成長而得。
  7. 如申請專利範圍第1項所述之內連線之奈米碳管的製程方法，其中該基底係為一導體，而該絕緣層之材質係為選自於由二氧化矽、含碳低介電絕緣材料、含氟低介電絕緣材料及具孔隙之低介電絕緣材料所組成之群組。
TW099141452A 2010-11-30 2010-11-30 Process of nanotubes with internal connections TWI428274B (zh)

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US13/094,388 US8461037B2 (en) 2010-11-30 2011-04-26 Method for fabricating interconnections with carbon nanotubes

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5624600B2 (ja) * 2012-12-27 2014-11-12 株式会社東芝 配線及び半導体装置の製造方法
JP5813682B2 (ja) * 2013-03-08 2015-11-17 株式会社東芝 半導体装置及びその製造方法
JP2016063097A (ja) * 2014-09-18 2016-04-25 株式会社東芝 カーボンナノチューブ配線構造およびその製造方法
US9544998B1 (en) * 2015-09-14 2017-01-10 The Boeing Company Growth of carbon nanotube (CNT) leads on circuits in substrate-free continuous chemical vapor deposition (CVD) process

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW582104B (en) 2002-11-08 2004-04-01 Ind Tech Res Inst Self-assembled nanometer conductive bump and its manufacturing method
US7135773B2 (en) * 2004-02-26 2006-11-14 International Business Machines Corporation Integrated circuit chip utilizing carbon nanotube composite interconnection vias
TWI298520B (en) 2005-09-12 2008-07-01 Ind Tech Res Inst Method of making an electroplated interconnection wire of a composite of metal and carbon nanotubes
US7312531B2 (en) 2005-10-28 2007-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and fabrication method thereof
KR100721020B1 (ko) * 2006-01-20 2007-05-23 삼성전자주식회사 콘택 구조체를 포함하는 반도체 소자 및 그 형성 방법
US8193641B2 (en) * 2006-05-09 2012-06-05 Intel Corporation Recessed workfunction metal in CMOS transistor gates
JP2011204769A (ja) * 2010-03-24 2011-10-13 Toshiba Corp 半導体装置及びその製造方法

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TW201221467A (en) 2012-06-01
US8461037B2 (en) 2013-06-11

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