TWI409774B - Liquid crystal display device and its driving method - Google Patents

Abstract

The invienton provides a liquid crystal display device and driving method thereof, which obtains a pixel voltage exceeding the ouput voltage of a driver LSI. The liquid crystal display device is disclosed comprising a display part, a scanning line driving circuit, a signal line driving circuit, a counter electrode driving circuit for providing counter electrodes with a counter electrode driving signal reversed in phase from a signal line driving circuit, an auxiliary capacitance having one end connected to an output end of each of switching elements, and an auxiliary capacitance line driving circuit for driving a plurality of auxiliary capacitance lines arranged in rows and has ends of such auxiliary capacitances in each row commonly connected thereto, wherein the auxiliary capacitance line driving circuit is adapted to apply a first voltage to the auxiliary capacitance lines for a first half cycle of the counter electrode driving signal and apply a second voltage thereto for a (p+ 1/2 )th cycle after the first period of the counter electrode driving signal where p is 0 or a natural number, said auxiliary capacitance line driving circuit making the auxiliary capacitance line in a floating condition after said (p+ 1/2 ) th cycle during the remaining holding time.

Description

Liquid crystal display device and driving method thereof

The present invention relates to a liquid crystal display device and a method of driving the same, and more particularly to a liquid crystal display device capable of boosting a pixel voltage by driving a capacitor electrode independent of a counter electrode, and a method of driving the same.

In a conventional liquid crystal display device, a voltage is applied to a liquid crystal by a switching element such as a thin film transistor (TFT) provided on each pixel composed of a liquid crystal. Fig. 21 is a view schematically showing the structure of one pixel component 100 of the conventional liquid crystal display device, and Fig. 22 is a view schematically showing the pixel structure of one column.

The pixel electrode (Pix) 101 is charged to the source potential by the transistor 102. A voltage (Vcom) for driving the counter electrode is applied to the counter electrode (COM) 103, and a potential difference between the counter electrode 103 and the pixel electrode 101 becomes a liquid crystal driving voltage (Vlcd). A storage capacitor electrode (Cs) 105 is provided on the substrate 104 side. The storage capacitor electrode 105 relaxes the potential fluctuation generated in the pixel electrode 101 due to the leakage current at the gate of the transistor 102 or the leakage current. The wiring of the auxiliary capacitor electrode 105 is usually laid in parallel with the gate wiring. This wiring is connected to the counter electrode 103. Thereby, the potential of the storage capacitor electrode 105 becomes a common potential with the counter electrode 103. The liquid crystal is AC driven to prevent imprinting or electrical decomposition.

Fig. 23 is a timing chart showing an example of a driving waveform of the liquid crystal display device, wherein (A) shows a voltage waveform applied to the counter electrode, (B) shows a signal line voltage waveform, and (C) shows a scanning line voltage waveform, (D) ) indicates the liquid crystal drive voltage waveform. As shown in the figure, the voltage waveform (Vcom) applied to the counter electrode and the voltage waveform (Vs) applied to the source electrode of the transistor are rectangular waves, and the scan line voltage is a voltage applied to the gate electrode of the transistor ( Vg). As shown in Fig. 23(C), when a high level of voltage is applied to the gate, the transistor is turned on, and when the voltage applied to the gate becomes high, the transistor becomes non-conductive. Between the holding period in which the transistor is turned off, the liquid crystal driving voltage (Vlcd) is changed up and down in accordance with the waveform of the voltage (Vcom) applied to the counter electrode, so that the liquid crystal driving voltage is applied to the gate. Each cycle of the voltage becomes a positive and negative voltage and is AC driven.

In terms of driving the liquid crystal display device, a voltage of about ±4 to 5 V is required for AC driving. As shown in Fig. 23, the AC drive voltage is generated by a combination of the signal line voltage (Vs) and the rectangular wave of the counter electrode voltage (Vcom). These signal waveforms are supplied from the driver LSI. In recent years, LSI's low voltage has been continuously improved, and the voltage between Vcom and Vs is about 4.8V at the maximum. This voltage limitation is not absolute. However, in order to output the above voltage from the driver LSI, it is necessary to change the withstand voltage design of the LSI, and the area and cost of the LSI are greatly increased. Since it is necessary to drive a liquid crystal display device as described above, a voltage of about ±4 to 5 V is required, so that it can be said that it is a barely good balance. However, in a liquid crystal display device (a vertical alignment mode or a lateral electric field mode n-type liquid crystal) developed in recent years, in order to fully exhibit its performance, there is a need for a voltage exceeding 5 V. In today's LSI There will be a slight lack of capacity in the middle.

However, in the liquid crystal display device disclosed in Patent Document 1, the storage capacitor line and the counter electrode are not connected, but a storage capacitor line drive circuit is particularly provided. In this case, the auxiliary capacitor is formed by a storage capacitor electrode, a pixel electrode, and an insulating layer interposed between the electrodes. Patent Document 1 discloses a liquid crystal display device in which a voltage different from a counter electrode is applied to a storage capacitor electrode from a storage capacitor line drive circuit. Fig. 24, Fig. 25, and Fig. 26 are diagrams each showing a block diagram of a liquid crystal display device disclosed in Patent Document 1, a waveform of a gate signal and a storage capacitor line drive signal, and a waveform applied to a pixel.

In Fig. 24, a display area 111 indicated by a broken line is a display unit that displays a predetermined image by a plurality of pixels. The display unit is scanned by the scanning lines G ₁ , G ₂ , G ₃ ... G _{n ,} and the display signals are given by the signal lines S ₁ , S ₂ , S ₃ ... S _m .

A thin film transistor (TFT) 114 is disposed at an intersection of the scanning lines G ₁ , G ₂ , G ₃ ... G _n and the signal lines S ₁ , S ₂ , S ₃ ... S _m . The liquid crystal cell 115 is disposed on the pixel electrode portion connected to the drain of each of the thin film transistors 114. The gate of the transistor is connected to the scanning line G, and the source is connected to the signal line S.

The scanning line driving circuit 116 sequentially scans the scanning lines G ₁ , G ₂ , G ₃ , G _n , and selects one column of pixel lines for each horizontal period. The signal line drive circuit 117 outputs a display signal through the respective signal lines S ₁ , S ₂ , S ₃ ... S _m , and the column 114 selected by the scan line drive circuit 116 in one horizontal period by the transistor 114 The portion of the liquid crystal cell imparts a pixel voltage. Further, the counter electrode 118 and its wiring line are provided on the second transparent substrate with the liquid crystal cells 115 interposed therebetween. These two substrates sandwich the liquid crystal cells 115.

The counter electrode driving circuit 119 applies a common counter electrode voltage Vcom to all of the liquid crystal cells by the counter electrode 118. One end of the auxiliary capacitor 112 provided on each pixel is connected to the drain of each of the transistors 114, and the other end is connected to the auxiliary capacitance line 113 different from each of the scanning lines. The scanning lines G ₁ corresponding to the storage capacitor line 113 line is connected to the first output terminal of the auxiliary capacitance line driver circuit 110, the scanning lines G ₂ corresponding to the storage capacitor line 113 line the second output terminal is connected to the auxiliary capacitance line driver circuit 110 . The auxiliary capacitance lines 113 corresponding to the scanning lines G ₃ to G _n are also connected in the same manner. Corresponding to the scanning lines G ₁ to G _n , the storage capacitor driving voltages Vst1 to Vstn are outputted from the first output to the nth output of the auxiliary capacitance line drive circuit 110 at different timings.

25 FIG line a timing chart showing the operation of the apparatus in Patent Document liquid crystal of a display section 25 (A) in FIG represents G from each of the scanning lines _1, G ₂ ... gate signal G _{SIG output, 1,} G _{sig, 2} ... 25(B) shows changes in the storage capacitor line drive voltages Vst1, Vst2, ... outputted from the auxiliary capacitance line drive circuit 110. The gate signals G _sig,1 , G _{sig , 2} ... are output from the scanning line driving circuit 116 of Fig. 24 and select the pulse wave of the scanning line, and have a repetition period of one frame. The voltage of the gate signal G _sig becomes the voltage Vgh when each pixel of one column is selected, and is held at the voltage Vgl when it is not selected. The auxiliary capacitance line drive voltages Vst1, Vst2, ... are binary voltage signals having an amplitude of ΔVst. As shown, it is applied to one end of each liquid crystal cell 115 by an auxiliary capacitor 112. Further, for the scanning line G ₁ of the auxiliary capacitance line drive voltage Vst1 be a slight delay after the gate signal G _SIG, and the amplitude varies only _a decrease Δ Vst. Similarly, the amplitude of the auxiliary capacitance line drive voltage Vst2 is changed.

Fig. 26 is a waveform diagram of voltages applied to respective pixels of the liquid crystal display device of Patent Document 1. The gate signal G _sig as shown in the same figure is output from the scanning line driving circuit 116 to the selected scanning line Gi (i = 1 to n). When one pixel of each column is selected, the voltage becomes Vgh, and when it is not selected, the voltage becomes Vgl. The DC counter electrode voltage Vcom is output from the counter electrode driving circuit 119. Vcom is fixed. The output voltage Vd outputted from the drain of the transistor 114 is in one frame period, and the output level is changed to the positive and negative sides centering on the counter electrode voltage Vcom. When the gate is selected, the pixel electrode of the liquid crystal cell 115 located on the scanning line is charged to the signal voltage Vsig supplied by the signal line S, but between the drain and the gate of the parasitic capacitance of the transistor 114. Under the influence of the capacitance Cdg, when the gate signal Gsig changes from Vgh to Vgl, the output voltage Vd changes to a voltage which is only Vpt lower than Vsig. Thereafter, as shown in the figure, if the auxiliary capacitance driving voltage Vst of the auxiliary capacitance line driving circuit 110 is lowered by only the ΔVst voltage, the output voltage Vd may be lowered by K ‧ ΔVst. Here, K is a constant depending on the capacitance value contained in the capacitance combination. In this way, the voltage Vd1 which is the difference between the counter electrode voltage Vcom and the voltage Vd of the pixel electrode is applied as the driving voltage of the liquid crystal cell 115.

More specifically, the above constant K is given by the following formula (1).

K=Cst/(Clc+Cst+Cdg) (1)

Here, the capacitance of the Cst-based auxiliary capacitor 112, the capacitance of the Clc-based liquid crystal cell 115, and the parasitic capacitance between the drain-gate of the Cdg-based transistor 114.

In the next frame, when the display signal is written to each liquid crystal cell 115 of the same scan line, when the scan line Gi is selected again, the liquid crystal of the pixel (i, j) by the signal line S _{j is} utilized. The signal voltage Vsig supplied from the cell 115 is charged. Vsig is centered on the level of Vcom and has a substantially symmetrical waveform. As shown in Fig. 26, in the transistor 114, under the influence of the parasitic capacitance Cdg between the drain and the gate _{, when} the voltage of the gate signal G _{sig, i} changes from Vgh to Vgl, the output voltage Vd is only Drop Vpt. Then, when the storage capacitor driving voltage Vst of the auxiliary capacitance line driving circuit 110 rises by only ΔVst, the output voltage Vd rises by only K‧ΔVst from the current voltage. Here, K is the above constant. Thereafter, the rising voltage is maintained, and the difference between the output voltage Vd and the counter electrode voltage Vcom is applied to the liquid crystal cell 115 as the driving voltage Vd1. As such, the liquid crystal panel is AC driven with one frame period.

As shown in Fig. 25, in the case where the output voltage Vd is lowered with respect to the counter electrode voltage Vcom, the output voltage Vd is compared with (Vsig + Vpt) by the signal from the auxiliary capacitance line driving circuit 110. The K‧ΔVst is translated in a lower direction with respect to the counter electrode voltage Vcom. Further, in the case where the output voltage Vd is increased with respect to the counter electrode voltage Vcom, the output voltage Vd is opposite to the counter electrode by (Vsig-Vpt) by the signal from the auxiliary capacitance line driving circuit 110. The voltage Vcom translates K‧ΔVst in a higher direction.

Therefore, according to Patent Document 1, since the liquid crystal cell 115 is black-displayed, when the drive voltage Vd1 is set to a value Vd11 higher than Vd10, the value of the signal voltage Vsig with respect to the predetermined drive voltage Vd11 can be reduced. In this way, since the output voltage Vd given to the liquid crystal cell 115 is shifted by only K ‧ ΔVst in the direction away from the counter electrode voltage Vcom, the amplitude Vspp' of the signal line can be more than the amplitude Vspp of the signal line of the conventional liquid crystal cell small.

In the method of driving the storage capacitor electrode described in Patent Document 1, a DC voltage is applied to the counter electrode, and the potential of the storage capacitor electrode is driven in synchronization with the frame period so as to be independent of the counter electrode, thereby driving the liquid crystal drive. The increase in voltage (Vlcd). However, the output signal Vst1 from the auxiliary capacitance line drive circuit 110 has a binary voltage signal having an amplitude of ΔVst which is slightly delayed after the gate signal G _sig,1 falls and the amplitude changes only by ΔVst. Therefore, it is necessary for the driving voltage Vst1 scanning line G ₁ of the auxiliary capacitance line to the scanning line G ₁ from a waveform of the ON cycle offset. Therefore, the signal of the auxiliary capacitance line driving circuit is complicated because any waveform applied to the signal line, the scanning line, and the counter electrode is different.

[Patent Document 1] JP-A-2001-255851

In the conventional liquid crystal display device shown in Fig. 23, the liquid crystal driving voltage (Vlcd) is applied by a combination of a signal line voltage (Vs) and a rectangular wave of the counter electrode voltage (Vcom). Therefore, when it is necessary to increase the liquid crystal driving voltage, a driving LSI having a large output voltage is required. In order to increase the signal line voltage without using a driving LSI having a large output voltage, it is considered that the auxiliary capacitor electrode is driven as in Patent Document 1 and the liquid crystal driving voltage is raised, but in the case of Patent Document 1, the pair is driven by a DC voltage. Since it is directed to the electrode, it cannot be applied immediately when the counter electrode voltage is driven by a rectangular wave. Therefore, in the conventional liquid crystal display device shown in FIG. 23, there is a problem in that it is impossible to obtain a specific circuit configuration and a driving method for driving the counter electrode voltage by a rectangular wave and driving the auxiliary capacitor to increase the liquid crystal driving voltage. .

In view of the above-described problems, it is an object of the present invention to provide a liquid crystal display device in which a boosting electrode is provided inside a pixel, and an operation similar to that of charge pumping is performed with an easier configuration, and it is possible to obtain a liquid crystal display. The pixel voltage of the output voltage of the driver LSI. Another object of the present invention is to provide a driving method of the liquid crystal display device.

In order to achieve the above-described object, the first configuration of the liquid crystal display device of the present invention includes a display unit which is composed of a scanning line which is composed of a plurality of columns (here, the column is an arbitrary natural number of 1≦i≦m). a signal line consisting of a plurality of lines (here, the line is an arbitrary natural number of 1≦j≦n); a switching element, which is disposed at an intersection of the scanning line and the signal line; a pixel electrode, It is connected to the output end of the switching element; the opposite electrode; the pixel matrix of m columns×n rows, which is formed by arranging liquid crystal cells between the pixel electrode and the counter electrode; the auxiliary capacitor is connected to the switching element at one end thereof. And an auxiliary capacitor line, which is composed of a plurality of columns connected to the switching elements of the columns and having the other ends of the auxiliary capacitors of the columns become common; the scanning line driving circuit has a scan line output for each column The switching element is a scanning line driving signal during an on period and an off period in which the switching element is turned on; the signal line driving circuit outputs a signal line driving signal to each line of signal lines; and the opposite electrode driving circuit is opposed to the opposite side Electrode output pair a driving signal for an electrode; and a storage capacitor line driving circuit for outputting a driving signal for the auxiliary capacitance line to the auxiliary capacitance line of each column; and the auxiliary capacitance line driving circuit for the auxiliary capacitance line, the first driving signal for the counter electrode The first voltage is applied during the period, and the second voltage is applied to the p+1/2 period (here, p is 0 or a natural number) after the first period of the driving signal for the counter electrode, where p+1/2 In the sustain period after the cycle, a signal for being turned on is outputted for each scanning line of each column by a drive signal.

According to the liquid crystal display device of the present invention, the auxiliary capacitor line driving circuit is configured to drive the auxiliary capacitor, and the boost state of the pixel voltage (Vpix) can be maintained during the holding period, and the contrast of the pixel can be improved. Therefore, the voltage within the voltage limit of the driver LSI used in the liquid crystal display device can be used, and the potential of the pixel can be raised.

In the above configuration, it is preferable that the auxiliary capacitance line drive circuit is composed of the first and second driving transistors connected to each of the storage capacitor lines, and the first main electrode and the auxiliary capacitor of the first driving transistor. The other end is connected, and the second main electrode of the first driving transistor is connected to the counter electrode wiring (COM1) serving as the first common electrode, and the control electrode of the first driving transistor and the scanning line of the i-th column (G _i The first main electrode of the second driving transistor is connected to the first main electrode of the first driving transistor, and the second main electrode of the second driving transistor is connected to the second common electrode wiring (COM2). The control electrode of the second driving transistor is connected to the scanning line (G _i+2 ) of the i+2th column.

A second configuration of the liquid crystal display device of the present invention includes a display unit composed of a scanning line composed of a plurality of columns (here, the column is an arbitrary natural number of 1≦i≦m); , which consists of a plurality of rows (here, the row is an arbitrary natural number of 1≦j≦n); a switching element, which is disposed at an intersection of the scan line and the signal line; and a pixel electrode connected to the switching element Output terminal; opposite electrode; m column x n rows of pixel matrix, which is formed by arranging liquid crystal cells between the pixel electrode and the counter electrode; and an auxiliary capacitor having one end connected to the output end of the switching element; The auxiliary capacitor line is composed of a plurality of columns connected to the switching elements of the respective columns and the other ends of the auxiliary capacitors of the respective columns; the scanning line driving circuit has the switching elements turned on for the scanning line outputs of the respective columns a scan line drive signal during the turn-on period and the off hold period; a signal line drive circuit that outputs a signal line drive signal for each row of signal lines; and a counter electrode drive circuit that outputs a counter electrode to the counter electrode Using a drive signal; The auxiliary capacitance line drive circuit outputs a drive signal for the auxiliary capacitance line to the auxiliary capacitance line of each column, and the auxiliary capacitance line drive circuit is composed of the first and second drive transistors connected to each of the storage capacitor lines. The first main electrode of the first driving transistor is connected to the other end of the storage capacitor, and the second main electrode of the first driving transistor is connected to the counter electrode wiring (COM1) serving as the first common electrode, and the first driving is used for the first driving. The control electrode of the transistor is connected to the scanning line (G _i ) of the i-th column, and the first main electrode of the second driving transistor is connected to the first main electrode of the first driving transistor, and the second driving transistor is The second main electrode is connected to the second common electrode wiring (COM2), the control electrode of the second driving transistor is connected to the scanning line (G _i+2 ) of the i+2 column, and the auxiliary capacitance line driving circuit is for the auxiliary capacitor. The first voltage is applied to the first period of the driving signal for the counter electrode, and is in the p+1/2 period (here, p is 0 or a natural number) after the first period of the driving signal for the counter electrode. The second voltage is applied, and each of the columns is matched in the holding period after the p+1/2 period. A scanning line drive signal set signal output ON state.

According to the above configuration, the auxiliary capacitance drive circuit can be realized by using the two transistors provided in each of the storage capacitor lines and the voltage applied to the counter electrode wiring and the scanning line voltage. The auxiliary capacitor can be driven by the auxiliary capacitor driving circuit to boost the pixel.

A third configuration of the liquid crystal display device of the present invention includes a display portion composed of a scanning line composed of a plurality of columns (here, the column is an arbitrary natural number of 1≦i≦m); a signal line , which consists of a plurality of rows (here, the row is an arbitrary natural number of 1≦j≦n); a switching element, which is disposed at an intersection of the scan line and the signal line; and a pixel electrode connected to the switching element Output terminal; opposite electrode; m column x n rows of pixel matrix, which is formed by arranging liquid crystal cells between the pixel electrode and the counter electrode; an auxiliary capacitor having one end connected to the output end of the switching element; a capacitor line composed of a plurality of columns connected to the switching elements of the respective columns and having the other ends of the auxiliary capacitors of the respective columns become common; and a parasitic capacitance shielding wiring which is disposed through the signal lines of the respective rows and the columns a scanning line driving circuit that outputs, to the scanning lines of the respective columns, driving signals for scanning lines having a switching period in which the switching elements are turned on and a period in which the switching elements are turned off; and a signal line driving circuit Signal line output letter of each line a driving signal for a line; a driving signal for a counter electrode that outputs a driving signal for the counter electrode; and an auxiliary capacitance line driving circuit that outputs a driving signal for the auxiliary capacitance line to the auxiliary capacitance line of each column; and an auxiliary capacitor The line driving circuit is composed of first and second driving transistors connected to each of the auxiliary capacitance lines, and the first main electrode of the first driving transistor is connected to the other end of the storage capacitor, and the first driving transistor is connected The second main electrode is connected to the counter electrode wiring (COM1) serving as the first common electrode, and the control electrode of the first driving transistor is connected to the scanning line (G _i ) of the i-th column, and the second driving transistor is The first main electrode is connected to the first main electrode of the first driving transistor, the second main electrode of the second driving transistor is connected to the second common electrode wiring (COM2), and the control electrode of the second driving transistor is The scanning line (G _i+2 ) of the i+2th column is connected, and the auxiliary capacitance line driving circuit applies the first voltage to the auxiliary capacitor line in the first period of the driving signal for the counter electrode, and drives the counter electrode. p+1/2 period after the first cycle of the signal (here p is 0 or a natural number) is applied to the second voltage, during the holding following this p + 1/2 cycles, with each scan line signal in each column driving signal is output to the open state.

In the above configuration, preferably, the auxiliary capacitor is composed of the first and second auxiliary capacitors, and one of the first and second auxiliary capacitors is connected to the pixel electrode, and the other end of the first auxiliary capacitor is connected to the auxiliary capacitor line. a circuit, and the other end of the second auxiliary capacitor is connected to the counter electrode. The pixel boost can be performed by driving an auxiliary capacitor separately provided in addition to the pixel auxiliary capacitor.

In the above configuration, preferably, the display unit includes the first and second substrates, the scanning lines and the signal lines are provided on the first substrate, and the counter electrode is provided on the second substrate. The auxiliary capacitor is preferably composed of a wiring provided on the first substrate, an insulating film provided on the wiring, and a transparent electrode provided on the insulating film. The auxiliary capacitance line driving circuit is disposed adjacent to the display portion, and the auxiliary capacitance line driving circuit is composed of a thin film transistor using an amorphous germanium or a polycrystalline germanium. Thereby, the storage capacitor driving circuit composed of the thin film transistor can be easily formed on the substrate.

In the above configuration, it is preferable that a DC voltage is applied to the parasitic capacitance shielding wiring. The driving signal for the counter electrode can also be applied to the parasitic capacitance shielding wiring. Preferably, the parasitic capacitance shielding wiring is disposed between the switching element and the auxiliary capacitor, and is disposed in parallel with the auxiliary capacitance line. The first gate insulating film and the second gate insulating film may be disposed on the first substrate, and the parasitic capacitance shielding wiring may be disposed on the first gate insulating film. The linear portion of the parasitic capacitance shielding wiring is disposed on the first substrate, and the intersection of the parasitic capacitance shielding wiring is disposed on the first gate insulating film, and the intersection portion and the upper linear portion are also disposed in the first portion 1 Contact hole of the gate insulating film is connected. The intersection of the parasitic capacitance shielding wiring is preferably composed of a transparent electrode material.

In order to achieve the above other objects, in the driving method of the liquid crystal display device of the present invention, the liquid crystal display device is provided with a scanning line composed of a plurality of columns (here, the column is an arbitrary natural number of 1≦i≦m) and a signal line composed of a plurality of lines (here, the line is an arbitrary natural number of 1≦j≦n), a switching element is disposed at an intersection of the scanning line and the signal line, and a pixel electrode connected to an output end of the switching element A pixel matrix of m columns×n rows composed of liquid crystal cells is disposed between the counter electrodes, and one end of the auxiliary capacitor is connected to an output end of the switching element, and the driving method is to perform a pixel by the following actions. The absolute value of the potential difference between the electrode and the counter electrode is increased: a rectangular wave signal having a switching period in which the switching element is turned on and a holding period in which the switching element is turned on is applied as a scanning line driving signal for the switching element, and the signal line and the pair are applied. A rectangular wave signal is applied to the electrode, and the first voltage is applied to the other end of the auxiliary capacitor in the first cycle of the driving signal for the counter electrode, and p+1/2 after the first cycle of the driving signal for the counter electrode cycle (here, p is 0 or a natural number) The second voltage is applied, and the holding period after the p+1/2 period is set to a floating state.

In the above configuration, it is preferable that the first voltage is the same voltage as the counter electrode, and the second voltage is a voltage different from the counter electrode. Alternatively, the first voltage may be the same voltage as the counter electrode, and the second voltage may be the same voltage as the counter voltage of the counter electrode.

Preferably, the second period is applied in synchronization with the on-period of the scan line (G _i+2 ) of the first two columns of the scan line (G _i ) of the i-th column to which the switching element is connected, that is, the i+2 column. Voltage.

Preferably, the voltage applied to the storage capacitor is a voltage that reduces the amplitude of the signal applied to the counter electrode wiring. Alternatively, the voltage applied to the storage capacitor may be a DC voltage corresponding to the center of the signal amplitude applied to the counter electrode wiring.

According to the above configuration, the auxiliary capacitance applied to the pixel is driven with a waveform having a predetermined timing with respect to the signal applied to the scanning line, the signal line, and the counter electrode, and the pixel voltage (Vpix) can be maintained during the holding period. The boost state can improve the contrast of the pixels. Therefore, the voltage within the voltage limit of the driver LSI used in the liquid crystal display device can be used, and the potential of the pixel can be raised.

According to the liquid crystal display device of the present invention and the driving method thereof, the auxiliary capacitor of the pixel is driven by the auxiliary capacitor driving circuit independently of the counter electrode, and the potential of the pixel can be raised with a simple configuration without using the driver. The LSI's output voltage rises to increase the contrast of the pixels. Since the auxiliary capacitor drive circuit can use the scanning signal in the liquid crystal display device or the signal of the counter electrode wiring, the contrast of the pixel can be improved at low cost.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the figures, the same or corresponding components are denoted by the same symbols.

Fig. 1 is a block diagram showing the configuration of a liquid crystal display device 1 of the present invention. Figs. 2 to 4 show an example of the display unit 10 of the liquid crystal display device 1 of the present invention.

As shown in FIG. 1, the liquid crystal display device 1 of the present invention is composed of a display unit 10 surrounded by a broken line, a scanning line drive circuit 20 disposed around the display unit 10, a signal line drive circuit 22, and a counter electrode drive circuit 24. And a storage capacitor line drive circuit 26.

In the liquid crystal display device 1, a scanning line composed of a plurality of columns and a signal line composed of a plurality of rows are disposed on a first transparent substrate (not shown), and a switching element 12 is disposed at an intersection of the scanning line and the signal line, and is connected. A pixel 15 composed of a liquid crystal cell is disposed between the pixel electrode 13 and the counter electrode 14 at the output end of the switching element 12, and one end of the auxiliary capacitor 16 is connected to the output end of the switching element 12. Therefore, the column is composed of any natural number of 1≦i≦m and is composed of any natural number of 1≦j≦n. Further, the switching element 12 of the i-th row and the j-th row can be referred to as the switching element 12 _ij .

In the case of the illustration, the display unit 10 has a plurality of pixels 15 arranged in a matrix of m columns×n rows. In this case, the gate electrodes (also referred to as control electrodes) of the switching elements 12 of the pixels 15 arranged in the respective columns are connected to each other to form gate electrode wirings. Therefore, the gate electrode wirings of the 1, 2, 3, and m columns are connected to the scanning lines G ₁ , G ₂ , and G ₃ to G _{m of the} scanning line driving circuit 20, respectively, and are scanned.

In the switching elements 12 of the pixels 15 arranged in the respective columns, source electrodes (also referred to as first main electrodes) are connected to each other to form source electrode wirings. Therefore, the source electrode wirings of the ₁ , ₂ , ₃ , and n rows are connected to the signal lines S ₁ , S ₂ , and S ₃ to S _{n of the} signal line drive circuit 22, respectively, and a display signal is applied.

The liquid crystal cell 15 is disposed between the counter electrode 14 and the pixel electrode 13 connected to the drain electrode (also referred to as the second main electrode) of each of the switching elements 12. The switching element 12 is, for example, a transistor. As the transistor 12, a thin film transistor produced by using amorphous germanium or low-temperature polycrystalline silicon on a first transparent substrate (not shown) can be used. As described above, the gate of the transistor 12 is connected to the scanning line, and the source is connected to the signal line S. The wiring of the counter electrode 14 and the counter electrode 14 is provided on a second transparent substrate (not shown) via the liquid crystal elements 15.

The scanning line driving circuit 20 outputs a scanning line driving signal having a switching period in which the switching element 12 is turned on and a holding period in which the switching element 12 is turned on for each column of scanning lines. The scanning line driving circuit 20 sequentially scans the scanning lines G ₁ , G ₂ , G ₃ to G _m to select one column of pixel columns for each horizontal period.

The signal line drive circuit 22 outputs a signal signal for a signal line of a predetermined timing which is substantially synchronized with the ON period of the switching element 12 for the signal lines of the respective rows. In other words, the display signals are output through the respective signal lines S ₁ , S ₂ , S ₃ to S _n . The signal line driving circuit 22 outputs the pixel voltage by the transistor 12 for one column of liquid crystal cells selected by the scanning line driving circuit 20 in one horizontal period.

The counter electrode driving circuit 24 outputs a driving signal for the counter electrode, and applies a common counter electrode voltage (Vcom) to all the liquid crystal cells by the counter electrode 14 formed on the second transparent substrate (not shown). 15.

One end of the auxiliary capacitor 16 is connected to the pixel electrode 13 connected to the drain of the transistor 12, and the other end of the auxiliary capacitor 16 is connected to the auxiliary capacitor line driving circuit 26. As shown in Fig. 1, in other words, the other ends of the storage capacitors 16 of the pixels 15 arranged in the respective columns are commonly wired to form a storage capacitor line connected to the auxiliary capacitance line drive circuit 26. Therefore, the auxiliary capacitance lines of the 1, 2, 3, and m columns are connected to the first output terminal to the mth output terminal of the auxiliary capacitance line drive circuit 26, respectively. Vcs1 to Vcsm are output from the first output terminal to the mth output terminal, respectively.

Further, in the above case, the pixel corresponding to the color display described in the liquid crystal display device 1 as a black-and-white display may be used.

Fig. 2 is a plan view showing a part of the first substrate 41 of the color liquid crystal display device 1 according to the first embodiment of the present invention, and Fig. 3(A) is a cross-sectional view taken along line XX of Fig. 2; 3(B) is a cross-sectional view showing the second substrate 42 including the portion along the YY line of FIG. 2 .

As shown in FIG. 2, on the first substrate 41, a plurality of scanning lines 44 and a plurality of signal lines 45 are extended in the column direction and the row direction, respectively. A thin film transistor 46 connected to the two lines 44 and 45 and a pixel electrode 47 driven by the thin film transistor 46 are disposed in the vicinity of each of the intersections of the two lines 44 and 45. Further, on the side opposite to the scanning line 44 with the pixel electrode 47 interposed therebetween, the auxiliary capacitance line 48 is overlapped with the pixel electrode 47 and arranged along the column direction.

As shown in FIG. 3(B), in the color liquid crystal display device 1, the first substrate 41 and the second substrate 42 which is located above the first substrate 41 and which serves as the counter substrate have a substantially square frame-shaped sealing material. (not shown), the liquid crystal 43 is sealed in a space defined between the sealing material and the two substrates 41 and 42.

Next, a specific structure of the thin film transistor 46 and the like will be described with reference to FIG. 3(A). A scanning line 44 including the gate electrode 51 is provided on the upper surface of the first substrate 41, that is, at a predetermined surface facing the surface of the second substrate 42, and the auxiliary capacitance line 48 is provided at the other predetermined portion. A gate insulating film 52 is provided on the entire surface thereof.

A semiconductor film 53 composed of intrinsic amorphous germanium is provided at a predetermined portion above the gate insulating film 52. On the upper surface of the semiconductor thin film 53, a channel protective film 54 is provided at a position more than the inner side of the intersection of the semiconductor thin film 53 and the gate electrode 51. Contact layers 55, 56 composed of n-type amorphous germanium are provided on both upper surface sides of the channel protective film 54 and on the upper surface of the semiconductor thin film 53 on both sides.

A drain electrode 57 is provided on the upper surface of one of the contact layers 55. A signal line 45 including the source electrode 58 is provided on the upper surface of the other contact layer 56 and on the upper surface of the gate insulating film 52.

The thin film transistor 46 is configured by the gate electrode 51, the gate insulating film 52, the semiconductor thin film 53, the channel protective film 54, the contact layers 55 and 56, the drain electrode 57, and the source electrode 58.

A cover film 59 composed of an insulating material is provided on the entire upper surface of the gate insulating film 52 including the thin film transistor 46 and the like. This cover film 59 can also be a planarization film. A contact hole 60 is provided in a portion corresponding to a predetermined portion of the gate electrode 57 of the cover film 59. A pixel electrode 47 is provided at a predetermined portion of the upper surface of the cover film 59. The pixel electrode 47 is formed of a transparent electrode composed of ITO. The pixel electrode 47 is connected to the drain electrode 57 via the contact hole 60.

Next, the second substrate 42 will be described with reference to the third (B) diagram. The black matrix 61 and the color filter elements 62R, 62G, and 62B of R, G, and B are provided at predetermined positions on the lower surface of the second substrate 42 (the surface facing the first substrate 41). Among them, the color filter elements 62R, 62G, 62B are disposed to face the corresponding pixel electrodes 47.

On the lower surface of the black matrix 61 and the color filter elements 62R, 62G, 62B, the counter electrode 63 is formed of a transparent electrode composed of ITO. The pixel capacitor portion is formed by the liquid crystal 43 sealed between the pixel electrode 47 and the counter electrode 63 disposed opposite thereto. In this case, since the area of the pixel electrode 47 is the same, the pixel capacitance of the pixel capacitance portion is the same.

Here, as shown in FIG. 2, among the auxiliary capacitance lines 48, the portion overlapping the pixel electrode 47 becomes the storage capacitor electrode 48a provided for each pixel. Then, the auxiliary capacitor 16 shown in Fig. 1 is formed by the portions thus overlapped. In other words, in the color liquid crystal display device 1 shown in FIGS. 2 and 3, the storage capacitor 16 is formed as a storage capacitor electrode 48a as a part of the wiring provided on the first substrate 41; The insulating films 52, 59 provided thereon; and the pixel electrodes 47 composed of transparent electrodes provided on the insulating films 52, 59.

On the other hand, the respective pixel electrodes 47 corresponding to the respective color filter elements 62R, 62G, and 62B are disposed on the same plane because they are provided on the cover film 59. Therefore, the gap size of each of the pixels of R, G, and B is d (refer to FIG. 3(B)).

It is to be noted that at least one circuit or all of the circuits of the scanning line driving circuit 20, the signal line driving circuit 22, and the auxiliary capacitance line driving circuit 26 can be formed in the thin film transistor which is connected to the pixel 15 of Fig. 1 as the switching element 12. Figs. 2 to 3 show the liquid crystal display device 1. For example, the thin film transistor 12 and each of the above-described driving circuits are formed on the first transparent substrate 41 using a low temperature polysilicon, and constitute a TFT array substrate. Here, the liquid crystal 43 is filled in the gap between the first substrate 41 and the second substrate 42.

Further, in the color liquid crystal display device 1 shown in FIGS. 2 and 3, the storage capacitor 16 is provided by the storage capacitor electrode 48a and the insulating films 52 and 59 and the pixel electrode 47 provided on the first substrate 41. Although it is formed, other structures may be employed in accordance with the pixel structure of the color liquid crystal display device 1.

Fig. 4 is a block diagram showing an equivalent circuit of a pixel structure of one column and three rows, Clc means a pixel capacitor, and Ccs means a capacitor 16. The additional characters of the switching element 12 indicate columns and rows, and the auxiliary capacitance lines of the first column are indicated by CS1.

Now, by applying a rectangular wave signal to the signal line and the counter electrode, and selecting the scanning line, the switching element 12 of the pixel 15 connected to the scanning line (G ₁ ) is turned on, and a voltage according to the display signal is applied. In the pixel electrode 13. That is, in the ON state, the storage capacitor line drive circuit 26 shown in Fig. 1 is in the first period of the auxiliary capacitor 16, that is, the storage capacitor electrode 17, in the first period of the drive signal for the counter electrode. The first voltage is applied. Next, a second voltage is applied to the p+1/2 period (here, p is 0 or a natural number) after the first cycle of the counter electrode driving signal, and the output is held during the p+1/2 period. Set to the signal of the open state. The drive signal for the counter electrode is outputted at a predetermined timing in accordance with the scanning line for each column.

Thereby, the absolute value of the potential difference between the pixel electrode 13 and the counter electrode 14 can be increased.

Fig. 5 is a waveform showing an example of a driving method of the liquid crystal display device 1 of the present invention, wherein (A) indicates a driving signal for the counter electrode, (B) indicates a driving signal for the auxiliary capacitance line, and (C) indicates a signal. The line drive signal, (D) represents the scan line drive signal, and (E) represents the voltage applied to the pixel 15 (the voltage difference between the pixel electrode 13 and the counter electrode 14) together with the voltage of the pixel electrode 13.

As shown in Fig. 5(A), the drive signal for the counter electrode corresponds to the pulse width of the drive signal for the scanning line, and the rectangular wave of the high level (VcomH) and the low level (VcomL) is repeated for the scanning line. Among the t0 to t1 and t5 to t6 in which the drive signal is ON, they are waveforms having amplitudes of a high level (VcomH) and a low level (VcomL), respectively. The waveform shown in Fig. 5(C) is an example of a signal line driving signal when the liquid crystal maximum voltage is applied. As shown in the fifth (D) diagram, the scanning line driving signal is a rectangular wave, and the period from t0 to t1 and t5 to t6 is the amplitude of the so-called high level in the charging period, and t1 to t5 and t6 to t10. The period becomes the amplitude of the low level of the hold period. In the time period from t1 to t5, it should be noted that it is not a few cycles shown in the figure, but is occupied by hundreds or more pulse waves. Similarly, the level of the counter electrode driving signal Vcom is in the period from t5 to t6, and attention should be paid to the inversion signal of the time period from t1 to t2. This will be repeated in each frame.

Here, in the drive signal for the counter electrode, the drive signal for the auxiliary capacitance line, and the drive signal for the signal line, t0 to t2 are referred to as a first cycle, and t2 to t4 are referred to as a second cycle. Further, one cycle of the scanning line drive signal is composed of a turn-on period (also referred to as a charge period) in which the switching element 12 is turned on, and a hold period in which the switching element 12 is turned off in a non-conductive state. .

The drive signal for the auxiliary capacitor line will be described.

As shown in FIG. 5(B), the auxiliary capacitance line drive signal Vcs is the first voltage when the scanning line drive signal is in the charging period (the period from t0 to t2), in other words, to the counter electrode 14 The same voltage Vcs1 (Vcs=VcomH) of the voltage VcomH is the same VcomL as the voltage applied to the counter electrode 14 at t1 to t2, and is applied to the opposite direction at the next t2 to t3. The second voltage (Vcs2) of the electrode 14 having a different voltage VcomH. At t3 to t5, the storage capacitor 16 is in a floating state by the auxiliary capacitance line drive circuit 26. In other words, selecting each scanning line, connected to the scanning lines (G ₁₎ of the pixel switch element 15 is turned on 12, 26 when the pixel electrode 13 based on the auxiliary capacitance line drive circuit the display signal voltage is applied to the For each of the storage capacitor lines, the first voltage is applied to the first period of the counter electrode driving signal. Next, in the half cycle (t2 to t3) after the ON period of the driving signal for the counter electrode (from t0 to t2), the auxiliary capacitance line driving circuit 26 applies the other half of the auxiliary capacitance line to the same period. The second voltage is a signal that is in an on state during the hold period (t3 to t6) after the half cycle. The auxiliary capacitance line drive circuit 26 applies the above-described voltage signal to the auxiliary capacitance lines of the respective columns by the drive signals for the scanning lines of the respective columns.

Thereby, the voltage difference generated by the pixel 15 is maintained until the next writing operation. As such, Vcom and Vcs respectively applied to the auxiliary capacitance line 48 and the counter electrode 14 are rectangular waves of 50% duty between the pulse waves of the scanning signal. The selection/charging operation is performed when the scanning line signal Vg (t0 to t1) is at a high level. After the levels of Vcom and Vcs are charged during t2~t3, when returning to the low level, Vcs will change from a high level to a low level, and a large voltage difference occurs in the liquid crystal 43. Thereafter (after t3), the voltage Vcs of the storage capacitor line 48 is set to be in a floating state in order to maintain a large voltage difference generated by the liquid crystal 43 of the pixel 15. In order to drive pixel 15 in alternating current (AC) mode, the high and low levels of these signals are reversed in the next frame. Therefore, in the next frame (refer to t5 to t10 in Fig. 5), the level of Vcs changes from VcomL to a high voltage during the period from t5 to t10.

Further, the period during which the second voltage is applied is not limited to a half period, and may be a p+1/2 period (here, p is 0 or a natural number). In the following description, the period in which the second voltage is applied will be described in a half cycle.

As shown in Fig. 5(B), when the drive signal for the auxiliary capacitance line is at t5 to t6, in other words, when the drive signal for the scan line is the charge period, it is the same voltage VcomL as that applied to the counter electrode 14. In the case of t6 to t7, the first voltage Vcs1 (Vcs1 = VcomH) which is the same as the voltage applied to the counter electrode 14 is applied and applied at the next t7 to t8. The second voltage (Vcs2) differs from the voltage (VcomL) of the counter electrode 14. At the time t8 to t10, at the other end of the storage capacitor 16, in other words, the storage capacitor line 48 including the storage capacitor electrode 17 is floated by the auxiliary capacitance line drive circuit 26.

The principle of operation of the driving method of the present invention will be described in more detail.

The capacitance (Clc) between the counter electrode 14 and the pixel electrode 13 and the capacitance (Ccs) between the pixel electrode 13 and the storage capacitor electrode 17 are fixed irrespective of changes in the dielectric constant of the liquid crystal. Further, the capacitance (Ccs) between the pixel electrode 13 and the storage capacitor electrode 17 is also fixed. The potential of the pixel electrode 13 when the charging of the pixel 15 is completed is Vpix1, the potential of the counter electrode 14 during charging is VcomW, and when the potential of the auxiliary capacitor electrode 17 during charging is Vcs1, In the pixel electrode 13 (Pix), charging is performed with an electric charge represented by Q = Clc × (Vpix1 - VcomW) + Ccs × (Vpix1 - Vcs1). Since the charging of the pixel 15 (for example, referring to t1 in Fig. 5) ends, the transistor 12 of the pixel 15 is turned off, so that the pixel 15 is in a floating state, and the Q is held until the next charging. For fixing. In the conventional example, the potential including the entire Vpix from this state matches the potential of the counter electrode 14 and vibrates as shown in Fig. 15.

Here, when only the voltage of the storage capacitor electrode 17 changes from Vcs1 to Vcs2, since Q and Clc and Ccs are fixed, the potential relationship changes shortly after charging. When the changed pixel potential is Vpix2, the relationship of Q=Clc×(Vpix1-VcomW)+Ccs×(Vpix1-Vcs1)=Clc×(Vpix2-VcomW)+Ccs×(Vpix2-Vcs2) is established, so The potential Vpix of the pixel electrode changes only Vpix2-Vpix1=Ccs/(Clc+Ccs)× (Vcs2-Vcs1). Since the voltage applied to the liquid crystal is Vpix-Vcom, Vpix2-Vpix1>0, that is, when Vcs2 is set as Vcs2-Vcs1>0 (refer to t7~t8 in FIG. 5), the voltage of the pixel 15 is boosted. . If Vcs2 < Vcs1 (refer to t2 to t3 in Fig. 5), the voltage is reduced. This is a phenomenon similar to the charge pump used for boosting inside the LSI, but the potential related aspect of the Vcom is different.

At the time of charging of the pixel 15, Vcs1 (corresponding to Vcom) is applied to the storage capacitor electrode 17, and after one cycle (that is, when the potential of the counter electrode becomes the same potential as that at the time of charging), t2~ When t3 (or t7~t8), grant Vcs2. In the other timings, the driving power supply of the storage capacitor electrode 17 causes the storage capacitor electrode 17 to be in an open state, in other words, to have a high impedance, and to set the storage capacitor line to a floating state. By performing such driving, the boost state of the pixel voltage (Vpix) due to the application of Vcs2 can be maintained during the sustain period. In other words, it is possible to increase the potential of the pixel 15 while exceeding the 4.8 V while using Vcs1 and Vcs2 in the voltage limit of the driver LSI.

Here, although the focus is on, when the voltage of the storage capacitor electrode 17 is changed from Vcs1 to Vcs2, Vcom is the same potential as that of the pixel 15 when it is charged. Vcs1 and Vcs2 are voltages that can be supplied together from the driver LSI (with a difference of Vs of 4.8V or less) can be realized in this timing. The p+1/2 period (p is 0 or a natural number) after the first cycle of the counter electrode driving signal indicates a period satisfying this condition.

In the first embodiment, the circuit operation similar to the charge pump for pushing up the pixel potential is changed as the potential of the storage capacitor electrode 17 is changed. Therefore, the liquid crystal can be driven with a voltage equal to or higher than the output voltage of the LSI. Since the auxiliary capacitance line 48 is separated from the counter electrode wiring, the signal necessary for such a boosting operation can be freely applied.

In the first embodiment, the storage capacitor electrode 17 is driven by wiring from the driver LSI. However, the driving of the thin film transistor composed of amorphous germanium or polycrystalline silicon may be added adjacent to the display region. The circuit is used to drive. In this case, since the number of wirings around the thin film transistor 12 and the liquid crystal display portion 10 is reduced, the effect of the LSI can be obtained without increasing the number of wirings.

In the first embodiment, the boosting of the storage capacitor 16 is performed by a voltage change applied to the storage capacitor electrode 17. When the configuration of the conventional pixel auxiliary capacitor is the same, even if other electrodes are added as the storage capacitor 16, the same effect can be obtained. Fig. 6, Fig. 7(A) and Fig. 7(B) show other embodiments of the present invention.

Fig. 6 is a block diagram showing the case where the storage capacitor 16 and the pixel auxiliary capacitor 18 are separately provided, and Figs. 7(A) and 7(B) are diagrams showing a specific pixel structure.

As shown in Fig. 6, the auxiliary capacitor is composed of the first and second storage capacitors 16, 18. In the case of this configuration, the first auxiliary capacitor 16 is simply referred to as a storage capacitor, and the second storage capacitor is referred to as a pixel auxiliary capacitor 18. Since the auxiliary capacitor electrode 17 forming the other end of the auxiliary capacitor 16 is connected to the CS terminal, the electrode at the other end of the pixel auxiliary capacitor 18 is connected to the COM electrode (also connected to the counter electrode 14), so the auxiliary capacitor 16 is provided. The voltage is applied independently of the electrodes of the pixel auxiliary capacitor 18. In other words, one end of the auxiliary capacitor 16 and the pixel auxiliary capacitor 18 are commonly connected to the pixel electrode 13, and the other ends of the auxiliary capacitor 16 and the pixel auxiliary capacitor 18 are individually disposed. While the other end of the auxiliary capacitor 16 is connected to the auxiliary capacitance line drive circuit 26, the other end of the pixel auxiliary capacitor 18 is connected to the counter electrode 14. In other words, the pixel auxiliary capacitor 18 is connected in parallel with the pixel 15.

In Fig. 7, (A) is a plan view of a pixel structure, and (B) is a cross-sectional view thereof. In this case, the auxiliary capacitor electrode 17 is formed at the other end of the auxiliary capacitor 16 disposed in each column of the pixels 15, and the auxiliary capacitor electrodes 17 are connected to each other by the auxiliary capacitor line 48. The electrode wiring of the auxiliary capacitor 16 can be disposed in parallel with the electrode wiring of the pixel auxiliary capacitor 18. Therefore, there is an advantage that the degree of freedom in pattern layout is increased. Patterns for forming opposing electrodes such as the auxiliary capacitor 16 and the pixel auxiliary capacitor 18 are arbitrarily designed. Thereby, the storage capacitor for holding the charge accumulated in the pixel is sufficient, and the storage capacitor 16 for increasing the voltage (Vpp, the voltage between the peaks) applied to the liquid crystal cell 15 can be formed.

Fig. 8 is a block diagram showing a second embodiment of the liquid crystal display device 30 of the present invention. The storage capacitor line drive circuit 26 is configured to include first and second storage capacitor driving transistors 31 and 32 connected to each of the storage capacitors 16 driven by the respective scanning lines (G ₁ to G _m ).

The n pixel electrodes 13 connected to the respective scanning lines of the scanning line driving circuit 20 are connected to one end of the auxiliary capacitor 16, and the other end of the auxiliary capacitor 16 is formed as a common electrode. This common electrode is provided with only the number of portions of the scanning line driving circuit 20. The wiring composed of the common electrode of the auxiliary capacitor 16 is referred to as a storage capacitor line (Cs1 to Csm) 48. In other words, each of the storage capacitor lines 48 is driven in a state of being separated from each other, and is driven by the first and second storage capacitor driving transistors 31 and 32 provided at both ends.

As shown in the figure, the first auxiliary capacitor driving transistor 31 is referred to as CTr ₁₁ to CTr _1m because m of scanning lines are arranged in a row along the scanning line driving circuit 20. In the same manner, the second storage capacitor driving transistor 32 is referred to as CTr ₂₁ to CTr _2m because m of the scanning lines are arranged along n rows of the switching elements 12.

The pixel electrode 13 is connected to the drain of the transistor 12. The counter electrode 14 which forms the liquid crystal cells 15 together with the pixel electrodes 13 corresponding to one row is connected to each other, and is connected to the second main electrode of the first storage capacitor driving transistor 31. The storage capacitor electrodes 17 which form the storage capacitor 16 together with the pixel electrodes 13 of the first row are connected to each other and to the first main electrode of the first storage capacitor driving transistor 31. The respective control electrodes of the first storage capacitor driving transistor 31 are connected to the corresponding scanning lines. The pixels in the second column and the third column are also constructed in the same manner. Then, the counter electrode 14 for the pixel auxiliary capacitor 18 is all connected to the counter electrode wiring (referred to as COM1) serving as the first common electrode. As shown in the figure, all of the second main electrodes of the second storage capacitor driving transistor 32 are connected to the second common electrode wiring (referred to as COM2). The pixels in the second column and the third column are also constructed in the same manner. In this way, the voltage of the counter electrode 14 as the other end electrode forming the pixel auxiliary capacitor 18 is constantly controlled to the voltage level of COM1. The voltage applied to the storage capacitor line 48 is controlled to the voltage level of COM2 by the switching states of the first storage capacitor driving transistor 31 and the second auxiliary capacitor driving transistor 32.

In the first storage capacitor driving transistor 31 of the i-th column, the first main electrode is connected to the storage capacitor line 48 connected to the auxiliary capacitor 16 of the i-th column, and the second main electrode is connected to the first common electrode. The counter electrode wiring (COM1) is connected, and the control electrode is connected to the scanning line Gi of the i-th column.

In the second storage capacitor driving transistor 32 of the i+2 column, the first main electrode is connected to the first main electrode and the storage capacitor 16 of the first storage capacitor driving transistor 31 of the i-th column. The auxiliary capacitance line 48 is connected to the second common electrode wiring (COM2), and the control electrode is connected to the scanning line G _{i+2 of} the i+2th column. Therefore, when n pixels 15 (15 ₁₁ to 15 1 _n ) in the first column are controlled, the first storage capacitor driving transistor CTr ₁₁ and the second storage capacitor driving transistor CTr _{23 are used} . Similarly, when controlling each pixel 15 of the i-th column, the transistor CTr ₁₁ and the transistor CTr _{r(i+2) are used} .

Further, when n pixels 15 in the _m- 1th column are controlled, the first storage capacitor driving transistor CTr _{1 (m-1)} and the second storage capacitor driving transistor CTr _{21 are used} . When n pixels in the mth column are controlled, the first storage capacitor driving transistor CTr _1m and the second storage capacitor driving transistor CTr _{22 are used} .

The auxiliary capacitance line drive circuit 26 is connected to the first and second storage capacitor driving transistors 31 and 32 for each scanning line, and the counter electrode wiring (COM1) is connected to the second main electrode of the first storage capacitor driving transistor 31. The second main electrode of the second storage capacitor driving transistor 32 is connected to the common electrode wiring (COM2). In a first scanning line G ₁ when the first storage capacitor electrode driving control electric crystal 31 will be connected to the scanning line G ₁ of the first column, the second storage capacitor electrode driving control electric crystal 32 will Connected to the scan line G _{3 of} the third column.

The inverted voltage of the counter electrode wiring (COM1) can be applied to the common electrode wiring (COM2). In this case, of course, the COM inversion signal generating circuit may be provided in the COM driver, but an inverter circuit composed of a thin film transistor (not shown) may be connected to the counter electrode driving circuit 24 to be inverted. The output of the circuit (COM2) is connected to the common electrode wiring and can be easily realized. Fig. 9 is a view schematically showing an equivalent circuit diagram of one pixel 15.

In Fig. 8, the scanning lines G ₁ , G ₂ , G ₃ ~ G _{m are} sequentially selected. Selected scanning line G ₁ when connected to the scanning line G switching element ₁ 12 is turned on (path) state, each pixel of the liquid crystal, and an auxiliary capacitor 1615 are charged to the signal line connected to S _1, S ₂ , the potential of S ₃ ~S _m . In this case, selection / charging period, the scanning lines G ₁ corresponding to the storage capacitor line 48 by the first storage capacitor line drive electric crystal CTr ₁₁ is applied to the voltage to the electrodes 14 (COM1). At this time, the auxiliary capacitor 16 is connected to the second storage capacitor line drive electric crystal CTr ₂₃ because the non-selected scanning line G _3, it is blocked (OFF) state. Therefore, Vcom2 does not affect the voltage of the auxiliary capacitor electrode 17 forming the auxiliary capacitor 16. The first storage capacitor driving electric crystal CTr ₁₁ is driven by the auxiliary capacitance electrode 17 only.

During the end of the selection scan lines G ₁ / charging in a non-selected state, the scanning lines G ₂ being selected when the first and second auxiliary capacitor driving electric crystal CTr ₁₁ and CTr ₂₃ gate lines as a very low level, so Together they become disconnected. Thus, the storage capacitor electrode 17 and the pixel electrode 13 in a floating state, the holding time of the scanning line G in the charge of _a selected charging, and to maintain the same potential (COM1) electrode 14. Thereby, even if Vcom1 changes, the voltage difference between the liquid crystal 15 and the storage capacitor 16 can be maintained in the same state.

When the selection/charging period of the scanning line G ₂ is completed and the non-selected state is reached, when the scanning line G ₃ is selected, the second storage capacitor driving transistor CTr _{23 is} turned on. This is because the scanning line G ₃ connected to the gate of the second storage capacitor driving transistor CTr ₂₃ is at a high level.

Whereby, ₂₃ will be applied to the auxiliary capacitance line 1 in 48 (Cs1) by the second storage capacitor electric crystal driving voltage Vcom2 CTr as the line COM2. The second auxiliary capacitor driving electric voltage is applied to the crystal CTr ₂₃ (COM2) from the auxiliary capacitance line drive circuit 17 via the auxiliary capacitor electrode. At this time, the potential of COM2 is a potential different from that of COM1, and the potential of the storage capacitor electrode 17 is changed from COM1 to COM2. Therefore, at this time, the voltage Vcom1 is supplied to the counter electrode 14 of the liquid crystal cell 15 in one column, and the voltage Vcom2 is supplied to the auxiliary capacitance line 48 (Cs1). This potential change spreads the potential difference between the pixel electrodes 13 and COM1 via the auxiliary capacitance line 48. That is, the liquid crystal application voltage is raised by an effect similar to that of the charge pump.

As above, after the end of the scan lines G ₃ is selected, then the period until the selection scan lines G ₁ to be the holding period, the first and second auxiliary capacitor driving electric crystal CTr ₁₁ and CTr ₂₃ continues the off-state together. That is, since the writing of the charges charged COM2 is held in the storage capacitor 16, in order to maintain the effect of the scanning lines of the pixel voltage step-up state on the ₁ G. The boosting system of the pixel 15 is maintained in a state where a potential difference from COM1 is generated. This is because the auxiliary capacitance lines 48 (Cs1, Cs2 to Csm) are in a floating state.

Fig. 10 is a waveform diagram showing a driving method of the liquid crystal display device 30 of the present invention, wherein (A) indicates a driving signal for the counter electrode, (B) indicates a driving signal for the second common electrode (Vcom2), and (C) indicates a signal. line driving signal, (D) represents a scanning line G drive signal _1, (E) represented by the scanning line G drive signal _2, (F) denotes a scanning line G driving signal _3, (G) represents a voltage applied to the auxiliary capacitance line The auxiliary capacitance line drive signal of 48, (H) represents the voltage of the pixel electrode 13 of the pixel 15, and the voltage difference between the liquid crystal cell 15 generated between the pixel electrode 13 and the counter electrode 14.

As shown in Fig. 10(A), the drive signal (VcomL) for the counter electrode is a rectangular wave, and the drive signal (Vcom2) for the second common electrode is an inverted signal of the drive signal (Vcom1) for the counter electrode (see the 10 (B) map). As shown in Fig. 10(C), the signal line drive signal is a rectangular wave in which the drive signal for the counter electrode is inverted. As shown in Figs. 10(D) to 10(F), the scanning line driving signal is a rectangular wave having a high level of amplitude during the selection/charging period. In the scanning line drive signals G _1, t0 ~ t1 and t5 ~ t6 having a high level of charge to become an amplitude on, other than the above-described period is all turned OFF, in other words, having a low level of amplitude of the waveform. Similarly, in the scan line drive signal G ₂ , t1 to t2 and t6 to t7 have amplitudes at which the charge is turned on, and all of the above-described turn-on periods are turned off, in other words, have a low level amplitude. Waveform. In the _third aspect of the scanning line driving signal G, t2 ~ t3 and t7 ~ t8 having a high level of charge to become an amplitude on, other than the above-described period is all turned OFF, in other words, having a low level of amplitude of the waveform. A period in which the lower level of the scanning line driving signal is set is referred to as "holding time".

Section 10 (G) are diagrams FIG applied to the storage capacitor electrode 17 waveforms, a scan line driving signal G ₁ is the time (t0 ~ t1) is turned on, the first auxiliary capacitor 31 will crystal driving power is turned on, this period Vcom1 is applied to the auxiliary capacitor electrode 17. When the scanning line driving signal G ₃ is turned on (t2 to t3), the second auxiliary capacitor driving transistor 32 is turned on, during which Vcom2 is applied to the auxiliary capacitor electrode configured to face the pixel electrode 13. 17. In the case of t3 to t5 other than the above-described period, since the first and second storage capacitor driving transistors 31 and 32 are not turned on, the storage capacitor electrode 17 is in a floating state. By this drive signal is set to the potential (Vcs of) the storage capacitor electrode 17 becomes a driving signal lines G ₁ and the second auxiliary capacitor driving power is applied to the scanning line is applied to the first storage capacitor driving electric crystals 31 The scanning line of the crystal 32 uses a waveform in which the signal center fluctuates up and down in each cycle of the driving signal G ₃ . For the same reason as described above, the pixel potential can be boosted by this change.

The 10th (H) figure and the pixel electrode 13 together represent the waveform of the voltage difference of the liquid crystal pixels 15. As shown in the figure, during the period from t2 to t3, the waveform of the pixel electrode 13 changes due to the influence of the voltage of the auxiliary capacitance line 48, and the voltage applied to the pixel 15 during the period from t3 to t5 is increased. Thereby, the boosting effect of increasing the absolute value of the potential difference between the pixel electrode 13 and the counter electrode 14 by using the auxiliary capacitance line driving circuit 26 can be obtained.

In the storage capacitor line drive circuit 26 of the second embodiment, signals from the original scanning line drive are used as control signals for the first and second storage capacitor driving transistors 31 and 32. Similarly, the voltage (Vcom1) applied to the main electrode of the first storage capacitor driving transistor 31 can be supplied from the counter electrode driving circuit 24. Further, Vcom2 applied to the main electrode of the second storage capacitor driving transistor 32 is supplied with an inverted signal from the counter electrode driving circuit 24. Therefore, in the storage capacitor line drive circuit 26 of the second embodiment, it is easy to form a signal for the auxiliary capacitor drive. In addition, the internal and external wiring for the new specification of the auxiliary capacitor drive is not required, and the drive LSI or the liquid crystal display device which does not require the auxiliary capacitor drive terminal of the liquid crystal display device 30 to be newly installed in the liquid crystal display device 30 is generated. The beneficial effect of the 30 circuit.

The waveforms of Vcom1 and Vcom2 and the values of these can have many patterns and variations. In the second embodiment, the signal driven by the storage capacitor is used as the Vcom inversion signal, but the signal may be a DC voltage (VcomDC) corresponding to the amplitude center of Vcom. In this case, there is an effect that the supply of the signal (Vcom2) becomes easier. Of course, it is also possible to reduce the amplitude while maintaining the timing of the Vcom inversion and the center of the amplitude. The state where the amplitude becomes 0 is the minimum value, which is VcomDC.

Further, the amplitude of Vcom2 shown in Fig. 10 can be changed to a value smaller than the value shown in Fig. 10(B). With respect to Vcom2, as long as the voltage applied to the liquid crystal cell 15 is boosted, the voltage or period of Vcom2 can be deformed a lot.

In the second embodiment, the pixel auxiliary capacitor (Cp) 18 may be different from the boosting auxiliary capacitor (Cs) 16 as in the first embodiment. As shown in FIGS. 6 and 7 , another auxiliary capacitor may be provided in parallel with the pixel-accumulated capacitor 18 that forms the liquid crystal. This example is shown in Figure 11. Fig. 11 is a block diagram showing a case where the pixel auxiliary capacitor 18 and the auxiliary capacitor 16 are separately provided, and Fig. 12 is a view showing a specific pixel configuration.

As shown in Fig. 11, one end of the pixel auxiliary capacitor 18 and the auxiliary capacitor 16 is commonly connected to the pixel electrode 13, and the other end of the pixel auxiliary capacitor 18 and the auxiliary capacitor electrode 17 at the other end of the auxiliary capacitor 16 are respectively They are individually arranged. In the illustrated case, the other end of the pixel auxiliary capacitor 18 is connected to the counter electrode 14, and the other end of the auxiliary capacitor 16 is connected to the auxiliary capacitance line drive circuit 26.

In Fig. 12, (A) is a plan view of a pixel structure, and (B) is a cross-sectional view thereof. In this case, the auxiliary capacitance line 48 is formed at the other end of the storage capacitor 16 of the pixels 15 arranged in each column. This auxiliary capacitance line 48 can be arranged in parallel with the pixel auxiliary capacitance line. Therefore, there is an advantage that the degree of freedom is increased in addition to the pattern design.

As shown in FIGS. 11 and 12, the structure of the auxiliary capacitor 16 and the pixel auxiliary capacitor 18 associated with each pixel is the same as that shown in FIGS. 6 and 7.

In the above example, the independently driven auxiliary capacitance line 48 is disposed in parallel with the capacitance line connected to the opposite electrode of the pixel capacitor. Therefore, there is an advantage that the degree of freedom is increased in addition to the pattern design. Since the pattern for forming the opposite electrode of the capacitor and the pattern of the capacitor line can be arbitrarily designed, the degree of freedom in pattern design can be achieved. This is the advantage. For example, the patterns of the electrodes for forming the auxiliary capacitor 16 and the pixel auxiliary capacitor 18 are arbitrarily designed. With this configuration, the storage capacitor for holding the charge accumulated in the pixel 15 can be made sufficient, and the voltage applied to the liquid crystal cell 15 (the voltage between Vpp and the peak) can be increased to obtain the pixel electrode 13 . Combined with the capacitance generated by the auxiliary capacitor electrode 17.

Here, the auxiliary capacitance line drive circuit 26 can be disposed adjacent to the display unit 10. As shown in FIGS. 2 and 3, the auxiliary capacitance line drive circuit 26 can be formed on the first transparent substrate 41 using an amorphous germanium or a polysilicon as in the case of the switching element 12 adjacent to the pixel 15, and constitutes a TFT array. Substrate.

In the embodiment of the liquid crystal display devices 1 and 30 described above, each of the storage capacitor lines 48 intersects with the signal line 45.

Fig. 13 is a schematic cross-sectional view showing the intersection of the signal line 45 and the auxiliary capacitance line 48 of the pixel shown in Fig. 2. Fig. 13 is a cross-sectional view taken along line A-A of Fig. 2, and since each auxiliary capacitance line 48 intersects with the signal line 45, a parasitic capacitance Cst is formed at each intersection.

Fig. 14 is an equivalent circuit diagram showing a parasitic capacitance Cst in the liquid crystal display device 30. As shown in Fig. 14, since the parasitic capacitance Cst is formed at the intersection of the auxiliary capacitance line 48 and the signal line 45, the floating auxiliary capacitance line 48 has the parasitic capacitance C (the parasitic capacitance occurring in each intersection). × Synthetic capacitance of the number of signal lines n. Therefore, the auxiliary capacitance line 48 is subjected to a potential fluctuation due to the influence of the average potential of the signal line 45 by the combined capacitance Cn. The potential variation of the storage capacitor line 48 is caused by a change in the voltage of the pixel column connected to the storage capacitor line 48. Therefore, the signal line potential, that is, the image data, causes the pixel to be in the auxiliary capacitance line 48. The voltage is affected.

Next, a description will be given of a modification of the pixel which can block the parasitic capacitance generated at the intersection of the signal line 45 and the auxiliary capacitance line 48 in the liquid crystal display devices 1 and 30.

Fig. 15 is a partial perspective plan view showing a configuration of a modification of a pixel, and Fig. 16 is a cross-sectional view taken along line X-X of Fig. 15.

As shown in Fig. 15, the pixel 70 is provided with a parasitic capacitance shielding wiring 72 for shielding the parasitic capacitance Cst generated between the auxiliary capacitance lines 48 of the signal line 45. As shown in Fig. 15, the parasitic capacitance shielding wiring 72 has a linear portion 72a and a convex portion 72b.

The parasitic capacitance shielding wiring 72 has a linear portion 72a disposed in the region between the auxiliary capacitance line 48 and the switching element 46 on the side of the auxiliary capacitance line 48 and the auxiliary capacitance electrode 48a and parallel, and parallel to the auxiliary capacitance line. 48; and a convex portion 72 that covers an intersection of the auxiliary capacitance line 48 and the signal line 45. The convex portion 72b is elongated so as to be vertically bent from the signal straight portion 72a toward the upper side of the paper surface. Therefore, the parasitic capacitance shielding wiring 72 is disposed so as to pass through the intersection of the signal line 45 of each row and the auxiliary capacitance line 48 of each column. Further, since the convex portion 72b is provided at the intersection of the signal line 45 and the auxiliary capacitance line 48, it is also simply referred to as an intersection portion.

As shown in Fig. 16, in the pixel 70, the gate insulating film 52 formed on the first substrate 41 of the liquid crystal display device 1 shown in Figs. 2 and 3 is referred to as the first gate insulating film 74. A two-layer structure in which the second gate insulating film 75 is laminated in this order forms a pattern of the parasitic capacitance shielding wiring 72 on the first gate insulating film 74. The formation of the storage capacitor line 48 on the first substrate 41 is the same as that of the liquid crystal display device 1.

In the pixel 70, the storage capacitor line 48 and the signal line 45 formed on the gate insulating film 52 of the liquid crystal display device 1 shown in FIGS. 2 and 3 are formed on the second gate insulating film 75. The parasitic capacitance shielding wiring 72 is formed in accordance with each of the storage capacitor lines Cs1 and Cs2 to Csm shown in FIG. 1 .

Fig. 17 is a schematic cross-sectional view showing the capacitance generated at the intersection of the parasitic capacitance shielding wiring 72 and the signal line by the addition of the parasitic capacitance shielding wiring 72 of the pixel 70. As shown in the figure, the auxiliary capacitance line 48 and the parasitic capacitance shielding line 72 face each other with the first gate insulating film 74 interposed therebetween, so that the first intersection portion is formed between the auxiliary capacitance line 48 and the parasitic capacitance shielding line 72. Capacitor 76. Further, since the parasitic capacitance shielding wiring 72 and the signal line 45 face each other with the second gate insulating film 75 interposed therebetween, the second intersecting portion capacitance 77 is generated between the parasitic capacitance shielding wiring 72 and the signal line 45. Therefore, between the auxiliary capacitance line 48 and the signal line 45, the first and second intersection capacitances 76 and 77 are formed together with the parasitic capacitance shielding wiring 72, but they are not formed on the auxiliary capacitance line 48 and Parasitic capacitance directly coupled between signal lines 45.

The parasitic capacitance shielding wiring 72 is formed in accordance with each of the storage capacitor lines Cs1 and Cs2 to Csm shown in FIG. 1 , but a common potential is applied to all of the m strips. The common potential applied to the m parasitic capacitance shielding wires 72 can be a fixed potential such as GND. The material of the parasitic capacitance shielding wiring 72 is preferably a low-resistance metal in order to prevent the delay of the voltage signal to be applied to the common potential.

As explained above, in the pixel 70, the unfavorable parasitic capacitance generated between the auxiliary capacitance line 48 and the signal line 45 is removed. Then, as described above, the boosting effect of the auxiliary capacitance lines 48 (Cs1, Cs2 to Csm) in the floating state is utilized because the potential of the signal line 45 is not received by the parasitic capacitance shielding wiring 72. The influence of the change makes it possible to stabilize and maintain the boost state of the pixel 70.

The potential of the parasitic capacitance shielding wiring 72 of the pixel 70 is set to a fixed potential such as GND, but may be a voltage (COM1) applied to the counter electrode 14. In this case, a capacitance is formed in a region where the parasitic capacitance shielding wiring 72 and the pixel electrode 47 overlap. This capacitor has an effect of stabilizing the potential of the pixel 70 in the same manner as the conventional auxiliary capacitor for pixels.

The pixel 70 can be produced by the following manufacturing method.

A metal layer is deposited on the first substrate 41, and a pattern of the gate electrode 51 and the auxiliary capacitance line 48 is formed by patterning. As the metal layer, a light-shielding chromium, a chromium alloy, aluminum, an aluminum alloy, molybdenum or the like can be used.

Next, the first gate insulating film 74 of a predetermined thickness is deposited so as to cover the entire surface of the first substrate 41 on which the gate electrode 51 and the auxiliary capacitance line 48 are formed. Similarly to the gate insulating film 52, the first gate insulating film 74 is made of an insulating material such as tantalum nitride or hafnium oxide.

Next, a metal layer is deposited on the first gate insulating film 74, and the parasitic capacitance shielding wiring 72 is formed by patterning. The material of the parasitic capacitance shielding wiring 72 can be the same material as the metal layer of the gate electrode 51 and the auxiliary capacitance line 48.

The second gate insulating film 75 having a predetermined thickness is deposited on the entire surface of the first gate insulating film 74 forming the pattern of the parasitic capacitance shielding wiring 72. Similarly to the gate insulating film 52, the second gate insulating film 75 may be made of an insulating material such as tantalum nitride or tantalum oxide, or may be the same material as the first insulating film 74. The subsequent steps may be the same as the manufacturing steps described in the liquid crystal display device 1 of Fig. 2.

Next, other pixels 80 will be described in addition to the liquid crystal display devices 1 and 30.

Fig. 18 is a partial perspective plan view showing the constitution of the pixel 80, and Fig. 19 is a sectional view taken along line X-X of Fig. 18.

As shown in the figure, in the pixel 80, the parasitic capacitance shielding wiring 82 is composed of a linear portion 82a which is disposed in parallel with the auxiliary capacitance line 48 on the first substrate 41, and a convex portion 82b. A region of the intersection of the auxiliary capacitance line 48 and the signal line 45 on the second gate insulating film 75. A contact hole 84 for exposing the parasitic capacitance shielding wiring 82 is disposed on the first gate insulating film 74. The convex portion 82b of the parasitic capacitance shielding wiring is disposed on the second gate insulating film 75, and is connected to the linear portion 82a of the parasitic capacitance shielding wiring by the contact hole 84.

Fig. 20 is a schematic cross-sectional view showing the capacitance generated in the intersection of the parasitic capacitance shielding wiring 82 and the signal line 45 of the pixel 80.

As shown in the figure, since the auxiliary capacitance line 48 and the convex portion 82b of the parasitic capacitance shielding wiring face each other with the first gate insulating film 74 interposed therebetween, the auxiliary capacitance line 48 and the parasitic capacitance shielding wiring portion 82b are A first intersection capacitor 76 is generated. In addition, since the convex portion 82b of the parasitic capacitance shielding wiring and the signal line 45 face each other with the second gate insulating film 75 interposed therebetween, a second portion is generated between the convex portion 72 of the parasitic capacitance shielding wiring and the signal line 45. Intersection capacitor 77. Therefore, between the auxiliary capacitance line 48 and the signal line 45, the first and second intersection capacitances 76, 77 are formed together with the parasitic capacitance shielding wiring 82, but are not formed in the auxiliary capacitance line 48 and A parasitic capacitance Cst directly coupled between the signal lines 45. The convex portion 82 of the parasitic capacitance shielding wiring is connected to the linear portion 82a of the parasitic capacitance shielding wiring by the contact hole 84. Therefore, the auxiliary capacitance line 48 and the signal line 45 are shielded by the parasitic capacitance in the same manner as the pixel 70. 82 shaded.

In the eighteenth diagram, the contact hole 84 is formed on the overlapping portion between the signal line 45 and the parasitic capacitance shielding wiring 82. However, this is not a requirement, and it can be formed on the parasitic capacitance shielding wiring 82. In any position.

In the above-described embodiment, similarly to the parasitic capacitance shielding wiring 72 of the pixel 70, a fixed potential such as GND or a voltage (COM1) applied to the counter electrode 14 is applied to the parasitic capacitance shielding wiring 82 of the pixel 80. Accordingly, since the parasitic capacitance is eliminated by the provision of the shielding wire 82 is affected by the signal lines _{S 1, S 2, S 3} ~ S n of potential variation, it is possible to stabilize and maintain the boosting state of the pixel 80.

In the above-described embodiment, when the same potential as that of the counter electrode 14 is applied to the parasitic capacitance shielding wiring 82, the effect of adding a storage capacitor for a conventional pixel is increased, and the stability of the potential of the pixel 80 is improved.

The pixel 80 of the embodiment shown in Fig. 18 can be manufactured in the following manner.

First, the same low-impedance conductive film is used on the first substrate 41 to form a pattern of the auxiliary capacitance line 48 and the linear portion 82a of the parasitic capacitance shielding wiring. Next, the first gate insulating film 74 is deposited to a predetermined thickness, and a contact hole 84 is provided in the linear portion 82a of the parasitic capacitance shielding wiring.

Then, the electrode layer which is the convex portion 82b of the parasitic capacitance shielding field is deposited to a predetermined thickness, and a pattern which is connected to the linear portion 82a of the parasitic capacitance shielding wiring is formed. The material of the convex portion 82b of the parasitic capacitance shielding wiring can be electrostatically shielded. therefore. The convex portion 82b of the parasitic capacitance shielding wiring does not need to use a low-impedance metal for preventing the delay of the voltage signal as in the parasitic capacitance shielding wiring 72 of the pixel 70 shown in Fig. 15, and can be transparent using ITO or the like. Conductive film. Thereby, compared with the above pixel 70, the aperture efficiency of the pixel 80 is further improved.

Next, the second gate insulating film 75 is deposited over the entire thickness of the first gate insulating film 74 with a predetermined thickness. After this step, the manufacturing steps described in the liquid crystal display device of Fig. 2 may be performed in the same manner.

Further, in the above-described fifth, tenth, and twenty-fourth drawings, care must be taken that the parasitic capacitance generated between the gate and the drain of the transistor 12 is not explicitly described. However, as shown by Vpt in Fig. 26, in fact, it is self-evident that the small voltage drop generated by the parasitic capacitance should be considered in addition to appropriately determining the driving waveform.

The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention, and it is obvious that the invention is also included in the scope of the invention.

1, 30. . . Liquid crystal display device

10. . . Display department

12, 46. . . Switching element (thin film transistor)

13, 47. . . Pixel electrode

14, 63. . . Counter electrode

15, 70, 80. . . Pixel

16. . . Auxiliary capacitor

17. . . Auxiliary capacitor electrode

18. . . Pixel auxiliary capacitor

20. . . Scan line driver circuit

twenty two. . . Signal line driver circuit

twenty four. . . Counter electrode driving circuit

26. . . Auxiliary capacitor line driver circuit

31. . . The first auxiliary capacitor driving transistor

32. . . Second auxiliary capacitor driving transistor

41. . . First substrate

42. . . Second substrate

43. . . liquid crystal

44. . . Scanning line

45. . . Signal line

48. . . Auxiliary capacitor line

51. . . Gate electrode

52. . . Gate insulating film

53. . . Semiconductor film

54. . . Protective film

55, 56. . . Contact layer

57. . . Bipolar electrode

58. . . Source electrode

59. . . Cover film (planar film)

60, 84. . . Contact hole

61. . . Black matrix

62. . . Color filter element

72, 82. . . Parasitic capacitance shielding wiring

72a, 82a. . . Straight line

72b, 82b. . . Convex

74. . . First gate insulating film

75. . . Second gate insulating film

76. . . 1st intersection capacitance

77. . . 2nd cross capacitance

Fig. 1 is a block diagram showing the configuration of a liquid crystal display device of the present invention.

Fig. 2 is a plan view showing a part of a first substrate of the color liquid crystal display device of the first embodiment of the present invention.

Fig. 3(A) is a cross-sectional view taken along line X-X of Fig. 2.

Fig. 3(B) is a cross-sectional view showing the second substrate including a portion along the Y-Y line of Fig. 2;

Fig. 4 is a block diagram showing an equivalent circuit of a pixel structure of one column and three rows.

Fig. 5 is a waveform showing an example of a driving method of the liquid crystal display device 1 of the present invention, wherein (A) indicates a driving signal for the counter electrode, (B) indicates a driving signal for the auxiliary capacitance line, and (C) indicates a signal. The line drive signal, (D) represents the scan line drive signal, and (E) represents the voltage applied to the pixel (the voltage difference between the pixel electrode and the counter electrode) together with the voltage of the pixel electrode.

Fig. 6 is a block diagram showing the arrangement of the pixel auxiliary capacitor and the auxiliary capacitor, respectively.

Fig. 7(A) is a plan view showing a pixel structure.

The seventh (B) diagram shows a cross-sectional view of the pixel structure.

Fig. 8 is a block diagram showing a second embodiment of the liquid crystal display device of the present invention.

Fig. 9 is a schematic diagram showing an equivalent circuit diagram of one pixel.

Fig. 10 is a waveform diagram showing a driving method of a liquid crystal display device of the present invention, wherein (A) indicates a driving signal for a counter electrode, (B) indicates a driving signal for a second common electrode (Vcom2), and (C) indicates a signal line. denotes a scanning line G-drive signal _1, (E) driving signal, (D) represents a scanning line G drive signal _2, (F) represents the driving signal of the scan lines G ₃ is, (G) represents a voltage applied to the auxiliary capacitor line The auxiliary capacitance line drive signal, (H) represents the voltage of the pixel electrode of the pixel, and the voltage difference between the liquid crystal cells generated between the pixel electrode and the counter electrode.

Fig. 11 is a block diagram showing the arrangement of the pixel auxiliary capacitor and the auxiliary capacitor, respectively.

Fig. 12 is a view showing a specific pixel structure of Fig. 11.

Fig. 13 is a schematic cross-sectional view showing the intersection of the signal line and the auxiliary capacitance line of the pixel shown in Fig. 2.

Fig. 14 is an equivalent circuit diagram showing a parasitic capacitance Cst in a liquid crystal display device.

Fig. 15 is a partial perspective plan view showing the configuration of a modification of the pixel.

Fig. 16 is a sectional view taken along line X-X of Fig. 15.

Fig. 17 is a schematic cross-sectional view showing the capacitance generated at the intersection of the parasitic capacitance shielding wiring and the signal line by the addition of the parasitic capacitance shielding wiring of the pixel.

Figure 18 is a partial perspective plan view showing the composition of pixels.

Figure 19 is a cross-sectional view taken along line X-X of Figure 18.

Fig. 20 is a schematic cross-sectional view showing the capacitance generated in the intersection of the parasitic capacitance shielding wiring and the signal line of the pixel.

Fig. 21 is a view schematically showing the structure of one pixel component of a conventional liquid crystal display device.

Figure 22 is a diagram schematically showing the structure of a column of pixels.

Fig. 23 is a view showing a waveform applied to a pixel.

Fig. 24 is a block diagram of a liquid crystal display device disclosed in Patent Document 1.

Fig. 25 is a timing chart showing the operation of the liquid crystal display device of Patent Document 1, (A) showing the gate signal output from each scanning line, and (B) showing the auxiliary capacitance line driving voltage output from the auxiliary capacitance line driving circuit. Variety.

Fig. 26 is a waveform diagram of voltages applied to respective pixels of the liquid crystal display device of Patent Document 1.

10. . . Display department

12. . . Switching element

13. . . Pixel electrode

14. . . Counter electrode

15. . . Pixel

16. . . Auxiliary capacitor

20. . . Scan line driver circuit

twenty two. . . Signal line driver circuit

twenty four. . . Counter electrode driving circuit

26. . . Auxiliary capacitor line driver circuit

Claims (26)

A liquid crystal display device comprising: a display portion, which is composed of a scan line composed of a plurality of columns (here, the column is an arbitrary natural number of 1≦i≦m); a signal line consisting of a plurality of lines (here, the line is an arbitrary natural number of 1≦j≦n); a switching element disposed at an intersection of the scan line and the signal line; and a pixel electrode connected to an output end of the switching element a counter pixel; a pixel matrix of m columns × n rows, wherein a liquid crystal cell is disposed between the pixel electrode and the counter electrode; and an auxiliary capacitor having one end connected to an output end of the switching element; The auxiliary capacitance line is composed of a plurality of columns connected to the switching elements of the respective columns and having the other ends of the auxiliary capacitors of the respective columns become common; and the scanning line driving circuit has a switch for the scanning lines of the respective columns. a scanning line driving signal for the on-time and the off-hold period; the signal line drive circuit outputs a signal line drive signal to the signal lines of the respective rows; and the counter electrode drive circuit Counter electrode And outputting a driving signal for the counter electrode; and a storage capacitor line driving circuit that outputs a driving signal for the auxiliary capacitance line to the auxiliary capacitance line of each of the columns; and the display unit includes the first and second substrates, the scanning line, and a signal line is disposed on the first substrate, and the opposite electrode is disposed The auxiliary capacitor line drive circuit applies a first voltage to the auxiliary capacitor line in the first period of the counter electrode driving signal, and is the first driving signal for the counter electrode. The second voltage is applied to the p+1/2 period (here, p is 0 or a natural number) after the period, and for each of the scanning lines of the above columns, in the holding period after the p+1/2 period. The drive signal outputs a signal that is set to an on state. The liquid crystal display device of claim 1, wherein the auxiliary capacitance line driving circuit is composed of first and second driving transistors connected to each of the storage capacitor lines, and the first driving transistor The first main electrode is connected to the other end of the auxiliary capacitor, and the second main electrode of the first driving transistor is connected to the counter electrode wiring (COM1) serving as the first common electrode, and the first driving transistor is The control electrode is connected to the scanning line (G _i ) of the i-th column, and the first main electrode of the second driving transistor is connected to the first main electrode of the first driving transistor, and the second driving transistor is The second main electrode is connected to the second common electrode wiring (COM2), and the control electrode of the second driving transistor is connected to the scanning line (G _i+2 ) of the i+2th column. For example, the liquid crystal display device of claim 1 or 2, wherein The auxiliary capacitor is composed of first and second auxiliary capacitors, one end of the first and second auxiliary capacitors is connected to the pixel electrode, and the other end of the first auxiliary capacitor is connected to the auxiliary capacitor line drive circuit, and The other end of the second auxiliary capacitor is connected to the counter electrode. The liquid crystal display device of claim 1, wherein the auxiliary capacitor is composed of: a wiring provided on the first substrate; an insulating film provided on the wiring; and an insulating film provided on the insulating film Transparent electrode. The liquid crystal display device of claim 1 or 2, wherein the auxiliary capacitance line driving circuit is disposed adjacent to the display portion, and the auxiliary capacitance line driving circuit is a film using amorphous germanium or polysilicon. The crystal is composed of. A liquid crystal display device comprising: a display portion, which is composed of a scan line composed of a plurality of columns (here, the column is an arbitrary natural number of 1≦i≦m); a signal line consisting of a plurality of lines (here, the line is an arbitrary natural number of 1≦j≦n); a switching element disposed at an intersection of the scan line and the signal line; and a pixel electrode connected to an output end of the switching element a counter pixel; a pixel matrix of m columns × n rows, wherein a liquid crystal cell is disposed between the pixel electrode and the counter electrode; and an auxiliary capacitor having one end connected to an output end of the switching element; The auxiliary capacitance line is composed of a plurality of columns connected to the switching elements of the respective columns and having the other ends of the auxiliary capacitors of the respective columns become common; the scanning line driving circuit has a switch for the scanning lines of the respective columns a scanning line driving signal for the on-time and the off-hold period; the signal line drive circuit outputs a signal line drive signal to the signal lines of the respective rows; and the counter electrode drive circuit Counter electrode And outputting a driving signal for the counter electrode; and a storage capacitor line driving circuit that outputs a driving signal for the auxiliary capacitance line to the auxiliary capacitance line of each of the columns; and the auxiliary capacitance line driving circuit is connected to each of the auxiliary capacitance lines The first and second driving transistors are configured, and the first main electrode of the first driving transistor is connected to the other end of the auxiliary capacitor, and the second main electrode of the first driving transistor is first The counter electrode wiring (COM1) of the common electrode is connected, the control electrode of the first driving transistor is connected to the scanning line (G _i ) of the i-th column, and the first main electrode of the second driving transistor and the first The first main electrode of the driving transistor is connected, the second main electrode of the second driving transistor is connected to the second common electrode wiring (COM2), and the control electrode of the second driving transistor and the i+2 The scanning line (G _i+2 ) of the column is connected, and the auxiliary capacitance line driving circuit applies a first voltage to the auxiliary capacitor line in the first period of the driving signal for the counter electrode, and the driving signal for the counter electrode After the first cycle The second voltage is applied to the p+1/2 period (here, p is 0 or a natural number), and the driving signal for each scanning line of each of the above columns is matched in the holding period after the p+1/2 period. The output is signaled to the on state. The liquid crystal display device of claim 6, wherein the auxiliary capacitor is composed of first and second auxiliary capacitors, and one of the first and second auxiliary capacitors is connected to the pixel electrode, and the first auxiliary The other end of the capacitor is connected to the auxiliary capacitance line drive circuit, and the other end of the second auxiliary capacitor is connected to the counter electrode. The liquid crystal display device of the sixth aspect or the seventh aspect, wherein the display unit and the auxiliary capacitance line drive circuit include first and second substrates, and the scan lines and signal lines are provided on the first substrate The counter electrode is provided on the second substrate. The liquid crystal display device of claim 8, wherein the auxiliary capacitor is composed of: a wiring provided on the first substrate; an insulating film provided on the wiring; and a wiring provided on the insulating film Transparent electrode. The liquid crystal display device of claim 6, wherein the auxiliary capacitance line driving circuit is disposed adjacent to the display portion, and the auxiliary capacitance line driving circuit is composed of a thin film transistor using an amorphous germanium or a polycrystalline germanium. . A driving method of a liquid crystal display device, wherein the liquid crystal display device is provided with a scan line composed of a plurality of columns (here, the column is an arbitrary natural number of 1≦i≦m) and a plurality of rows (here, the row is 1 a signal line composed of any natural number of ≦j≦n, a switching element is disposed at an intersection of the scanning line and the signal line, and is disposed between a pixel electrode and a counter electrode connected to an output end of the switching element A pixel matrix of m columns×n rows composed of liquid crystal cells is formed, and one end of the auxiliary capacitor is connected to an output end of the switching element, and the driving method is to perform the pixel element and the pair by the following operation The absolute value of the potential difference to the electrode is increased by applying a rectangular wave signal having the switching period in which the switching element is turned on and the holding period in which the switching element is turned on as a scanning line driving signal of the switching element, and applying a rectangular shape to the signal line a wave signal, a driving signal for the counter electrode for applying a rectangular wave signal to the counter electrode, and a first electric current applied to the first period of the driving signal for the counter electrode at the other end of the auxiliary capacitor The second voltage is applied to the p+1/2 cycle (here, p is 0 or a natural number) after the first cycle of the drive signal for the counter electrode, and the p+1/2 cycle is maintained. In the middle of the period, the first voltage is set to a voltage equal to the voltage applied to the counter electrode, and the second voltage is applied to the counter current. The voltage of the pole is different. The method of driving a liquid crystal display device according to claim 11, wherein the second voltage is a voltage which is the same as an inverted voltage of a voltage applied to the counter electrode in reverse. The driving method of a liquid crystal display device according to claim 12, wherein the driving method is applied in synchronization with a turn-on period of the scanning line (Gi+2) of the second column before the scanning line (Gi) to which the switching element is connected The aforementioned second voltage. The method of driving a liquid crystal display device according to claim 11 or claim 12, wherein the second voltage is a voltage for reducing a signal amplitude applied to the counter electrode. The method of driving a liquid crystal display device according to claim 11 or claim 12, wherein the second voltage is a DC voltage corresponding to a center of a signal amplitude applied to the counter electrode. A liquid crystal display device comprising: a display portion, which is composed of a scan line composed of a plurality of columns (here, the column is an arbitrary natural number of 1≦i≦m); a signal line consisting of a plurality of lines (here, the line is an arbitrary natural number of 1≦j≦n); a switching element disposed at an intersection of the scan line and the signal line; and a pixel electrode connected to an output end of the switching element a counter pixel; m column x n rows of pixel matrix, which is formed by arranging liquid crystal cells between the pixel electrode and the counter electrode; and an auxiliary capacitor having one end connected to the output end of the switching element; a capacitance line composed of a plurality of columns connected to the switching elements of the respective columns and having the other ends of the auxiliary capacitors of the respective columns common; and a parasitic capacitance shielding wiring which is disposed through the signal lines of the respective rows a scanning line driving circuit that outputs a driving signal for a scanning line having a switching period in which the switching element is turned on and a period in which the switching element is turned off, and a scanning line driving circuit that outputs a driving signal for the scanning line of each of the columns; Line drive circuit a signal line for outputting a signal line for each of the above-mentioned lines, a counter electrode driving circuit for outputting a driving signal for the counter electrode to the counter electrode, and an auxiliary capacitance line driving circuit for assisting the respective columns a capacitance line for outputting a drive signal for the auxiliary capacitance line; and the auxiliary capacitance line drive circuit is composed of first and second drive transistors connected to each of the storage capacitor lines, and the first drive transistor a main electrode is connected to the other end of the auxiliary capacitor, and a second main electrode of the first driving transistor is connected to a counter electrode wiring (COM1) that is a first common electrode, and a control electrode of the first driving transistor Connected to the scanning line (G _i ) of the i-th column, the first main electrode of the second driving transistor is connected to the first main electrode of the first driving transistor, and the second main electrode of the second driving transistor The main electrode is connected to the second common electrode wiring (COM2), the control electrode of the second driving transistor is connected to the scanning line (G _i+2 ) of the i+2 column, and the auxiliary capacitance line driving circuit is for the auxiliary capacitor Line, on The first voltage is applied to the first period of the driving signal for the counter electrode, and the first voltage is applied to the p+1/2 period (here, p is 0 or a natural number) after the first period of the driving signal for the counter electrode. In the holding period of the p+1/2 period, the voltage is outputted to the scanning signal for each scanning line in each of the above columns. The liquid crystal display device of claim 16, wherein the auxiliary capacitor is composed of first and second auxiliary capacitors, and one of the first and second auxiliary capacitors is connected to the pixel electrode, and the first auxiliary The other end of the capacitor is connected to the auxiliary capacitance line drive circuit, and the other end of the second auxiliary capacitor is connected to the counter electrode. The liquid crystal display device of claim 16, wherein a DC voltage is applied to the parasitic capacitance shielding wiring. The liquid crystal display device of claim 16, wherein a driving signal for the counter electrode is applied to the parasitic capacitance shielding wiring. The liquid crystal display device of claim 16, wherein the display unit and the auxiliary capacitance line drive circuit include first and second substrates, and the scan lines and signal lines are provided on the first substrate, and the pair The electrode is provided on the second substrate. The liquid crystal display device of claim 20, wherein the auxiliary capacitor is composed of: a device disposed on the first substrate a line; an insulating film disposed on the wiring; and a transparent electrode disposed on the insulating film. The liquid crystal display device of claim 16, wherein the auxiliary capacitance line driving circuit is disposed adjacent to the display portion, and the auxiliary capacitance line driving circuit is composed of a thin film transistor using an amorphous germanium or a polysilicon. . The liquid crystal display device of claim 16, wherein the parasitic capacitance shielding wiring is disposed between the switching element and the auxiliary capacitor, and is disposed in parallel with the auxiliary capacitance line. The liquid crystal display device of claim 20, wherein the first gate insulating film and the second gate insulating film are disposed on the first substrate, and the parasitic capacitance shielding wiring is disposed on the first gate On the insulating film. The liquid crystal display device of claim 20, wherein the linear portion of the parasitic capacitance shielding wiring is disposed on the first substrate, and an intersection of the parasitic capacitance shielding wiring is disposed in the first gate insulating In the film, the intersection portion and the linear portion are connected by a contact hole disposed in the first gate insulating film. The liquid crystal display device of claim 25, wherein the intersection of the parasitic capacitance shielding wiring is composed of a transparent electrode material.