JP2010146025A - Liquid crystal display and driving method for the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display and a driving method for the same, obtaining pixel voltage exceeding the output voltage of a driver LSI. <P>SOLUTION: This liquid crystal display includes: a display part 10; a scanning line driving circuit 20; a signal line driving circuit 22; a counter electrode driving circuit 24 for outputting a counter electrode driving signal in opposite phase to a signal line driving signal to a counter electrode; an auxiliary capacitor 16, one end of which is connected to an output end of a switching element 12; and an auxiliary capacitor line driving circuit 26 connected to the switching element 12 of each row to drive auxiliary capacitor lines of two or more rows to which the other end of the auxiliary capacitor 16 of each row is common. The auxiliary capacitor line driving circuit 26 applies a first voltage to the auxiliary capacitor line of each row during a first period of a counter electrode driving signal, applies a second voltage during p+1/2 period after the first period of the counter electrode driving signal (wherein p is 0 or natural numbers), and outputs a signal for making the open state during the holding period after the p+1/2 period according to each scanning line driving signal of each row. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly to a liquid crystal display device and a driving method thereof that can drive a storage capacitor electrode of a pixel independently of a counter electrode to improve a pixel voltage.

In a conventional liquid crystal display device, a voltage is applied to the liquid crystal by a switching element such as a thin film transistor (TFT) provided in each pixel made of liquid crystal. FIG. 21 is a diagram schematically showing one pixel 100 of a conventional liquid crystal display device, and FIG. 22 is a diagram schematically showing a pixel structure for one row.
The pixel electrode (Pix) 101 is charged to the source potential via the transistor 102. A voltage (Vcom) for driving the counter electrode is applied to the counter electrode (COM) 103, and a potential difference between the counter electrode 103 and the pixel electrode 101 becomes a liquid crystal driving voltage (Vlcd). A storage capacitor electrode (Cs) 105 is provided on the substrate 104 side. The auxiliary capacitance electrode 105 alleviates the potential fluctuation generated in the pixel electrode 101 due to the gate potential fluctuation of the transistor 102 or the leakage current when the transistor 102 is off. The wiring of the auxiliary capacitance electrode 105 is usually laid in parallel with the gate wiring. This wiring is connected to the counter electrode 103. As a result, the potential of the auxiliary capacitance electrode 105 is the same as that of the counter electrode 103. The liquid crystal is AC driven to prevent burn-in and electrolysis.

  FIG. 23 is a time chart showing an example of a driving waveform in the liquid crystal display device, where (A) shows a voltage waveform applied to the counter electrode, (B) shows a signal line voltage waveform, and (C) shows a scanning line. The voltage waveform is shown by (D) in FIG. As shown in the figure, the voltage waveform (Vcom) applied to the counter electrode and the voltage waveform (Vs) applied to the source electrode of the transistor are rectangular waves, and the scanning line voltage is the voltage ( Vg). As shown in FIG. 23C, the transistor is turned on when a high level voltage is applied to the gate, and the transistor is turned off (off) when the voltage applied to the gate becomes low level. During the holding period in which the transistor is turned off, the liquid crystal drive voltage (Vlcd) rises and falls as a whole according to the waveform of the voltage (Vcom) applied to the counter electrode, so the liquid crystal drive voltage is equal to the voltage applied to the gate. It is AC driven by having positive and negative voltages for each cycle.

  In order to drive the liquid crystal display device, a voltage of about ± 4 to 5 V is required for AC driving. As shown in FIG. 23, an AC driving voltage is generated by a combination of rectangular waves of the signal line voltage (Vs) and the counter electrode voltage (Vcom). These signal waveforms are supplied from the driver LSI. In recent years, the voltage of LSI has been lowered, and the voltage between Vcom and Vs is about 4.8 V at the maximum. Although this voltage restriction is not absolute, in order to output a voltage higher than this from the driver LSI, it is necessary to change the withstand voltage design of the LSI, and the area and cost of the LSI are greatly increased. As described above, a voltage of about ± 4 to 5 V is required for driving the liquid crystal display device, so it can be said that it is a marginal balance. However, some new-mode liquid crystal display devices (vertical alignment mode, lateral electric field mode n-type liquid crystal, etc.) that have been developed in recent years require a voltage exceeding 5 V in order to fully exhibit their performance. In some cases, the LSIs seem to be lacking in capacity.

  By the way, in the liquid crystal display device disclosed in Patent Document 1, a storage capacitor line drive circuit is provided separately without connecting the storage capacitor electrode and the counter electrode. In this case, the auxiliary capacitance is formed by an auxiliary capacitance electrode, a pixel electrode, and an insulating layer inserted between these electrodes. Patent Document 1 discloses a liquid crystal display device that applies a voltage different from that of a counter electrode from an auxiliary capacitance line driving circuit to an auxiliary capacitance electrode. 24, 25, and 26 are diagrams showing a block diagram of a liquid crystal display device disclosed in Patent Document 1, waveforms of gate signals and auxiliary capacitance line drive signals, and waveforms applied to pixels, respectively.

A display region 111 indicated by a dotted line in FIG. 24 is a display unit that displays a predetermined image with a plurality of pixels. Display unit is scanned by the scanning lines _{G 1, G 2, G 3} ··· G n, is given a display signal by the signal lines _{S 1, S 2, S 3} ··· S m.

Scan lines _{G 1, G 2, G 3} ··· G n and the signal lines _{S 1, S 2, S 3} ··· TFT at the intersection of the S _m (TFT) 114 is arranged. A liquid crystal cell 115 is disposed on the pixel electrode portion connected to the drain of each thin film transistor 114. The gate of the transistor is connected to the scanning line G, and the source is connected to the signal line S.

Scanning line drive circuit 116 selects the pixel columns of one row every horizontal period are sequentially scanning each scanning line _{G 1, G 2, G 3} ··· G n. The signal line driving circuit 117 outputs a display signal through each of the signal lines S ₁ , S ₂ , S ₃ ... S _m , and outputs it to one row of liquid crystal cells selected by the scanning line driving circuit 116 within one horizontal period. In contrast, a pixel voltage is applied through the transistor 114. Further, the counter electrode 118 and its wiring line are provided on the second transparent substrate with each liquid crystal cell 115 interposed therebetween. These two substrates sandwich the liquid crystal cell 115.

The common electrode drive circuit 119 applies a common common electrode voltage Vcom to all liquid crystal cells via the common electrode 118. One end of the auxiliary capacitor 112 provided in each pixel is connected to the drain of each transistor 114, and the other end is connected to a different auxiliary capacitor line 113 for each scanning line. The storage capacitor line 113 corresponding to the scanning line G ₁ is connected to the first output terminal of the storage capacitor line driving circuit 110, and the storage capacitor line 113 corresponding to the scanning line G ₂ is connected to the second output terminal of the storage capacitor line driving circuit 110. Connected to. The auxiliary capacitance lines 113 corresponding to the scanning lines G _{3 to} G _n are similarly connected. The storage capacitor driving voltages Vst1 to Vstn are output from the first output terminal to the nth output terminal of the storage capacitor line driving circuit 110 at different timings corresponding to the scanning lines G _{1 to} G _n , respectively.

FIG. 25 is a timing chart showing the operation of the liquid crystal display device of Patent Document 1. 25A shows gate signals G _{sig, 1} , G _{sig, 2} ... Output from the scanning lines G ₁ , G ₂ ..., And FIG. Shows changes in the storage capacitor line drive voltages Vst1, Vst2,. The gate signals G _{sig, 1} , G _{sig, 2} ... _Are pulses that are output from the scanning line driving circuit 116 of FIG. 24 and select a scanning line, and have a repetition period of one frame. The voltage of the gate signal G _sig becomes the voltage Vgh when each pixel for one row is selected, and is held at the voltage Vgl when not selected. The auxiliary capacitance line drive voltages Vst1, Vst2,... Are binary voltage signals having an amplitude of ΔVst. As shown in the figure, the voltage is applied to one end of each liquid crystal cell 115 via the auxiliary capacitor 112. The auxiliary capacitance line drive voltage Vst1 to the scanning lines G _1, after the gate signal G _{sig, 1} falls, the amplitude a slight delay changes by DerutaVst. Similarly, the auxiliary capacitance line drive voltages Vst2...

FIG. 26 is a waveform diagram of a voltage applied to each pixel of the liquid crystal display device of Patent Document 1. The gate signal G _sig shown in the figure is output to the scanning line Gi (i = 1 to n) selected from the scanning line driving circuit 116. When selecting each pixel for one row, the voltage becomes Vgh, and when not selected, the voltage becomes Vgl. The DC counter electrode voltage Vcom is output from the counter electrode drive circuit 119. Vcom is constant. The output level of the output voltage Vd output from the drain of the transistor 114 changes to the positive and negative sides around the counter electrode voltage Vcom in one frame period. When the gate is selected, the pixel electrode of the liquid crystal cell 115 on the scanning line is charged with the signal voltage Vsig supplied through the signal line S, but the drain-gate capacitance which is a parasitic capacitance of the transistor 114. Due to the influence of Cdg, when the gate signal G _sig changes from Vgh to Vgl, the output voltage Vd changes to a voltage that is lower than Vsig by Vpt. Thereafter, as shown in the drawing, when the auxiliary capacitance driving voltage Vst of the auxiliary capacitance line driving circuit 110 falls by ΔVst voltage, the output voltage Vd further decreases by K · ΔVst. Here, K is a constant that depends on the value of the capacitance included in the capacitive coupling. Thus, the voltage Vdl, which is the difference between the counter electrode voltage Vcom and the pixel electrode voltage Vd, is applied as the driving voltage of the liquid crystal cell 115.

More specifically, the constant K is given by the following equation (1).
K = Cst / (Clc + Cst + Cdg) (1)
Here, Cst is the capacitance of the auxiliary capacitor 112, Clc is the capacitance of the liquid crystal cell 115, and Cdg is the parasitic capacitance between the drain and gate of the transistor 114.

When writing a display signal to the liquid crystal cells 115 of the same scan line in the next frame, when again the selection of the scanning line G _i, a signal line S _j to the liquid crystal cell 115 of the pixel (i, j) Charging is performed by the signal voltage Vsig supplied through the terminal. Vsig has a substantially symmetrical waveform around the level of Vcom. As shown in FIG. 26, the drain in the transistor 114 - under the influence of the parasitic capacitance Cdg between the gate, when the gate signal G _sig, voltage of _i is changed to Vgl from Vgh, the output voltage Vd is reduced by Vpt. Thereafter, when the auxiliary capacitance driving voltage Vst of the auxiliary capacitance line driving circuit 110 rises by ΔVst, the output voltage Vd rises from the current voltage by K · ΔVst. Here, K is the above constant. Thereafter, the increased voltage is held, and the difference between the output voltage Vd and the counter electrode voltage Vcom is applied to the liquid crystal cell 115 as the drive voltage Vdl. In this way, the liquid crystal panel is AC driven with a period of one frame.

  As shown in FIG. 25, when the output voltage Vd becomes lower than the counter electrode voltage Vcom, the output voltage Vd is further set to the counter electrode voltage Vcom by K · ΔVst from (Vsig + Vpt) by the signal from the auxiliary capacitance line driving circuit 110. It shifts to a lower direction. Further, when the output voltage Vd is higher than the counter electrode pressure Vcom, the output voltage Vd is higher than the counter electrode voltage Vcom by K · ΔVst than (Vsig−Vpt) by a signal from the auxiliary capacitance line driving circuit 110. Shift in direction.

  Therefore, according to Patent Document 1, in order to display the liquid crystal cell 115 in black, when the drive voltage Vdl is set to a value Vdl1 higher than Vdl0, the value of the signal voltage Vsig with respect to the predetermined drive voltage Vdl1 can be reduced. As described above, since the output voltage Vd applied to the liquid crystal cell 115 shifts away from the common electrode voltage Vcom by K · ΔVst, the amplitude Vspp ′ of the signal line is made smaller than the amplitude Vspp of the signal line in the conventional liquid crystal cell. be able to.

In the driving method of the auxiliary capacity electrode described in Patent Document 1, a DC voltage is applied to the counter electrode, and the liquid crystal driving voltage is driven by synchronizing the potential of the auxiliary capacity electrode with the frame period independently of the counter electrode. (Vlcd) is improved. However, the output signal Vst1 from the auxiliary capacitance line drive circuit 110 is a binary voltage signal having an amplitude of ΔVst, and after the gate signal G _{sig, 1} falls, the amplitude is changed by ΔVst with a slight delay. ing. Therefore, the auxiliary capacitance line drive voltage Vst1 to the scanning lines G _1, it is necessary to make the waveform scan lines G ₁ is shifted from the cycle turned on. For this reason, the signal of the storage capacitor line driving circuit is different from any waveform applied to the signal line, the scanning line, and the counter electrode, and thus the circuit configuration is complicated.

JP 2001-255851 A

  In the conventional liquid crystal display device shown in FIG. 23, the liquid crystal driving voltage (Vlcd) is applied as a combination of a rectangular wave of the signal line voltage (Vs) and the counter electrode voltage (Vcom). For this reason, when it is necessary to increase the liquid crystal driving voltage, a driving LSI having a large output voltage is required. In order to increase the signal line voltage without using a driving LSI having a large output voltage, it is conceivable to improve the liquid crystal driving voltage by driving the auxiliary capacitance electrode as in Patent Document 1. In this case, since the counter electrode is driven with a DC voltage, it cannot be applied immediately when the counter electrode voltage is driven with a rectangular wave. For this reason, the conventional liquid crystal display device shown in FIG. 23 obtains a specific circuit configuration and driving method for driving the counter electrode voltage with a rectangular wave and driving the auxiliary capacitor to improve the liquid crystal driving voltage. There is a problem that it is not done.

  In view of the above problems, the present invention provides a booster electrode inside a pixel and performs driving that makes the operation similar to that of a charge pump with an easier configuration, and obtains a pixel voltage that exceeds the output voltage of a driver LSI for liquid crystal display. Another object is to provide a liquid crystal display device that can be used. Another object of the present invention is to provide a method for driving the liquid crystal display device.

In order to achieve the above object, a first configuration of the liquid crystal display device of the present invention includes a plurality of rows (where a row is an arbitrary natural number of 1 ≦ i ≦ m) and a plurality of columns ( Here, the column is a signal line consisting of 1 ≦ j ≦ n), a switching element provided at the intersection of the scanning line and the signal line, a pixel electrode connected to the output terminal of the switching element, , A counter matrix, an m-row × n-column pixel matrix in which a liquid crystal cell is disposed between the pixel electrode and the counter electrode, an auxiliary capacitor having one end connected to the output end of the switching element, and switching of each row A display unit comprising a plurality of rows of auxiliary capacitance lines connected to the elements and having the other ends of the auxiliary capacitances of each row in common, and an on period and an off time during which the switching elements are turned on for the scanning lines of each row A scanning line drive signal having a holding period of A scanning line driving circuit that outputs power, a signal line driving circuit that outputs a driving signal for a signal line to the signal line of each column, a counter electrode driving circuit that outputs a driving signal for the counter electrode to the counter electrode, and an auxiliary for each row A storage capacitor line driving circuit that outputs a storage capacitor line driving signal to the capacitor line, the storage capacitor line driving circuit having a first voltage in the first period of the counter electrode driving signal with respect to the storage capacitor line. And the second voltage is applied to p + 1/2 period (where p is 0 or a natural number) after the first period of the counter electrode drive signal, and the holding period after this p + 1/2 period Then, a signal for setting the open state is output for each scanning line driving signal in each row.
According to the liquid crystal display device of the present invention, the storage capacitor can be driven by a storage capacitor line driving circuit having a simple configuration, and the boosted state of the pixel voltage (Vpix) can be maintained during the holding period, and the contrast of the pixel can be increased. Can be bigger. Therefore, the pixel potential can be boosted while using a voltage within the voltage limit of the driver LSI used in the liquid crystal display device.

In the above configuration, preferably, the storage capacitor line drive circuit includes first and second drive transistors connected to each storage capacitor line, and the first main electrode of the first drive transistor is the other of the storage capacitor. The second main electrode of the first driving transistor is connected to the counter electrode wiring (COM1) serving as the first common electrode, and the control electrode of the first driving transistor is connected to the i-th row of the scanning line. (G _i ), the first main electrode of the second driving transistor is connected to the first main electrode of the first driving transistor, and the second main electrode of the second driving transistor is the second Are connected to the common electrode wiring (COM2), and the control electrode of the second driving transistor is connected to the scanning line (G _{i + 2} ) in the ( _{i + 2} ) _th row.

The second configuration of the liquid crystal display device of the present invention includes a scanning line composed of a plurality of rows (where a row is an arbitrary natural number satisfying 1 ≦ i ≦ m) and a plurality of columns (where a column is 1 ≦ j). ≦ n arbitrary natural number), a switching element provided at the intersection of the scanning line and the signal line, a pixel electrode connected to the output terminal of the switching element, a counter electrode, a pixel electrode, A pixel matrix of m rows × n columns in which a liquid crystal cell is disposed between the counter electrode, an auxiliary capacitor having one end connected to the output end of the switching element, a switching element connected to each row, and each row A plurality of rows of auxiliary capacitance lines sharing the other end of the auxiliary capacitance, a display portion, and a scanning line having an on period in which the switching element is on and a holding period in which the switching element is off with respect to the scanning line of each row A scanning line driving circuit for outputting a driving signal for use; A signal line drive circuit that outputs a signal line drive signal to the column signal line, a counter electrode drive circuit that outputs a counter electrode drive signal to the counter electrode, and an auxiliary capacitance line drive for the auxiliary capacitance line of each row An auxiliary capacitance line driving circuit that outputs a signal, and the auxiliary capacitance line driving circuit is composed of first and second driving transistors connected to each auxiliary capacitance line, and the first of the first driving transistors. The main electrode is connected to the other end of the auxiliary capacitor, the second main electrode of the first driving transistor is connected to the counter electrode wiring (COM1) serving as the first common electrode, and the control electrode of the first driving transistor Is connected to the _i-th scanning line (G _i ), the first main electrode of the second driving transistor is connected to the first main electrode of the first driving transistor, and the second driving transistor first Two main electrodes are connected to the second common electrode wiring (CO M2), the control electrode of the second driving transistor is connected to the scanning line (G _{i + 2} ) of the ( _{i + 2} ) _th row, and the auxiliary capacitance line driving circuit transmits the counter electrode driving signal to the auxiliary capacitance line. A first voltage is applied in the first period, and a second voltage is applied in the p + 1/2 period (where p is 0 or a natural number) after the first period of the counter electrode drive signal. In the holding period after the p + 1/2 cycle, a signal for opening is output for each scanning line driving signal in each row.

  According to the above configuration, the storage capacitor driving circuit can be realized by using the two transistors provided for each storage capacitor line, the voltage applied to the counter electrode wiring, and the scanning line voltage. By driving the auxiliary capacitor by this auxiliary capacitor driving circuit, the pixel can be boosted.

A third configuration of the liquid crystal display device according to the present invention includes a scanning line composed of a plurality of rows (where a row is an arbitrary natural number satisfying 1 ≦ i ≦ m) and a plurality of columns (where a column is 1 ≦ j). ≦ n arbitrary natural number), a switching element provided at the intersection of the scanning line and the signal line, a pixel electrode connected to the output terminal of the switching element, a counter electrode, a pixel electrode, A pixel matrix of m rows × n columns in which a liquid crystal cell is disposed between the counter electrode, an auxiliary capacitor having one end connected to the output end of the switching element, a switching element connected to each row, and each row An auxiliary capacitance line composed of a plurality of rows having the other end of the auxiliary capacitance in common, and a parasitic capacitance shielding wiring arranged so as to pass through the intersection of the signal line of each column and the auxiliary capacitance line of each row, And a switching element is turned on for each scanning line. A scanning line driving circuit that outputs a scanning line driving signal having an ON period and a holding period that is OFF, a signal line driving circuit that outputs a signal line driving signal to the signal line of each column, and a counter electrode A counter electrode drive circuit that outputs a drive signal for the counter electrode; and an auxiliary capacitance line drive circuit that outputs a drive signal for the auxiliary capacitance line to the auxiliary capacitance line of each row. The first and second driving transistors are connected to each other, the first main electrode of the first driving transistor is connected to the other end of the auxiliary capacitor, and the second main electrode of the first driving transistor is The counter electrode wiring (COM1) serving as the first common electrode is connected, the control electrode of the first driving transistor is connected to the _i-th scanning line (G _i ), and the first driving transistor first The main electrode is the first driving transistor Is connected to the first main electrode, the second main electrode of the second driving transistor is connected to the second common electrode wiring (COM2), and the control electrode of the second driving transistor is the scanning line of the (i + 2) th row. (G i _{+ 2)} is connected to the storage capacitor line drive circuit in the first cycle of the drive signal for a counter electrode with respect to the auxiliary capacitance line by applying a first voltage, the first period of the counter electrode driving signal The second voltage is applied in the subsequent p + 1/2 period (where p is 0 or a natural number), and a signal that is opened in the holding period after the p + 1/2 period is driven for the scanning line of each row. Output according to each signal.

  In the above configuration, preferably, the auxiliary capacitor includes first and second auxiliary capacitors, one end of the first and second auxiliary capacitors is connected to the pixel electrode, and the other end of the first auxiliary capacitor is the auxiliary capacitor line. In addition to being connected to the drive circuit, the other end of the second auxiliary capacitor is connected to the counter electrode. By driving an auxiliary capacitor provided separately from the pixel auxiliary capacitor, the pixel can be boosted.

  In the above structure, preferably, the display portion includes first and second substrates, the scanning lines and the signal lines are provided on the first substrate, and the counter electrode is provided on the second substrate. The auxiliary capacitor is preferably composed of a wiring provided on the first substrate, an insulating film provided on the wiring, and a transparent electrode provided on the insulating film. The auxiliary capacitance line driving circuit is provided adjacent to the display portion, and the auxiliary capacitance line driving circuit is formed of a thin film transistor using amorphous silicon or polysilicon. Thereby, an auxiliary capacity driving circuit made of a thin film transistor can be easily formed on the substrate.

  In the above configuration, a DC voltage is preferably applied to the parasitic capacitance shielding wiring. A counter electrode drive signal may be applied to the parasitic capacitance shielding wiring. The parasitic capacitance shielding wiring is preferably arranged between the switching element and the auxiliary capacitance, and is arranged in parallel with the auxiliary capacitance line. The first gate insulating film and the second gate insulating film may be disposed on the first substrate, and the parasitic capacitance shielding wiring may be disposed on the first gate insulating film. The straight portion of the parasitic capacitance shielding wiring is disposed on the first substrate, the intersection portion of the parasitic capacitance shielding wiring is disposed on the first gate insulating film, and the intersection portion and the straight portion are insulated from the first gate insulation. They may be connected via contact holes arranged in the film. The intersection of the parasitic capacitance shielding wiring is preferably made of a transparent electrode material.

  In order to achieve the other object, a driving method of a liquid crystal display device according to the present invention includes a scanning line and a plurality of columns (here, a row is an arbitrary natural number of 1 ≦ i ≦ m). , The column is provided with a signal line of 1 ≦ j ≦ n), a switching element is provided at the intersection of the scanning line and the signal line, and a pixel electrode and a counter electrode connected to the output end of the switching element A liquid crystal display device driving method in which an m-row × n-column pixel matrix made up of liquid crystal cells is disposed between and one end of an auxiliary capacitor connected to the output end of the switching element. A rectangular wave signal having an on period in which the switching element is turned on and a holding period in which the switching element is turned off is applied as a line driving signal, a rectangular wave signal is applied to the signal line and the counter electrode, and the other end of the auxiliary capacitor is applied. , The first rotation of the drive signal for the counter electrode The first voltage is applied to the counter electrode, and the second voltage is applied to the p + 1/2 period (where p is 0 or a natural number) after the first period of the counter electrode drive signal, and the p + 1/2 period By setting the floating state during the subsequent holding period, the absolute value of the potential difference between the pixel electrode and the counter electrode is increased.

In the above configuration, the first voltage is preferably the same voltage as the counter electrode, and the second voltage is different from the counter electrode. Alternatively, the first voltage may be the same voltage as the counter electrode, and the second voltage may be the same voltage as the inverted voltage of the counter electrode.
The second voltage is preferably synchronized with the ON period of the second destination of the _i-th scanning line (G _i ) to which the switching element is connected, that is, the i + 2th scanning line (G _{i + 2} ). Apply.
The voltage applied to the auxiliary capacitor is preferably a voltage in which the amplitude of the signal applied to the counter electrode wiring is reduced. Alternatively, the voltage applied to the auxiliary capacitor may be a DC voltage corresponding to the amplitude center of the signal applied to the counter electrode wiring.

  According to the above configuration, since the auxiliary capacitor provided in the pixel is driven with a waveform having a predetermined timing with respect to the signal applied to the scanning line, the signal line, and the counter electrode, the boosted state of the pixel voltage (Vpix) is set. This can be maintained during the holding period, and the contrast of the pixel can be increased. Therefore, the pixel potential can be boosted while using a voltage within the voltage limit of the driver LSI used in the liquid crystal display device.

  According to the liquid crystal display device and the driving method thereof of the present invention, the auxiliary capacitance of the pixel can be driven independently of the counter electrode by the auxiliary capacitance driving circuit, and the potential of the pixel can be boosted with a simple configuration. The contrast of the pixel can be improved without increasing the output voltage of the driver LSI. Since the storage capacitor driving circuit can use the scanning signal in the liquid crystal display device or the signal of the counter electrode wiring, the contrast of the pixel can be improved at low cost.

It is a block diagram which shows the structure of the liquid crystal display device of this invention. It is a figure which shows the permeation | transmission top view of a part of 1st board | substrate in the color liquid crystal display device as 1st Embodiment of this invention. (A) is sectional drawing which follows the XX line of FIG. 2, (B) has shown sectional drawing containing the 2nd board | substrate in the part which follows the YY line of FIG. It is a block diagram which shows the equivalent circuit of the pixel structure of 1 row 3 columns. FIG. 6 is a waveform showing an example of a driving method of the liquid crystal display device 1 according to the present invention, where (A) is a driving signal for a counter electrode, (B) is a driving signal for an auxiliary capacitance line, and (C) is a signal line. The drive signal, (D) shows the scanning line drive signal, and (E) shows the voltage applied to the pixel together with the voltage of the pixel electrode (voltage difference between the pixel electrode and the counter electrode). A block diagram in the case where a pixel auxiliary capacitor and an auxiliary capacitor are provided separately is shown. (A) is a plan view of the pixel structure, and (B) is a cross-sectional view. It is a block diagram which shows 2nd Embodiment of the liquid crystal display device of this invention. It is a figure which shows typically the equivalent circuit of 1 pixel. FIG. 5 is a waveform showing a driving method of the liquid crystal display device of the present invention, where (A) is a counter electrode driving signal, (B) is a second common electrode driving signal (Vcom2), and (C) is a signal. (D) is the driving signal for the scanning line G ₁ , (E) is the driving signal for the scanning line G ₂ , (F) is the driving signal for the scanning line G ₃ , and (G) is the auxiliary signal. As for the auxiliary capacitance line drive signal applied to the capacitance line, (H) shows the voltage at the pixel electrode of the pixel and the voltage difference of the liquid crystal cell generated between the pixel electrode and the counter electrode. A block diagram in the case where a pixel auxiliary capacitor and an auxiliary capacitor are provided separately is shown. FIG. 12 is a diagram illustrating a specific pixel structure of FIG. 11, where (A) is a plan view of the pixel structure and (B) is a cross-sectional view. FIG. 3 is a schematic cross-sectional view showing an intersection between a signal line and an auxiliary capacitance line of the pixel shown in FIG. 2. FIG. 3 is a diagram illustrating an equivalent circuit including a parasitic capacitance Cst in a liquid crystal display device. It is a partial perspective top view which shows the structure of the modification of a pixel. FIG. 16 is a cross-sectional view taken along line XX in FIG. 15. It is a cross-sectional schematic diagram which shows the capacity | capacitance which arises in the intersection of a parasitic capacitance shielding wiring and a signal line by addition of the parasitic capacitance shielding wiring in a pixel. It is a partial perspective top view which shows the structure of a pixel. FIG. 19 is a cross-sectional view taken along line XX in FIG. 18. It is a cross-sectional schematic diagram which shows the capacity | capacitance which arises in the intersection part of the parasitic capacitance shielding wiring and signal line in a pixel. It is a figure which shows typically the structure for 1 pixel of the conventional liquid crystal display device. It is a figure which shows typically the pixel structure for one line. It is a figure which shows the waveform applied to a pixel. 1 is a block diagram of a liquid crystal display device disclosed in Patent Document 1. FIG. 4 is a timing chart showing the operation of the liquid crystal display device of Patent Document 1, wherein (A) shows a gate signal output from each scanning line, and (B) shows an auxiliary capacitance line drive voltage output from an auxiliary capacitance line drive circuit. Shows changes. 6 is a waveform diagram of a voltage applied to each image of the liquid crystal display device of Patent Document 1. FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In each figure, the same or corresponding members are denoted by the same reference numerals.
FIG. 1 is a block diagram showing a configuration of a liquid crystal display device 1 of the present invention, and FIGS. 2 to 4 show an example of a display unit 10 in the liquid crystal display device 1 of the present invention.
As shown in FIG. 1, the liquid crystal display device 1 of the present invention includes a display unit 10 surrounded by a dotted line, a scanning line driving circuit 20, a signal line driving circuit 22, a counter electrode driving circuit 24, and the periphery of the display unit 10. A storage capacitor line driving circuit 26 is arranged.

In the liquid crystal display device 1, scanning lines composed of a plurality of rows and signal lines composed of a plurality of columns are disposed on a first transparent substrate (not shown), and a switching element 12 is disposed at the intersection of the scanning lines and the signal lines. A pixel 15 made of a liquid crystal cell is disposed between the pixel electrode 13 connected to the output end of the switching element 12 and the counter electrode 14, and one end of the auxiliary capacitor 16 is connected to the output end of the switching element 12. Has been. Here, the row is composed of an arbitrary natural number of 1 ≦ i ≦ m, and the column is composed of an arbitrary natural number of 1 ≦ j ≦ n. In addition, the switching element 12 of i row j column is described with the switching element _12ij .

In the case of illustration, the display unit 10 includes a plurality of pixels 15 arranged in a matrix of m rows × n columns. In this case, the gate electrodes (also referred to as control electrodes) of the switching elements 12 arranged in the pixels 15 in each row are connected to each other to form a gate electrode wiring. Accordingly, the gate electrode wirings in the ₁ , ₂ , _{3 to m} rows are connected to the scanning lines G ₁ , G ₂ , G _{3 to} G _m of the scanning line driving circuit 20 and scanned.

In the switching elements 12 arranged in the pixels 15 of each column, the source electrodes (also referred to as first main electrodes) are connected to each other to form a source electrode wiring. Accordingly, the source electrode wirings in the ₁ , ₂ , _{3 to n} columns are connected to the signal lines S ₁ , S ₂ , S _{3 to} Sn of the signal line driving circuit 22, respectively, and a display signal is applied.

  A liquid crystal cell 15 is disposed between the counter electrode 14 and the pixel electrode 13 connected to the drain electrode (also referred to as a second main electrode) of each switching element 12. The switching element 12 is, for example, a transistor. As the transistor 12, a thin film transistor manufactured using amorphous silicon or low-temperature polysilicon on a first transparent substrate (not shown) can be used. As described above, the gate of the transistor 12 is connected to the scanning line, and the source is connected to the signal line S. A wiring between the counter electrode 14 and the counter electrode 14 is provided on a second transparent substrate (not shown) with each liquid crystal cell 15 inserted.

The scanning line driving circuit 20 outputs a scanning line driving signal having an on period in which the switching element 12 is turned on and a holding period in which the switching element 12 is turned off with respect to each scanning line. The scanning line driving circuit 20 selects one row of pixel columns every horizontal period by sequentially scanning the scanning lines G ₁ , G ₂ , G _{3 to} G _m .

The signal line drive circuit 22 outputs a signal line drive signal at a predetermined timing that is substantially synchronized with the ON period of the switching element 12 for the signal lines in each column. That, and outputs a display signal through the signal lines _{S 1, S 2, S 3} ~S n. The signal line driving circuit 22 outputs a pixel voltage via the transistor 12 to the liquid crystal cells for one row selected by the scanning line driving circuit 20 within one horizontal period.

  The common electrode drive circuit 24 outputs a common electrode drive signal and applies a common common electrode voltage (Vcom) to all the liquid crystal cells 15 via the common electrode 14 formed on the second transparent substrate (not shown).

One end of the auxiliary capacitor 16 is connected to the pixel electrode 13 to which the drain of the transistor 12 is connected, and the other end of the auxiliary capacitor 16 is connected to the auxiliary capacitor line driving circuit 26. As shown in FIG. 1, that is, the other ends of the auxiliary capacitors 16 arranged in the pixels 15 of each row are wired in common to form an auxiliary capacitor line connected to the auxiliary capacitor line driving circuit 26. Accordingly, the auxiliary capacitance lines of 1, 2, 3 to m rows are connected to the first to m-th output terminals of the auxiliary capacitance line driving circuit 26, respectively. Vcs1 to Vcsm are output from the first output terminal to the m-th output terminal, respectively.
In the above case, the liquid crystal display device 1 may be a pixel corresponding to a color display described as a monochrome display.

  2 is a transmission plan view showing a part of the first substrate 41 in the color liquid crystal display device 1 as the first embodiment of the present invention, and FIG. 3 (A) is taken along line XX of FIG. FIG. 3B is a cross-sectional view including the second substrate 42 taken along the line YY in FIG.

  As shown in FIG. 2, a plurality of scanning lines 44 and a plurality of signal lines 45 are provided on the first substrate 41 so as to extend in the row direction and the column direction, respectively. Near each intersection of both lines 44 and 45, a thin film transistor 46 connected to both lines 44 and 45 and a pixel electrode 47 driven by the thin film transistor 46 are disposed. Further, an auxiliary capacitance line 48 is provided on the opposite side of the scanning line 44 across the pixel electrode 47 so as to overlap the pixel electrode 47 along the row direction.

  As shown in FIG. 3B, in this color liquid crystal display device 1, a first substrate 41 and a second substrate 42 which is a counter substrate positioned above the first substrate 41 are formed in a substantially rectangular frame shape. The liquid crystal 43 is sealed in a space defined between the sealing material and the two substrates 41 and 42.

  Next, a specific structure of the thin film transistor 46 and the like will be described with reference to FIG. A scanning line 44 including the gate electrode 51 is provided on one predetermined portion of the upper surface of the first substrate 41, that is, the surface facing the second substrate 42, and an auxiliary capacitance line 48 is provided on the other predetermined portion. A gate insulating film 52 is provided on the entire upper surface.

  A semiconductor thin film 53 made of intrinsic amorphous silicon is provided at a predetermined position on the upper surface of the gate insulating film 52. On the upper surface of the semiconductor thin film 53, a channel protective film 54 is provided on the inner side by a predetermined amount than the intersection between the semiconductor thin film 53 and the gate electrode 51. Contact layers 55 and 56 made of n-type amorphous silicon are provided on both sides of the upper surface of the channel protective film 54 and on the upper surface of the semiconductor thin film 53 on both sides thereof.

  A drain electrode 57 is provided on the upper surface of one contact layer 55. A signal line 45 including a source electrode 58 is provided at a predetermined position on the upper surface of the other contact layer 56 and the upper surface of the gate insulating film 52.

  The gate electrode 51, the gate insulating film 52, the semiconductor thin film 53, the channel protective film 54, the contact layers 55 and 56, the drain electrode 57 and the source electrode 58 constitute a thin film transistor 46.

  An overcoat film 59 made of an insulating material is provided on the entire upper surface of the gate insulating film 52 including the thin film transistor 46 and the like. The overcoat film 59 may be a planarizing film. A contact hole 60 is provided in a portion corresponding to a predetermined portion of the drain electrode 57 of the overcoat film 59. A pixel electrode 47 is provided at a predetermined position on the upper surface of the overcoat film 59. The pixel electrode 47 is formed of a transparent electrode made of ITO. The pixel electrode 47 is connected to the drain electrode 57 through the contact hole 60.

  Next, the second substrate 42 will be described with reference to FIG. A black matrix 61 and R, G, and B color filter elements 62R, 62G, and 62B are provided at predetermined locations on the lower surface of the second substrate 42 (the surface facing the first substrate 41). Among these, the color filter elements 62R, 62G, and 62B are provided to face the corresponding pixel electrodes 47.

  On the lower surfaces of the black matrix 61 and the color filter elements 62R, 62G, and 62B, a counter electrode 63 is formed of a transparent electrode made of ITO. A pixel capacitor portion is formed by the liquid crystal 43 sealed between the pixel electrode 47 and the counter electrode 63 disposed opposite thereto. In this case, since the area of the pixel electrode 47 is the same, the pixel capacitance of the pixel capacitance portion is the same.

  Here, as shown in FIG. 2, the portion of the auxiliary capacitance line 48 that overlaps the pixel electrode 47 is an auxiliary capacitance electrode 48a provided in each pixel. The auxiliary capacitor 16 shown in FIG. 1 is formed by the overlapped portion. That is, in the color liquid crystal display device 1 shown in FIGS. 2 and 3, the auxiliary capacitor 16 is connected to the auxiliary capacitor electrode 48a which is a part of the wiring provided on the first substrate 41 and the insulation provided on the wiring. The films 52 and 59 and the pixel electrode 47 made of a transparent electrode provided on the insulating films 52 and 59 are formed.

  On the other hand, since each pixel electrode 47 corresponding to each color filter element 62R, 62G, 62B is provided on the overcoat film 59, it is arranged on the same plane. Therefore, the dimension of the gap in each of the R, G, and B pixels is d (see FIG. 3B).

In addition to the thin film transistor which is the switching element 12 connected to the pixel 15 in FIG. 1, at least one circuit or all the circuits of the scanning line driving circuit 20, the signal line driving circuit 22, and the auxiliary capacitance line driving circuit 26 are shown in FIG. -It can form on the liquid crystal display device 1 of FIG. For example, the thin film transistor 12 and each of the above drive circuits are formed on the first transparent substrate 41 using low-temperature polysilicon to constitute a TFT array substrate. Here, the liquid crystal 43 is filled in the gap between the first substrate 41 and the second substrate 42.
In the color liquid crystal display device 1 shown in FIGS. 2 and 3, the auxiliary capacitor 16 is formed by the auxiliary capacitor electrode 48 a, the insulating films 52 and 59, and the pixel electrode 47 provided on the first substrate 41. However, other structures may be used according to the pixel structure of the color liquid crystal display device 1.

  FIG. 4 is a block diagram showing an equivalent circuit of a pixel structure of 1 row and 3 columns, where Clc indicates a pixel capacitance and Ccs indicates an auxiliary capacitance 16. The subscripts of the switching element 12 indicate rows and columns, and the auxiliary capacitance line in the first row is indicated by CS1.

Now, when a rectangular wave signal is applied to the signal line and the counter electrode, the scanning line is selected, and the switching element 12 of the pixel 15 connected to the scanning line (G ₁ ) is turned on so that the pixel electrode A voltage based on the display signal is applied to 13. That is, in the on state, the auxiliary capacitance line driving circuit 26 shown in FIG. 1 applies the first voltage to the other end of the auxiliary capacitance 16, that is, the auxiliary capacitance electrode 17 in the first cycle of the counter electrode drive signal. To do. Subsequently, the second voltage is applied during p + 1/2 period (where p is 0 or a natural number) after the first period of the counter electrode drive signal, and during the holding period after p + 1/2 period. Outputs a signal for opening. The counter electrode driving signal is output at a predetermined timing in accordance with the scanning line driving signal of each row.
Thereby, the absolute value of the potential difference between the pixel electrode 13 and the counter electrode 14 can be increased.

FIG. 5 is a waveform showing an example of a driving method of the liquid crystal display device 1 according to the present invention, in which (A) shows a driving signal for a counter electrode, (B) shows a driving signal for an auxiliary capacitance line, and (C) shows The signal line drive signal, (D) the scan line drive signal, and (E) the voltage applied to the pixel 15 together with the voltage of the pixel electrode 13 (voltage difference between the pixel electrode 13 and the counter electrode 14). ing.
As shown in FIG. 5A, the counter electrode drive signal is a rectangular wave that repeats high level (VcomH) and low level (VcomL) amplitudes corresponding to the pulse width of the scan line drive signal. The waveforms have high-level (VcomH) and low-level (VcomL) amplitudes at t0 to t1 and t5 to t6 when the scanning line driving signal is turned on, respectively. The waveform shown in FIG. 5C is an example of a signal line drive signal when the maximum voltage is applied to the liquid crystal. As shown in FIG. 5D, the scanning line driving signal is a rectangular wave, and the so-called high level amplitude in which the period from t0 to t1 and t5 to t6 is the charging period, and from t1 to t5 and t6 to t10. It has a low level amplitude in which the period becomes the holding period. It should be noted that the time period from t1 to t5 is occupied by several hundred pulses or more, not the several periods shown in the figure. Similarly, it should be noted that the level of the counter electrode drive signal Vcom is a signal inverted from the time period of t1 to t2 in the time period of t5 to t6. This is repeated for each frame.

  Here, in the counter electrode drive signal, the storage capacitor line drive signal, and the signal line drive signal, t0 to t2 are referred to as a first period, and t2 to t4 are referred to as a second period. In addition, one cycle of the scanning line driving signal includes an on period (also referred to as a charging period) in which the switching element 12 is in a conductive state and a holding period in which the switching element 12 is in a non-conductive state.

The auxiliary capacitance line drive signal will be described.
As shown in FIG. 5B, the storage capacitor line drive signal Vcs is applied to the first voltage, that is, the counter electrode 14 when the scan line drive signal is in the charging period (period t0 to t1). The same voltage Vcs1 (Vcs1 = VcomH) as the voltage VcomH, the same VcomL as the voltage applied to the counter electrode 14 at t1 to t2, and the voltage VcomH applied to the counter electrode 14 at the next t2 to t3. Are different second voltages (Vcs2). From t3 to t5, the storage capacitor 16 is brought into a floating state by the storage capacitor line driving circuit 26. That is, when each scanning line is selected, the switching element 12 of the pixel 15 connected to the scanning line (G ₁ ) is turned on, and the voltage based on the display signal is applied to the pixel electrode 13, the auxiliary capacitance line driving circuit 26. Applies a first voltage to each auxiliary capacitance line in the first period of the counter electrode drive signal. Next, in the next half cycle (t2 to t3) of the ON period (t0 to t2) of the counter electrode drive signal, the storage capacitor line drive circuit 26 is synchronized with this storage cycle for each storage capacitor line. In the holding period (t3 to t6) after this half cycle, a signal for opening is output. The auxiliary capacitance line driving circuit 26 applies the voltage signal to the auxiliary capacitance line in each row for each scanning line driving signal in each row.

Thereby, the voltage difference generated in the pixel 15 is held until the next writing. As described above, Vcom and Vcs applied to the storage capacitor line 48 and the counter electrode 14 are both rectangular waves of 50% duty during the scanning signal pulses. The selection / charging operation is performed when the scanning line signal Vg (t0 to t1) is at a high level. When the levels of Vcom and Vcs return to the low level after charging in the period from t2 to t3, Vcs changes from the high level to the low level, and a large voltage difference is generated in the liquid crystal 43. Thereafter (after t3), the voltage Vcs of the auxiliary capacitance line 48 is brought into a floating state in order to maintain a large voltage difference generated in the liquid crystal 43 of the pixel 15. In order to drive the pixel 15 in the alternating current (AC) mode, the roles of the high level and low level of these signals are reversed in the next frame. Therefore, in the next frame (see t5 to t10 in FIG. 5), the level of Vcs is higher than VcomL during the period from t5 to t10.
Note that the period for applying the second voltage is not limited to a half cycle, and may be p + 1/2 cycles (where p is 0 or a natural number). In the following description, the period for applying the second voltage is described as a half cycle.

  As shown in FIG. 5B, the storage capacitor line drive signal is at the same voltage VcomL as the voltage applied to the counter electrode 14 at t5 to t6, that is, when the scan line drive signal is in the charging period. Yes, it is the same first voltage Vcs1 (Vcs1 = VcomH) as the voltage applied to the counter electrode 14 at t6 to t7, and the voltage (VcomL) applied to the counter electrode 14 at the next t7 to t8 A different second voltage (Vcs2). From t8 to t10, the other end of the auxiliary capacitance 16, that is, the auxiliary capacitance line 48 including the auxiliary capacitance electrode 17 is brought into a floating state by the auxiliary capacitance line driving circuit 26.

The operation principle of the driving method of the present invention will be described in more detail.
The capacitance (Clc) between the counter electrode 14 and the pixel electrode 13 and the actual capacitance (Ccs) between the pixel electrode 13 and the capture capacitance electrode 17 are constant unless the change in dielectric constant of the liquid crystal is taken into consideration. Further, the capacitance (Ccs) between the pixel electrode 13 and the auxiliary capacitance electrode 17 is also constant. Assuming that the potential of the pixel electrode 13 when charging of the pixel 15 is Vpixl, the potential of the counter electrode 14 being charged is VcomW, and the potential of the auxiliary capacitance electrode 17 being charged is Vcsl, the pixel electrode 13 (Pix) has ,
Q = Clc * (Vpix1-VcomW) + Ccs * (Vpixl-Vcsl)
The charge indicated by is charged. When the charging of the pixel 15 (see, for example, t1 in FIG. 5) is completed, the transistor 12 of the pixel 15 is turned off, so that the pixel 15 is in a floating state, and this Q is held constant until the next charging. In the conventional example, the entire potential including Vpix from this state vibrates as shown in FIG. 15 according to the potential of the counter electrode 14.

Here, when only the voltage of the auxiliary capacitance electrode 17 is changed from Vcsl to Vcs2, Q, Clc, and Ccs are constant, so that the potential opening changes immediately after charging. If the pixel potential after the change is Vpix2,
Q = Clc × (Vpixl−VcomW) + Ccs × (Vpixl−Vcsl)
= Clc * (Vpix2-VcomW) + Ccs * (Vpix2-Vcs2)
Therefore, the potential Vpix of the pixel electrode changes by Vpix2-Vpixl = Ccs / (Clc + Ccs) × (Vcs2-Vcsl). Since the voltage applied to the liquid crystal is Vpix−Vcom, if Vcs2 is set so that Vpix2−Vpixl> 0, ie, Vcs2−Vcsl> 0 (see t7 to t8 in FIG. 5), the voltage of the pixel 15 is boosted. It will be. If Vcs2 <Vcsl (see t2 to t3 in FIG. 5), the voltage drops. This is a phenomenon similar to a charge pump used for boosting in an LSI, except that a potential Vcom is involved.

Vcsl (equivalent to Vcom) is applied to the auxiliary capacitance electrode 17 when the pixel 15 is charged, and t2 to t3 (or t7 to t7) after one cycle (that is, when the potential of the counter electrode becomes the same as that during charging). Vcs2 is given at t8). At other timings, the drive power supply for the auxiliary capacitance electrode 17 opens the auxiliary capacitance electrode 17, that is, sets the auxiliary capacitance line in a floating state by setting the impedance to high. By performing such driving, it is possible to maintain the boosted state of the pixel voltage (Vpix) by the application of Vcs2 during the holding period. That is, the potential of the pixel 15 can be boosted and exceeded 4.8 V using Vcs1 and Vcs2 within the voltage limit of the driver LSI.
Here, the point is that when the voltage of the auxiliary capacitance electrode 17 is changed from Vcsl to Vcs2, Vcom is the same potential as when the pixel 15 is charged. It can be realized at this timing that both Vcsl and Vcs2 are voltages that can be supplied from the driver LSI (the difference from Vs is within 4.8 V). The p + 1/2 period (p is 0 or a natural number) after the first period of the counter electrode driving signal indicates a period in which this condition is satisfied.

  In the first embodiment, since the circuit operation is similar to a charge pump that changes the potential of the auxiliary capacitance electrode 17 and thereby boosts the pixel potential, the liquid crystal can be driven with a voltage higher than the output voltage of the LSI. Become. As a result, the auxiliary capacitance line 48 is made independent of the counter electrode wiring, so that a signal necessary for such a boosting operation can be freely applied.

  In the first embodiment, as an example, the auxiliary capacitance electrode 17 is driven by wiring from the driver LSI. However, a drive circuit using a thin film transistor made of amorphous silicon or polysilicon is formed adjacent to the display area. It may be driven by this. In this case, since the number of wirings around the thin film transistor 12 and the liquid crystal display unit 10 is reduced, it is possible to obtain an effect that it is not necessary to enlarge the LSI.

In the first embodiment, the auxiliary capacitor 16 is boosted by a voltage change applied to the auxiliary capacitor electrode 17. The same effect can be obtained by adding another electrode as the auxiliary capacitor 16 while keeping the same configuration of the conventional pixel auxiliary capacitor. 6, 7A and 7B show another embodiment of the present invention.
FIG. 6 shows a block diagram in the case where the auxiliary capacitor 16 and the pixel auxiliary capacitor 18 are separately provided, and FIGS. 7A and 7B are diagrams showing specific pixel structures.
As shown in FIG. 6, the auxiliary capacitor includes first and second auxiliary capacitors 16 and 18. In this configuration, the first auxiliary capacitor 16 is simply called an auxiliary capacitor, and the second auxiliary capacitor is called a pixel auxiliary capacitor 18. The auxiliary capacitor electrode 17 at the other end forming the auxiliary capacitor 16 is connected to the CS terminal, and the other electrode of the pixel auxiliary capacitor 18 is connected to the COM electrode (also connected to the counter electrode 14). A voltage is independently applied to the electrodes of the capacitor 16 and the pixel auxiliary capacitor 18. That is, one end of the auxiliary capacitor 16 and the pixel auxiliary capacitor 18 is connected to the pixel electrode 13 in common, and the other ends of the auxiliary capacitor 16 and the pixel auxiliary capacitor 18 are individually provided. The other end of the auxiliary capacitor 16 is connected to the auxiliary capacitor line driving circuit 26, and the other end of the pixel auxiliary capacitor 18 is connected to the counter electrode 14. That is, the pixel auxiliary capacitor 18 is connected in parallel with the pixel 15.

  7A is a plan view of the pixel structure, and FIG. 7B is a cross-sectional view thereof. In this case, the auxiliary capacitance electrode 17 is formed at the other end of the auxiliary capacitance 16 disposed in the pixel 15 of each row, and the auxiliary capacitance electrodes 17 are connected to each other by the auxiliary capacitance line 48. The electrode wiring of the auxiliary capacitor 16 can be arranged in parallel with the electrode wiring of the pixel auxiliary capacitor 18. Therefore, there is an advantage that the degree of freedom increases on the pattern layout. For example, the patterns of the opposing electrodes for forming the auxiliary capacitor 16 and the pixel auxiliary capacitor 18 are arbitrarily designed. As a result, it is possible to form a storage capacitor 16 that has sufficient storage capacity for holding charges to be stored in the pixel and at the same time boosts the voltage (Vpp, peak-to-peak voltage) applied to the liquid crystal cell 15. .

FIG. 8 is a block diagram showing a second embodiment of the liquid crystal display device 30 of the present invention. The storage capacitor line driving circuit 26 includes first and second storage capacitor driving transistors 31 and 32 connected to each storage capacitor 16 driven by each scanning line (G _{1 to} G _m ). Yes.
The n pixel electrodes 13 connected to each scanning line of the scanning line driving circuit 20 are connected to one end of the auxiliary capacitor 16 and the other end of the auxiliary capacitor 16 is formed as a common electrode. The common electrodes are provided by the number of scanning line driving circuits 20. The wiring composed of the common electrode of the auxiliary capacitance 16 is referred to as auxiliary capacitance lines (Cs1 to Csm) 48. That is, each of the storage capacitor lines 48 is separated from each other, and is driven by the first and second storage capacitor driving transistors 31 and 32 provided at both ends thereof.

The first auxiliary capacitor driving transistors 31 are called CTr _{11 to} CTr _1m because m, which is the number of scanning lines, is arranged in a line along the scanning line driving circuit 20 as shown in the figure. Similarly, the second storage capacitor driving transistors 32 are called CTr _{21 to} CTr _2m because m, which is the number of scanning lines, is arranged along the n columns of the switching elements 12.

  The pixel electrode 13 is connected to the drain of the transistor 12. The counter electrodes 14 that form the liquid crystal cells 15 together with the corresponding pixel electrodes 13 in one row are all connected to each other and connected to the second main electrode of the first auxiliary capacitance driving transistor 31. The auxiliary capacitance electrodes 17 that form the auxiliary capacitance 16 together with the pixel electrodes 13 in the first row are connected to each other and connected to the first main electrode of the first auxiliary capacitance driving transistor 31. Each control electrode of the first auxiliary capacitance driving transistor 31 is connected to each corresponding scanning line. The pixels in the second and third rows are similarly configured. The counter electrodes 14 for the pixel auxiliary capacitors 18 are all connected to a counter electrode wiring (referred to as COM1) serving as a first common electrode. As shown in the drawing, the second main electrodes of the second storage capacitor driving transistor 32 are all connected to the second common electrode wiring (referred to as COM2). The pixels in the second and third rows are similarly configured. In this way, the voltage of the counter electrode 14, which is the electrode at the other end forming the pixel auxiliary capacitor 18, is always controlled to the voltage level of COM1. The voltage applied to the storage capacitor line 48 is controlled to the voltage level of COM2 by the switching state of the first storage capacitor driving transistor 31 and the second storage capacitor driving transistor 32.

In the i-th row first auxiliary capacitance driving transistor 31, the first main electrode is connected to the auxiliary capacitance line 48 connected to the i-th row auxiliary capacitance 16, and the second main electrode is connected to the first common electrode. The control electrode is connected to the _i-th scanning line Gi.

In the second storage capacitor driving transistor 32 in the (i + 2) th row, the first main electrode is connected to the first main electrode of the first storage capacitor driving transistor 31 in the i-th row and the storage capacitor 16. The second main electrodes are all connected to the second common electrode wiring (COM2), and the control electrodes are connected to the (i + 2) th scanning line G _{i + 2} . Therefore, the first auxiliary capacitance driving transistor CTr ₁₁ and the second auxiliary capacitance driving transistor CTr ₂₃ are used for controlling the n pixels 15 (15 ₁₁ to 15 _1n ) in the first row. Similarly, a transistor CTr _1i and a transistor CTrr _{(i + 2)} are used to control each pixel 15 in the i row.

Note that the first auxiliary capacitance driving transistor CTr _{1 (m−1)} and the second auxiliary capacitance driving transistor CTr ₂₁ are used to control the n pixels 15 in the _(m−1) th row. m to n pixels control row includes a first storage capacitor driving transistor CTr _{1 m} and the second storage capacitor driving transistor CTr ₂₂ is used.

The auxiliary capacitance line driving circuit 26 is connected to the first and second auxiliary capacitance driving transistors 31 and 32 for each scanning line, and the second main electrode of the first auxiliary capacitance driving transistor 31 is connected to the counter electrode wiring ( COM1) is connected, and the second main electrode of the second storage capacitor driving transistor 32 is connected to the second common electrode wiring (COM2). When the scanning line is G _{1 in} the first row, the control electrode of the first auxiliary capacitance driving transistor 31 is connected to the scanning line G ₁ in the first row, and the second auxiliary capacitance driving transistor 32 is controlled. The electrode is connected to the _third scanning line G3.

  A reverse phase voltage of the counter electrode wiring (COM1) can be applied to the common electrode wiring (COM2). In this case, of course, a COM inversion signal generation circuit may be provided in the COM driver. However, an inverter circuit composed of a thin film transistor (not shown) is connected to the counter electrode drive circuit 24, and the output of the inverter circuit is connected to the common electrode wiring (COM2). It can be easily realized by connecting to the. FIG. 9 schematically shows an equivalent circuit of one pixel 15.

In FIG. 8, scanning lines G ₁ , G ₂ , G _{3 to} G _m are sequentially selected. When the scanning line G ₁ is selected, the switching element 12 connected to the scanning line G ₁ is turned on, and the signal lines S ₁ and S ₁ connected to the liquid crystal of each pixel 15 and the auxiliary capacitor 16 are connected. ₂ and charged to the potential of S _{3 to} S _m . Selection / charging period of time, the auxiliary capacitance line 48 corresponding to the scanning lines G _1, the voltage of the counter electrode 14 (COM1) is applied by the first auxiliary capacitance driving transistor CTr _11. At this time, the second auxiliary capacitance driving transistor CTr ₂₃ connected to the auxiliary capacitor 16, the scanning line G ₃ is blocked because the non-selected (off) state. Therefore, Vcom2 does not affect the voltage of the auxiliary capacitance electrode 17 that forms the auxiliary capacitance 16. The auxiliary capacitance electrodes 17 are driven only by the first auxiliary capacitance driving transistor CTr _11.

Selection / charging period of the scanning lines G ₁ is terminated becomes a non-selected state, when the scanning line G ₂ is selected, the first and second auxiliary capacitance driving transistor CTr ₁₁ and CTr _23, the gate Since both are low level, both are in an off state. Therefore, the auxiliary capacitance electrode 17 and the pixel electrode 13 becomes a floating state, the voltage charged at the time of selection scan lines G ₁ are holding, to maintain the same potential as the counter electrode 14 (COM1). Thereby, even if Vcom1 changes, the voltage difference between the liquid crystal 15 and the auxiliary capacitor 16 maintains the same state.

Selection / charging period of the scanning lines G ₂ is terminated becomes a non-selected state, the scanning line G ₃ is selected, the second auxiliary capacitance driving transistor CTr ₂₃ is turned on. This is because the scanning lines G ₃ which are connected to the gate of the second auxiliary capacitance driving transistor CTr ₂₃ is at a high level.
Thus, Vcom2 is the voltage COM2 line is applied via the auxiliary capacitance line 48 in a row to the (Cs1) a second auxiliary capacitance driving transistor CTr _23. The storage capacitor electrode 17 voltage from the auxiliary capacitance line drive circuit (COM2) is applied via the second auxiliary capacitance driving transistor CTr _23. At this time, the potential of COM2 is different from that of COM1, and the potential of the auxiliary capacitance electrode 17 changes from COM1 to COM2. Accordingly, at this time, the voltage Vcom1 is supplied to the counter electrode 14 of the liquid crystal cells 15 in one row, while the voltage Vcom2 is supplied to the auxiliary capacitance line 48 (Cs1). This potential change widens the potential difference between the pixel electrode 13 and COM1 via the auxiliary capacitance line 48. That is, the liquid crystal application voltage is boosted by an effect similar to that of the charge pump.

As described above, after the selection of the scanning line G ₃ is completed, the period until the next selection of the scanning line G ₁ is a holding period, and the first and second auxiliary capacitance driving transistors CTr ₁₁ and CTr Both ₂₃ remain off. That is, the auxiliary capacitor 16, the electric charge charged in the writing of COM2 is held, the boost state of the pixel voltage on scan lines G ₁ in this effect is maintained. The boost of the pixel 15 is maintained in a state where a potential difference is generated with respect to COM1. This is because the auxiliary capacitance line 48 (Cs1, Cs2 to Csm) is in a floating state.

FIG. 10 is a waveform showing a driving method of the liquid crystal display device 30 of the present invention, in which (A) shows a driving signal for a counter electrode, and (B) shows a driving signal for a second common electrode (Vcom2), respectively. (C) is a drive signal for a signal line, (D) is a drive signal for the scan line G ₁ , (E) is a drive signal for the scan line G ₂ , and (F) is a drive signal for the scan line G ₃ , (G) is an auxiliary capacitance line drive signal applied to the auxiliary capacitance line 48, (H) is the voltage of the pixel electrode 13 of the pixel 15 and the liquid crystal cell 15 generated between the pixel electrode 13 and the counter electrode 14. Voltage difference.
As shown in FIG. 10A, the counter electrode drive signal (Vcom1) is a rectangular wave, and the second common electrode drive signal (Vcom2) is a reverse phase signal of the counter electrode drive signal (Vcom1). (See FIG. 10B). As shown in FIG. 10C, the signal line drive signal is a rectangular wave having a phase opposite to that of the counter electrode drive signal. As shown in FIGS. 10D to 10F, the scanning line driving signal is a rectangular wave, and the selection / charging period has a high level amplitude. In the scanning line drive signals G _1, t0 to t1 and t5~t6 has an amplitude of high level turns on the charge, other than the above-described on-period, all off, i.e. waveform having an amplitude of the low-level It is. Similarly, the scanning line drive signal G ₂ is, has an amplitude of high level t1~t2 and t6~t7 is on charge, it said non-on period, all off, i.e. the amplitude of the low level It is a waveform that has Scanning line drive signal G ₃ are, has an amplitude of high level t2~t3 and t7~t8 is on charge, other than the above-described on-period, all off, i.e. to have an amplitude of the low-level It is a simple waveform. A period during which the scanning line driving signal is at a low level is referred to as “holding time”.

Figure 10 (G) shows a waveform applied to the auxiliary capacitance electrode 17, when the scanning line drive signal G ₁ is turned on (high level) (t0 to t1), the first storage capacitor driving transistor 31 Is conducted, and Vcom 1 is applied to the auxiliary capacitance electrode 17 during this period. When the scanning line driving signal G ₃ is turned on (t 2 to t 3), the second auxiliary capacitor driving transistor 32 is turned on, and during this period Vcom 2, the auxiliary capacitor electrode 17 disposed facing the pixel electrode 13. To be applied. Since the first and second storage capacitor driving transistors 31 and 32 are not conductive during the period from t3 to t5 other than the above period, the storage capacitor electrode 17 is in a floating state. By using such a drive signal, the potential (Vcs) of the storage capacitor electrode 17 is changed so that the scanning line drive signal G ₁ applied to the first storage capacitor driving transistor 31 and the second storage capacitor driving transistor. The signal center has a waveform in which the signal center rises and falls every cycle of the scanning line driving signal G ₃ applied to 32. For the same reason as described above, the pixel potential can be boosted by this change.

  FIG. 10H shows the waveform of the voltage difference of the liquid crystal pixel 15 together with the pixel electrode 13. As shown in the figure, the waveform of the pixel electrode 13 changes due to the influence of the voltage of the auxiliary capacitance line 48 in the period from t2 to t3, and the voltage applied to the pixel 15 is improved in the period from t3 to t5. As a result, the boosting effect of increasing the absolute value of the potential difference between the pixel electrode 13 and the counter electrode 14 can be obtained by using the auxiliary capacitance line driving circuit 26.

  In the storage capacitor line drive circuit 26 of the second embodiment, signals from the existing scanning line drive are used as control signals for the first and second storage capacitor drive transistors 31 and 32. Similarly, the voltage (Vcom 1) applied to the main electrode of the first auxiliary capacitance driving transistor 31 can be supplied from the counter electrode driving circuit 24. Further, an inverted signal from the counter electrode driving circuit 24 can be supplied to Vcom2 applied to the main electrode of the second auxiliary capacitance driving transistor 32. Therefore, in the storage capacitor line drive circuit 26 of the second embodiment, it is easy to form a signal for driving the storage capacitor. In addition, a new internal / external wiring for driving the auxiliary capacitance is not required, and it is necessary to newly provide an auxiliary capacitance driving terminal of the liquid crystal display device 30 in the driving LSI of the liquid crystal display device 30 or the circuit of the liquid crystal display device 30. There is also an advantageous effect of not.

Many forms and modifications are possible for the waveforms of Vcom1 and Vcom2 and their values. In the second embodiment, the auxiliary capacitor driving signal is the Vcom inversion signal, but this signal may be a DC voltage (VcomDC) corresponding to the amplitude center of Vcom. In this case, there is an effect that the supply of the signal (Vcom2) is further facilitated. Of course, the amplitude may be reduced while maintaining the Vcom inversion timing and the amplitude center. The state where the amplitude becomes zero is the minimum, and this is VcomDC.
Furthermore, the amplitude of Vcom2 shown in FIG. 10 can be changed to a value smaller than the value shown in FIG. For Vcom2, as long as the voltage applied to the liquid crystal cell 15 is boosted, the voltage and period of Vcom2 can be modified in many ways.

Also in the second embodiment, similarly to the first embodiment, the pixel auxiliary capacitor (Cp) 18 may be provided different from the boost auxiliary capacitor (Cs) 16. As shown in FIGS. 6 and 7, another auxiliary capacitor may be provided in parallel with the pixel auxiliary capacitor 18 forming the liquid crystal. Such an example is shown in FIG. FIG. 11 is a block diagram in the case where the pixel auxiliary capacitor 18 and the auxiliary capacitor 16 are separately provided, and FIG. 12 is a diagram showing a specific pixel structure.
As shown in FIG. 11, one end of the pixel auxiliary capacitor 18 and the auxiliary capacitor 16 is commonly connected to the pixel electrode 13, and the auxiliary capacitor electrode 17 serving as the other end of the pixel auxiliary capacitor 18, the other end, and the auxiliary capacitor 16 is Are arranged individually. In the illustrated case, the other end of the pixel auxiliary capacitor 18 is connected to the counter electrode 14, and the other end of the auxiliary capacitor 16 is connected to the auxiliary capacitor line driving circuit 26.

12A is a plan view of a pixel structure, and FIG. 12B is a cross-sectional view thereof. In this case, the other end of the auxiliary capacitor 16 disposed in the pixel 15 of each row forms an auxiliary capacitor line 48. The auxiliary capacitance line 48 can be disposed in parallel with the pixel auxiliary capacitance line. Therefore, there is an advantage that the degree of freedom increases in the pattern layout.
As shown in FIGS. 11 and 12, the structures of the auxiliary capacitor 16 and the pixel auxiliary capacitor 18 for each pixel are the same as those shown in FIGS.
In the above example, the auxiliary capacitance line 48 that is driven independently is arranged in parallel with the capacitance line connected to the opposing electrode of the pixel capacitance. Therefore, there is an advantage that the degree of freedom increases in the pattern layout. Since the patterns of the opposing electrode and the capacitor line for forming the capacitor can be arbitrarily designed, the degree of freedom in pattern design is achieved. This is an advantage. For example, opposing electrode patterns for forming the auxiliary capacitor 16 and the pixel auxiliary capacitor 18 are each arbitrarily designed. Accordingly, the pixel electrode 13 and the auxiliary capacitor electrode 17 are provided so that a storage capacitor for holding charges to be stored in the pixel 15 is sufficient, and at the same time, the voltage (Vpp, peak-to-peak voltage) applied to the liquid crystal cell 15 is boosted. Capacitive coupling caused by the above can be obtained.
Here, the storage capacitor line driving circuit 26 can be provided adjacent to the display unit 10. As described in FIGS. 2 and 3, the auxiliary capacitance line driving circuit 26 is formed on the first transparent substrate 41 using amorphous silicon or polysilicon, similarly to the switching element 12 connected to the pixel 15. A TFT array substrate can be constructed.

In the embodiments of the liquid crystal display devices 1 and 30 described above, each auxiliary capacitance line 48 intersects with the signal line 45.
FIG. 13 is a schematic cross-sectional view showing the intersection of the signal line 45 and the auxiliary capacitance line 48 of the pixel shown in FIG. FIG. 13 is a cross-sectional view taken along the line AA in FIG. 2. Since each auxiliary capacitance line 48 intersects with the signal line 45, a parasitic capacitance Cst is formed at each intersection.

  FIG. 14 is a diagram illustrating an equivalent circuit including the parasitic capacitance Cst in the liquid crystal display device 30. As shown in FIG. 14, since the parasitic capacitance Cst is formed at the intersection between the auxiliary capacitance line 48 and the signal line 45, the floating auxiliary capacitance line 48 is connected to the parasitic capacitance C (the parasitic capacitance generated at each intersection). (Capacity) .times.the total capacity of the signal lines n. For this reason, the potential of the auxiliary capacitance line 48 is affected by the average potential of the signal line 45 via the combined capacitance Cn. Since the potential fluctuation of the auxiliary capacitance line 48 causes a boosting change in the pixel column connected to the auxiliary capacitance line 48, the pixel voltage is affected in units of the auxiliary capacitance line 48 by the signal line potential, that is, image data.

Next, in the liquid crystal display devices 1 and 30, a modified example of the pixel that can shield the parasitic capacitance generated at the intersection of the signal line 45 and the auxiliary capacitance line 48 will be described.
FIG. 15 is a partial perspective plan view showing a configuration of a modified example of the pixel, and FIG. 16 is a cross-sectional view taken along line XX of FIG.
As shown in FIG. 15, the pixel 70 includes a parasitic capacitance shielding wiring 72 for shielding a parasitic capacitance Cst generated between the signal line 45 and the auxiliary capacitance line 48. As shown in FIG. 15, the parasitic capacitance shielding wiring 72 has a straight portion 72a and a convex portion 72b.
The parasitic capacitance shielding wiring 72 is arranged in parallel to the auxiliary capacitance line 48 and the auxiliary capacitance electrode 48 a in the region between the auxiliary capacitance line 48 and the switching element 46, and is a straight line parallel to the auxiliary capacitance line 48. Part 7a, and a convex part 72b covering the intersection of the auxiliary capacitance line 48 and the signal line 45. The convex portion 72b extends from the signal linear portion 72a so as to be bent vertically upward on the paper surface. For this reason, the parasitic capacitance shielding wiring 72 is disposed so as to pass through the intersection of the signal line 45 in each column and the auxiliary capacitance line 48 in each row. Note that the convex portion 72 b is provided at the intersection of the signal line 45 and the auxiliary capacitance line 48, and is also simply referred to as an intersection.

  As shown in FIG. 16, in the pixel 70, the gate insulating film 52 formed on the first substrate 41 of the liquid crystal display device 1 shown in FIGS. 2 and 3 is replaced with the first gate insulating film 74. The second gate insulating film 75 is laminated in this order, and a pattern to be a parasitic capacitance shielding wiring 72 is formed on the first gate insulating film 74. The auxiliary capacitance line 48 is formed on the first substrate 41 as in the liquid crystal display device 1.

  In the pixel 70, the auxiliary capacitance line 48 and the signal line 45 formed on the gate insulating film 52 of the liquid crystal display device 1 shown in FIGS. 2 and 3 are formed on the second gate insulating film 75. . There are m parasitic capacitance shielding wirings 72 corresponding to the auxiliary capacitance lines Cs1, Cs2 to Csm shown in FIG.

  FIG. 17 is a schematic cross-sectional view showing the capacitance generated at the intersection of the parasitic capacitance shielding wiring 72 and the signal line due to the addition of the parasitic capacitance shielding wiring 72 in the pixel 70. As shown in the figure, since the auxiliary capacitance line 48 and the parasitic capacitance shielding wiring 72 are opposed to each other with the first gate insulating film 74 interposed therebetween, the first capacitance is interposed between the auxiliary capacitance line 48 and the parasitic capacitance shielding wiring 72. Cross capacitance 76 occurs. Further, since the parasitic capacitance shielding wiring 72 and the signal line 45 are opposed to each other with the second gate insulating film 75 interposed therebetween, the second intersection capacitance 77 is formed between the parasitic capacitance shielding wiring 72 and the signal line 45. Arise. Therefore, the first and second intersecting capacitors 76 and 77 are formed between the auxiliary capacitance line 48 and the signal line 45 between the parasitic capacitance shielding wiring 72 and the auxiliary capacitance line 48 and the signal line 45. A parasitic capacitance that is directly coupled to the line 45 is not formed.

  Although the m parasitic capacitance shielding wires 72 are formed corresponding to the auxiliary capacitance lines Cs1, Cs2 to Csm shown in FIG. 1, a common potential is applied to all the m capacitance wires. The common potential applied in common to the m parasitic capacitance shielding wirings 72 can be a fixed potential such as GND. As a material of the parasitic capacitance shielding wiring 72, it is preferable to use a low-resistance metal in order to prevent a delay of a voltage signal serving as a common potential to be applied.

  As described above, in the pixel 70, the disadvantageous parasitic capacitance generated between the auxiliary capacitance line 48 and the signal line 45 is removed. As described above, the boosting effect using the auxiliary capacitance line 48 (Cs1, Cs2 to Csm) in the floating state is affected by the potential fluctuation of the signal line 45 by providing the parasitic capacitance shielding wiring 72. Therefore, the boosted state of the pixel 70 can be stably maintained.

  Although the potential of the parasitic capacitance shielding wiring 72 of the pixel 70 is a fixed potential such as GND, it may be a voltage (COM1) applied to the counter electrode 14. In this case, a capacitance is formed in a region where the parasitic capacitance shielding wiring 72 and the pixel electrode 47 overlap. This capacitance is effective in stabilizing the potential of the pixel 70 as in the so-called conventional pixel auxiliary capacitance.

The pixel 70 can be manufactured by the following manufacturing method.
A metal layer is deposited on the first substrate 41 and patterned to form a pattern of the gate electrode 51 and the auxiliary capacitance line 48. For the metal layer, light-shielding chromium, chromium alloy, aluminum, aluminum alloy, molybdenum, or the like can be used.
Next, a first gate insulating film 74 having a predetermined thickness is deposited so as to cover the entire surface of the first substrate 41 on which the pattern of the gate electrode 51 and the auxiliary capacitance line 48 is formed. The first gate insulating film 74 is made of an insulating material such as silicon nitride or silicon oxide, like the gate insulating film 52.
Next, a parasitic capacitance shielding wiring 72 is formed by depositing a metal layer on the first gate insulating film 74 and patterning it. As the material of the parasitic capacitance shielding wiring 72, the same material as that of the metal layer that becomes the gate electrode 51 and the auxiliary capacitance line 48 can be used.
A second gate insulating film 75 having a predetermined thickness is deposited on the entire surface of the first gate insulating film 74 on which the pattern of the parasitic capacitance shielding wiring 72 is formed. For the second gate insulating film 75, an insulating material such as silicon nitride or silicon oxide can be used similarly to the gate insulating film 52, and the same material as the first insulating film 74 may be used. The subsequent steps may be performed in the same manner as the manufacturing steps described in the liquid crystal display device 1 in FIG.

Next, another pixel 80 that can be used in the liquid crystal display devices 1 and 30 will be described.
18 is a partial perspective plan view showing the configuration of the pixel 80, and FIG. 19 is a cross-sectional view taken along line XX of FIG.
As shown in the drawing, in the pixel 80, the parasitic capacitance shielding wiring 82 includes a linear portion 82 a disposed on the first substrate 41 so as to be parallel to the auxiliary capacitance line 48, and the second gate insulating film 75. The upper auxiliary capacitance line 48 and the signal line 45 are composed of a convex portion 82 b disposed in a region where the upper auxiliary capacitance line 48 and the signal line 45 intersect. The first gate insulating film 74 is provided with a contact hole 84 for exposing the parasitic capacitance shielding wiring 82. The protruding portion 82 b of the parasitic capacitance shielding wiring is disposed on the second gate insulating film 75 and is connected to the straight portion 82 a of the parasitic capacitance shielding wiring through the contact hole 84.

FIG. 20 is a schematic cross-sectional view showing the capacitance generated at the intersection between the parasitic capacitance shielding wiring 82 and the signal line 45 in the pixel 80.
As shown in the figure, since the auxiliary capacitance line 48 and the convex portion 82b of the parasitic capacitance shielding wiring are opposed to each other with the first gate insulating film 74 interposed therebetween, the auxiliary capacitance line 48 and the convex portion 82b of the parasitic capacitance shielding wiring are arranged. A first intersection capacitance 76 occurs in between. Further, since the convex portion 82 b of the parasitic capacitance shielding wiring and the signal line 45 face each other with the second gate insulating film 75 interposed therebetween, the second portion is interposed between the convex portion 72 b of the parasitic capacitance shielding wiring and the signal line 45. The intersection capacitance 77 is generated. Therefore, the first and second intersecting capacitors 76 and 77 are formed between the auxiliary capacitance line 48 and the signal line 45 between the parasitic capacitance shielding wiring 82 and the auxiliary capacitance line 48 and the signal line 45. A parasitic capacitance Cst that is directly coupled to the line 45 is not formed. Since the projecting portion 82 b of the parasitic capacitance shielding wiring is connected to the straight portion 82 a of the parasitic capacitance shielding wiring via the contact hole 84, the parasitic capacitance line 48 and the signal line 45 are parasitic between the auxiliary capacitance line 48 and the signal line 45. It is shielded by the capacitance shielding wiring 82.

  In FIG. 18, the contact hole 84 is illustrated as being formed in the overlapping portion of the signal line 45 and the parasitic capacitance shielding wiring 82, but this is not a necessary condition, and any position may be provided on the parasitic capacitance shielding wiring 82. Can be formed.

In the above embodiment, a fixed potential such as GND or a voltage (COM 1) applied to the counter electrode 14 is applied to the parasitic capacitance shielding wiring 82 of the pixel 80, similarly to the parasitic capacitance shielding wiring 72 in the pixel 70. Therefore, the signal lines S ₁ by providing the parasitic capacitance shield wiring 82, S _2, S a ₃ to S _n boosting state of the pixel 80 for it is no longer affected by the potential change of can stably be maintained It becomes.

  In the above-described embodiment, when the same potential as that of the counter electrode 14 is applied to the parasitic capacitance shielding wiring 82, the conventional auxiliary capacitance for the pixel is added, and the stability of the potential of the pixel 80 is improved. To do.

The pixel 80 of the embodiment shown in FIG. 18 can be manufactured as follows.
First, a pattern is formed on the first substrate 41 by using the same low resistance conductive film for the auxiliary capacitance line 48 and the linear portion 82a of the parasitic capacitance shielding wiring. Next, a first gate insulating film 74 is deposited to a predetermined thickness, and a contact hole 84 is provided on the straight portion 82a of the parasitic capacitance shielding wiring.
Subsequently, an electrode layer to be a convex portion 82b of the parasitic capacitance shielding wiring is deposited to a predetermined thickness, and a pattern connected to the straight portion 82a of the parasitic capacitance shielding wiring is formed. The material of the convex portion 82b of the parasitic capacitance shielding wiring only needs to be capable of electrostatic shielding. For this reason, the projection 82b of the parasitic capacitance shielding wiring does not need to use a low-resistance metal for preventing delay of the voltage signal unlike the parasitic capacitance shielding wiring 72 of the pixel 70 shown in FIG. A conductive film can be used. Thereby, the aperture efficiency of the pixel 80 is improved as compared with the pixel 70.
Next, a second gate insulating film 75 is deposited on the entire surface of the first gate insulating film 74 to a predetermined thickness. The steps after this step may be performed in the same manner as the manufacturing steps described in the liquid crystal display device of FIG.

  It should be noted that the parasitic capacitance generated between the gate and the drain of the transistor 12 is not clearly described in FIGS. However, as shown by Vpt in FIG. 26, it is needless to say that the small voltage drop caused by this parasitic capacitance is actually considered in determining the drive waveform properly.

  The present invention is not limited to the above-described embodiment, and various modifications are possible within the scope of the invention of the liquid crystal display device and the driving method described in the claims, and these are also within the scope of the present invention. It is clear that it is included.

DESCRIPTION OF SYMBOLS 1,30: Liquid crystal display device 10: Display part 12, 46: Switching element (thin film transistor)
13, 47: Pixel electrode 14, 63: Counter electrode 15, 70, 80: Pixel 16: Auxiliary capacitor 17: Auxiliary capacitor electrode 18: Pixel auxiliary capacitor 20: Scan line drive circuit 22: Signal line drive circuit 24: Counter electrode drive Circuit 26: Auxiliary capacitance line driving circuit 31: First auxiliary capacitance driving transistor 32: Second auxiliary capacitance driving transistor 41: First substrate 42: Second substrate 43: Liquid crystal 44: Scan line 45: Signal Line 48: Auxiliary capacitance line 51: Gate electrode 52: Gate insulating film 53: Semiconductor thin film 54: Protective film 55, 56: Contact layer 57: Drain electrode 58: Source electrode 59: Overcoat film (flattening film)
60, 84: Contact hole 61: Black matrix 62: Color filter element 72, 82: Parasitic capacitance shielding wiring 72a, 82a: Straight line portion 72b, 82b: Convex portion 74: First gate insulating film 75: Second gate insulation Film 76: first intersection capacitance 77: second intersection capacitance

Claims (28)

A scanning line composed of a plurality of rows (where a row is an arbitrary natural number satisfying 1 ≦ i ≦ m), and a signal line composed of a plurality of columns (where the column is an arbitrary natural number satisfying 1 ≦ j ≦ n); A switching element provided at an intersection of the scanning line and the signal line, a pixel electrode connected to an output end of the switching element, a counter electrode, and a liquid crystal cell between the pixel electrode and the counter electrode A pixel matrix of m rows × n columns, an auxiliary capacitor having one end connected to the output terminal of the switching element, and other than the auxiliary capacitor of each row connected to the switching element of each row. A storage capacitor line composed of a plurality of rows having common ends, and a display unit comprising:
A scanning line driving circuit that outputs a scanning line driving signal having an on period in which a switching element is turned on and a holding period in which the switching element is turned off with respect to the scanning line of each row;
A signal line driving circuit for outputting a signal line driving signal to the signal lines in each column;
A counter electrode drive circuit for outputting a drive signal for the counter electrode to the counter electrode;
An auxiliary capacitance line driving circuit that outputs an auxiliary capacitance line driving signal to the auxiliary capacitance lines of each row;
With
The auxiliary capacitance line driving circuit applies a first voltage to the auxiliary capacitance line in a first cycle of the counter electrode drive signal, and a p + 1/2 cycle after the first cycle of the counter electrode drive signal. (Where p is 0 or a natural number), a second voltage is applied, and a signal that is opened in the holding period after this p + 1/2 cycle is output for each scanning line driving signal in each row. A liquid crystal display device. The auxiliary capacitance line driving circuit is composed of first and second driving transistors connected to each auxiliary capacitance line,
A first main electrode of the first driving transistor is connected to the other end of the auxiliary capacitor;
A second main electrode of the first driving transistor is connected to a counter electrode wiring (COM1) serving as a first common electrode;
The control electrode of the first driving transistor is connected to the _i-th scanning line (G _i ),
A first main electrode of the second driving transistor is connected to a first main electrode of the first driving transistor;
A second main electrode of the second driving transistor is connected to a second common electrode wiring (COM2);
2. The liquid crystal display device according to claim 1, wherein the control electrode of the second driving transistor is connected to a scanning line (G _{i + 2} ) of the ( _{i + 2} ) _th row.   The auxiliary capacitor includes first and second auxiliary capacitors, one end of the first and second auxiliary capacitors is connected to the pixel electrode, and the other end of the first auxiliary capacitor is the auxiliary capacitor line driving circuit. 3. The liquid crystal display device according to claim 1, wherein the other end of the second auxiliary capacitor is connected to the counter electrode.   The display section includes first and second substrates, the scanning lines and signal lines are provided on the first substrate, and the counter electrode is provided on the second substrate. The liquid crystal display device according to any one of?   The liquid crystal display device according to claim 4, wherein the auxiliary capacitor includes a wiring provided on the first substrate, an insulating film provided on the wiring, and a transparent electrode provided on the insulating film.   3. The liquid crystal display device according to claim 1, wherein the storage capacitor line driving circuit is provided adjacent to the display portion, and the storage capacitor line driving circuit is formed of a thin film transistor using amorphous silicon or polysilicon. A scanning line composed of a plurality of rows (where a row is an arbitrary natural number satisfying 1 ≦ i ≦ m), and a signal line composed of a plurality of columns (where the column is an arbitrary natural number satisfying 1 ≦ j ≦ n); A switching element provided at an intersection of the scanning line and the signal line, a pixel electrode connected to an output end of the switching element, a counter electrode, and a liquid crystal cell between the pixel electrode and the counter electrode A pixel matrix of m rows × n columns, an auxiliary capacitor having one end connected to the output terminal of the switching element, and other than the auxiliary capacitor of each row connected to the switching element of each row. A storage capacitor line composed of a plurality of rows having common ends, and a display unit comprising:
A scanning line driving circuit that outputs a scanning line driving signal having an on period in which a switching element is turned on and a holding period in which the switching element is turned off with respect to the scanning line of each row;
A signal line driving circuit for outputting a signal line driving signal to the signal lines in each column;
A counter electrode drive circuit for outputting a drive signal for the counter electrode to the counter electrode;
An auxiliary capacitance line driving circuit that outputs an auxiliary capacitance line driving signal to the auxiliary capacitance lines of each row;
With
The auxiliary capacitance line driving circuit is composed of first and second driving transistors connected to each auxiliary capacitance line,
A first main electrode of the first driving transistor is connected to the other end of the auxiliary capacitor;
A second main electrode of the first driving transistor is connected to a counter electrode wiring (COM1) serving as a first common electrode;
The control electrode of the first driving transistor is connected to the _i-th scanning line (G _i ),
A first main electrode of the second driving transistor is connected to a first main electrode of the first driving transistor;
A second main electrode of the second driving transistor is connected to a second common electrode wiring (COM2);
Is connected a control electrode of the second driving transistor i + 2 row scanning lines and (G i _{+ 2),}
The auxiliary capacitance line driving circuit applies a first voltage to the auxiliary capacitance line in a first cycle of the counter electrode drive signal, and a p + 1/2 cycle after the first cycle of the counter electrode drive signal. (Where p is 0 or a natural number), a second voltage is applied, and a signal that is opened in the holding period after this p + 1/2 cycle is output for each scanning line driving signal in each row. A liquid crystal display device.   The auxiliary capacitor includes first and second auxiliary capacitors, one end of the first and second auxiliary capacitors is connected to the pixel electrode, and the other end of the first auxiliary capacitor is the auxiliary capacitor line driving circuit. The liquid crystal display device according to claim 7, wherein the other end of the second auxiliary capacitor is connected to the counter electrode.   The display section and the storage capacitor line driving circuit include first and second substrates, the scanning lines and signal lines are provided on the first substrate, and the counter electrode is provided on the second substrate. The liquid crystal display device according to claim 7 or 8.   The liquid crystal display device according to claim 9, wherein the auxiliary capacitor includes a wiring provided on the first substrate, an insulating film provided on the wiring, and a transparent electrode provided on the insulating film.   8. The liquid crystal display device according to claim 7, wherein the auxiliary capacitance line driving circuit is provided adjacent to the display portion, and the auxiliary capacitance line driving circuit is formed of a thin film transistor using amorphous silicon or polysilicon. A scanning line composed of a plurality of rows (where a row is an arbitrary natural number satisfying 1 ≦ i ≦ m) and a signal line composed of a plurality of columns (where the column is an arbitrary natural number satisfying 1 ≦ j ≦ n) are provided, A switching element is provided at the intersection of the scanning line and the signal line, and a pixel matrix of m rows × n columns composed of liquid crystal cells is arranged between the pixel electrode connected to the output end of the switching element and the counter electrode. A driving method of a liquid crystal display device comprising one end of an auxiliary capacitor connected to the output end of the switching element,
Applying a rectangular wave signal having an on period in which the switching element is turned on and a holding period in which the switching element is turned off as a scanning line drive signal for the switching element,
A rectangular wave signal is applied to the signal line and the counter electrode,
A first voltage is applied to the other end of the auxiliary capacitor in the first period of the counter electrode drive signal, and a p + 1/2 period after the first period of the counter electrode drive signal (here, p Is a 0 or a natural number) by applying a second voltage and setting the floating period during the holding period after the p + 1/2 period,
A driving method of a liquid crystal display device, wherein an absolute value of a potential difference between the pixel electrode and the counter electrode is increased.   The method for driving a liquid crystal display device according to claim 12, wherein the first voltage is set to the same voltage as the counter electrode, and the second voltage is set to a voltage different from that of the counter electrode.   The driving method of the liquid crystal display device according to claim 12, wherein the first voltage is the same voltage as the counter electrode, and the second voltage is the same voltage as an inverted voltage of the counter electrode. Wherein the second voltage is applied in synchronization with the ON period in 2 destinations scanning lines (G i _{+ 2)} of the scan line switching element is connected (G _i), the liquid crystal according to claim 14 A driving method of a display device.   15. The method for driving a liquid crystal display device according to claim 13, wherein the voltage applied to the auxiliary capacitor is a voltage obtained by reducing the amplitude of a signal applied to the counter electrode wiring.   15. The method for driving a liquid crystal display device according to claim 13, wherein the voltage applied to the auxiliary capacitor is a DC voltage corresponding to the amplitude center of a signal applied to the counter electrode wiring. A scanning line composed of a plurality of rows (where a row is an arbitrary natural number satisfying 1 ≦ i ≦ m), and a signal line composed of a plurality of columns (where the column is an arbitrary natural number satisfying 1 ≦ j ≦ n); A switching element provided at an intersection of the scanning line and the signal line, a pixel electrode connected to an output end of the switching element, a counter electrode, and a liquid crystal cell between the pixel electrode and the counter electrode A pixel matrix of m rows × n columns, an auxiliary capacitor having one end connected to the output terminal of the switching element, and other than the auxiliary capacitor of each row connected to the switching element of each row. A display comprising a storage capacitor line composed of a plurality of rows having common ends, and a parasitic capacitance shielding wiring disposed so as to pass through an intersection of the signal line of each column and the storage capacitor line of each row. And
A scanning line driving circuit that outputs a scanning line driving signal having an on period in which a switching element is turned on and a holding period in which the switching element is turned off with respect to the scanning line of each row;
A signal line driving circuit for outputting a signal line driving signal to the signal lines in each column;
A counter electrode drive circuit for outputting a drive signal for the counter electrode to the counter electrode;
An auxiliary capacitance line driving circuit that outputs an auxiliary capacitance line driving signal to the auxiliary capacitance lines of each row;
With
The auxiliary capacitance line driving circuit is composed of first and second driving transistors connected to each auxiliary capacitance line,
A first main electrode of the first driving transistor is connected to the other end of the auxiliary capacitor;
A second main electrode of the first driving transistor is connected to a counter electrode wiring (COM1) serving as a first common electrode;
The control electrode of the first driving transistor is connected to the _i-th scanning line (G _i ),
A first main electrode of the second driving transistor is connected to a first main electrode of the first driving transistor;
A second main electrode of the second driving transistor is connected to a second common electrode wiring (COM2);
The control electrode of the second driving transistor is connected to the scanning line (G _{i + 2} ) in the ( _{i + 2} ) _th row,
The auxiliary capacitance line driving circuit applies a first voltage to the auxiliary capacitance line in a first cycle of the counter electrode drive signal, and a p + 1/2 cycle after the first cycle of the counter electrode drive signal. (Where p is 0 or a natural number), a second voltage is applied, and a signal that is opened in the holding period after this p + 1/2 cycle is output for each scanning line driving signal in each row. A liquid crystal display device.   The auxiliary capacitor includes first and second auxiliary capacitors, one end of the first and second auxiliary capacitors is connected to the pixel electrode, and the other end of the first auxiliary capacitor is the auxiliary capacitor line driving circuit. The liquid crystal display device according to claim 18, wherein the other end of the second auxiliary capacitor is connected to the counter electrode.   The liquid crystal display device according to claim 18, wherein a DC voltage is applied to the parasitic capacitance shielding wiring.   The liquid crystal display device according to claim 18, wherein a driving signal for a counter electrode is applied to the parasitic capacitance shielding wiring.   The display unit and the storage capacitor line driving circuit include first and second substrates, the scanning lines and signal lines are provided on the first substrate, and the counter electrode is provided on the second substrate. The liquid crystal display device according to claim 18.   23. The liquid crystal display device according to claim 22, wherein the auxiliary capacitor includes a wiring provided on the first substrate, an insulating film provided on the wiring, and a transparent electrode provided on the insulating film.   19. The liquid crystal display device according to claim 18, wherein the auxiliary capacitance line driving circuit is provided adjacent to the display portion, and the auxiliary capacitance line driving circuit is formed of a thin film transistor using amorphous silicon or polysilicon.   The liquid crystal display device according to claim 18, wherein the parasitic capacitance shielding wiring is provided between the switching element and the auxiliary capacitance, and is provided in parallel with the auxiliary capacitance line.   The first gate insulating film and the second gate insulating film are disposed on the first substrate, and the parasitic capacitance shielding wiring is disposed on the first gate insulating film. 22. A liquid crystal display device according to 22.   A straight line portion of the parasitic capacitance shielding wiring is disposed on the first substrate, and an intersection portion of the parasitic capacitance shielding wiring is disposed on the first gate insulating film. The liquid crystal display device according to claim 22, wherein the liquid crystal display devices are connected through a contact hole disposed in the first gate insulating film.   28. The liquid crystal display device according to claim 27, wherein an intersection of the parasitic capacitance shielding wiring is made of a transparent electrode material.

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