TW200926128A - Liquid crystal display device and its driving method - Google Patents

Abstract

A liquid display device is provided with a pixel voltage which can exceed the output voltage of a driver LSI, and a method of driving the same. A liquid crystal display device is disclosed comprising a display part 10, a scanning line driving circuit 20, a signal line driving circuit 22, a counter electrode driving circuit 24 for providing counter electrodes with a counter electrode driving signal reversed in phase from a signal line driving circuit, and auxiliary capacitance 16 having one end connected to an output end of each of switching elements 12, and an auxiliary capacitance line driving circuit 26 for driving a plurality of auxiliary capacitance lines arranged in rows, each of which connects to the switch element 12 in each row and has ends of such auxiliary capacitances 16 in each row commonly connected thereto, wherein the auxiliary capacitance line driving circuit is adapted to apply a first voltage to the auxiliary capacitance lines for a first half cycle of the counter electrode driving signal and apply a second voltage thereto for a (p+1/2)th cycle after the first period of the counter electrode driving signal where p is 0 or a natural number, said auxiliary capacitance line driving circuit making the auxiliary capacitance line in a floating condition after said (p+1/2)th cycle during the remaining holding time.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly to a liquid crystal display capable of boosting a pixel voltage independently of an auxiliary capacitor electrode that drives a pixel independently of a counter electrode Device and its driving method. [Prior Art] A conventional liquid crystal display device applies a voltage to a liquid crystal by a switching element such as a thin film transistor (TFT) provided on each pixel composed of a liquid crystal. Fig. 21 is a view schematically showing the structure of one pixel component of the conventional liquid crystal display device, and Fig. 22 is a view schematically showing the pixel structure of one column. The pixel electrode (Pix) 101 is charged to the source potential by the transistor 102. A voltage (Vcom) for driving the counter electrode is applied to the counter electrode (COM) 103, and a potential difference between the counter electrode 1〇3 and the pixel electrode 101 becomes a liquid crystal driving voltage (Vied). A storage capacitor electrode (Cs) 105 is provided on the substrate 104 side. The storage capacitor electrode 1〇5 relaxes the potential fluctuation at the pixel electrode 1〇1 due to the gate current of the transistor 1〇2 or the leakage current when it is turned off. The wiring of this auxiliary capacitor electrode 105 is usually laid in parallel with the gate wiring. This wiring is connected to the counter electrode 103. Thereby, the potential of the auxiliary capacitor electrode 105 becomes a common potential with the counter electrode 103. The liquid crystal is AC driven to prevent branding or electrical decomposition. Fig. 23 is a timing chart showing an example of a driving waveform of the liquid crystal display device. (A) shows a voltage waveform applied to the counter electrode, (B) shows a signal line voltage waveform, and (C) shows a scanning line voltage waveform, (d) ) indicates the liquid crystal drive 200926128 dynamic voltage waveform. As shown in the figure, the voltage waveform (Vcom) applied to the counter electrode and the voltage waveform (Vs) applied to the source electrode of the transistor are rectangular waves, and the scan line voltage is a voltage applied to the gate electrode of the transistor ( Vg) » As shown in Figure 23(C), when a high level of voltage is applied to the gate, the transistor will conduct and the transistor will become non-conductive when the voltage applied to the gate becomes high. The liquid crystal driving voltage (Vied) changes up and down all in accordance with the waveform of the voltage (Vcom) applied to the counter electrode during the holding period in which the transistor is turned off. Therefore, the liquid crystal driving voltage is applied to the gate. Each cycle of the voltage becomes a positive and negative voltage and is AC driven. In terms of driving the liquid crystal display device, a voltage of about ±4 to 5 V is required for AC driving. As shown in Fig. 23, the AC drive voltage is generated by a combination of a signal line voltage (Vs) and a rectangular wave of the counter electrode voltage (Vcom). These signal waveforms are supplied from the driver LSI. In recent years, LSI's low voltage has been continuously improved, and the voltage between Vcom and Vs is about 4.8V at the maximum. This voltage limitation is not absolute. However, in order to output the above voltage from the driver LSI, it is necessary to change the withstand voltage design of the LSI, and the area and cost of the LSI are greatly increased. Since it is necessary to drive a liquid crystal display device as described above, a voltage of about ±4 to 5 V is required, so that it can be said that it is a barely good balance. However, in a liquid crystal display device (a vertical alignment mode or an n-type liquid crystal in a lateral electric field mode) developed in recent years, in order to fully exhibit its performance, there is a need for a voltage exceeding 5 V. In today's LSI There will be a slight lack of capacity in the middle. However, in the liquid crystal display device disclosed in Patent Document 1, the auxiliary capacitor electrode and the counter electrode are not connected, but the auxiliary capacitor line driver 200926128 is additionally provided with the thyristor line 〇 Dynamic circuit. In this case, the auxiliary capacitor is formed by the auxiliary capacitor electrode, the electrode 'and the insulating layer interposed between these electrodes. In Patent Document 1, a liquid crystal display device in which a voltage different from that of a counter electrode is applied to a storage capacitor from a storage capacitor line driving circuit has been disclosed. Fig. 24 is a view showing a block diagram of a liquid crystal display device, a waveform of a gate signal and a storage capacitor line drive signal, and a waveform applied to a pixel, respectively, disclosed in Patent Document 1. In Fig. 24, a display area ill indicated by a broken line is a display portion for displaying a predetermined image by a plurality of pixels. The display unit is scanned by the scanning lines G, G2, G3, ..., Gn, and signals are displayed by the signal lines Si, S2, and Sr__Sm. On the scanning lines Gr G2, G3...G. A thin film transistor (TFT) 14 is disposed on the intersection with the signal lines S2, S3, ..., Sm. The liquid crystal cell 115 is disposed on the pixel electrode portion connected to the drain of each of the thin film electrodes 114. The pole of the transistor is connected to the scanning line G, and the source is connected to the signal line S. The scanning line driving circuit 116 sequentially scans the scanning lines Gi and G2 Gr_·G„, and selects one column of pixel lines for each horizontal period. The signal driving circuit 117 passes through the respective signal lines S>, S2. S^__Sm outputs a signal, and the transistor 114 applies a pixel voltage to one column of liquid crystal cells selected by the scan driving circuit 116 in one horizontal period. In addition, the counter electrode 118 and its wiring line Each of the liquid crystal cells 115 is disposed on the second transparent substrate. The two substrates sandwich the liquid crystal cell 115. The counter electrode driving circuit 119 applies a common counter electrode voltage to all the liquid crystal cells by the counter electrode 118. V com. 200926128 of each pixel is provided. One end of the auxiliary capacitor 112 is connected to the drain of each transistor 114, and the other end is connected to the auxiliary capacitance line 113 different from each scanning line. The auxiliary corresponding to the scanning line G! The capacitor line 113 is connected to the first output end of the auxiliary capacitance line driving circuit 110, and the auxiliary capacitance line 113 corresponding to the scanning line G2 is connected to the second output end of the auxiliary capacitance line driving circuit 110. The auxiliary lines Z3 to Gn are auxiliary. Capacitor line 113 also Comp is connected corresponding to the scanning line G, ~ G », the driving storage capacitor voltages at different timings Vstl~Vstn will drive the first output terminal of the secondary circuit 110 from the ~ _ storage capacitor line are respectively a first output terminal η

D output. Fig. 25 is a timing chart showing the operation of the liquid crystal display device of Patent Document 1, and Fig. 25(A) is a view showing the gate signals Gsi, .· > Gsie, 2-, from the respective scanning lines Gi, G2, ... 25(B) shows changes in the auxiliary capacitance line drive voltages Vstl and Vst2··· outputted from the auxiliary capacitance line drive circuit 1 10 . The gate signal Gsn'Gsu" is output from the scanning line driving circuit 116 of Fig. 24 and selects the pulse wave of the scanning line, and has a repetition period of one frame. The voltage of the gate β signal G&ampere becomes the voltage Vgh when each pixel of one column is selected, and is held at the voltage Vgl when it is not selected. The auxiliary capacitance line driving voltages Vstl and Vst2..· are binary voltage signals having an amplitude of ΔVst. As shown in the figure, it is applied to one end of each liquid crystal cell 115 by the auxiliary capacitor 112. Further, the auxiliary capacitance line drive voltage Vstl for the scanning line 〇! is slightly delayed after the gate signal Gsu" falls and the amplitude changes only by ΔVst. Similarly, the amplitude of the auxiliary capacitance line drive voltage Vs t2 is changed. Fig. 26 is a waveform diagram of voltages applied to respective pixels 200926128 of the liquid crystal display device of Patent Document 1. The gate signal GSie as shown in the same figure is output from the scanning line driving circuit 116 to the selected scanning line Gi (i = 1 to η). When each pixel of one column is selected, the voltage becomes Vgh, and when it is not selected, the counter electrode voltage Vcom whose voltage becomes Vgl»DC is output from the counter electrode driving circuit 119. Vcom is fixed. The output voltage Vd outputted from the drain of the transistor 114 is in one frame period, and the output level is changed to the positive and negative sides centering on the counter electrode voltage Vcom. When the gate is selected, the pixel electrode of the liquid crystal cell 115 located on the scanning line is charged to the signal voltage Vsig supplied by the signal line S, but between the drain and the gate of the parasitic capacitance of the transistor 114. Under the influence of the capacitance Cdg, when the gate signal Gsii changes from Vgh to Vgl, the output voltage Vd changes to a voltage that is only Vpt lower than Vsig. Thereafter, as shown in the figure, if the auxiliary capacitor driving voltage Vst of the auxiliary capacitance line driving circuit 110 drops only the AVst voltage, the output voltage Vd may even decrease by K·ΔVs t. Here, K is dependent on the constant of the capacitance 包含 included in the capacitance combination. In this manner, the voltage Vd1 which is the difference between the counter electrode voltage Vcom and the voltage Vd of the pixel electrode is applied as the driving voltage of the liquid crystal cell 115. More specifically, the above constant K is given by the following formula (1). K = Cst / (Clc + Cst + Cdg) (1) Here, the capacitance of the Cst-based auxiliary capacitor 112, the capacitance of the Clc-based liquid crystal cell 115, and the parasitic capacitance between the drain-gate of the Cdg-based transistor 114. In the next frame, when the display signal is written to each liquid crystal cell 115 of the same scan line, when the scan line Gi is selected again, the liquid crystal of the pixel (i, j) is utilized by the signal line S 』 The signal voltage Vsig -10- 200926128 supplied from the cell 115 is charged. Vsig is centered on the Vcom level and has a real waveform. As shown in Fig. 26, in the transistor 14, the voltage Vgh of the gate signal Gsig.i is changed to Vgl under the influence of the parasitic capacitance Cdg between the drain electrodes, and the output voltage Vd is only decreased by Vpt. When the auxiliary capacitor driving voltage Vst of the auxiliary capacitance line driving circuit 110 rises by AVst, the output voltage Vd rises only from the current voltage Κ·Δ, and the above constant is used. Thereafter, the rising voltage is maintained, and the difference between the output voltage Vd and the counter electrode voltage Vcom is applied to the liquid crystal cell 1 15 as the driving voltage Vd1. As such, the LCD panel is AC driven in one frame period. As shown in Fig. 25, in the case where the voltage Vd is lowered with respect to the counter electrode voltage Vcom, the output voltage Vd is relatively opposite to (Vsig + Vpt) by the signal from the auxiliary capacitance line driving the electric S. The K·AVst is shifted in the lower direction at the electrode voltage Vcom. Further, when the output voltage Vd is increased for the counter electrode voltage Vcom, the phase (Vsig-Vpt) of the signal from the auxiliary capacitance line drive circuit 110, the output voltage Vd is higher in the direction with respect to the counter electrode voltage. Pan Κ Δ Vst. Therefore, according to Patent Document 1, since the liquid crystal cell 15 is shown, when the driving voltage Vd1 is higher than VdlO, the signal Vsig with respect to the predetermined driving voltage Vdll can be reduced. In this way, since the output power given to the liquid crystal cell 115 is only shifted by K·AVs in the direction away from the counter electrode voltage Vcom, the amplitude Vspp' of the signal line can be compared with the signal line of the conventional liquid crystal cell. After that, only on Vst. When the power is turned off, it is outputted by the %110 phase, which is smaller than the Vcom black Vdll voltage Vd t, and the vibration -11-200926128 V s p p. In the method of driving the storage capacitor electrode described in Patent Document 1, a DC voltage ' is applied to the counter electrode to drive the potential of the storage capacitor electrode in synchronization with the frame period so as to be independent of the counter electrode, thereby driving the liquid crystal drive. The increase in voltage (Vied). However, the output signal Vstl from the auxiliary capacitance line drive circuit 110 has a binary voltage signal having an amplitude of AVst which is slightly delayed after the gate signal G"u falls and the amplitude changes only by ΔV st. Therefore, it must be targeted The auxiliary capacitance line drive voltage Vstl of the scanning line G! is set to a waveform that is shifted from the scanning line 〇 to the on-period. Therefore, the signal of the auxiliary capacitance line driving circuit is due to the pair of signal lines, scanning lines, and opposite reading poles. The circuit configuration is complicated, and the circuit configuration is complicated. [Patent Document 1] JP-A-2001 _25 5 85 丨罅 [Summary of the Invention] [Problems to be Solved by the Invention] In the liquid crystal display device, the liquid crystal driving voltage (Vied) is applied by a combination of a signal line voltage (Vs) and a rectangular wave of the counter electrode voltage (Vcom). Therefore, in the case where it is necessary to increase the liquid crystal driving voltage. In order to increase the signal line voltage without using a driving LSI having a large output voltage, it is considered to drive the auxiliary capacitor as in Patent Document 1 without using a driving LSI having a large output voltage. Further, the liquid crystal driving voltage is increased, but in the case of Patent Document 1, the DC power is used to drive the extreme electric current of the liquid crystal liquid power which is displayed without the setting of the mounting state. 3 Wipe the 2 wave M-dance in the moment, so as to use it. The use of the appropriate, ie ί Ϊ ιρτ 1\1 to the law-12-200926128, there will be no way to obtain the rectangular electrode to drive the counter electrode voltage, Further, in view of the above-mentioned problems, an object of the present invention is to provide a liquid crystal display device in which a boosting electrode is provided inside a pixel to make it easier. In order to obtain a driving operation similar to that of the charge pump, it is possible to obtain a pixel voltage that exceeds the output voltage of the driver LSI for liquid crystal display. Another object of the present invention is to provide a driving method of the liquid crystal display device. Means for Solving the Problem In order to achieve the above-described object, the first configuration of the liquid crystal display device of the present invention includes a display unit that is composed of: a scanning line, It consists of a complex column (where the 'column is any natural number of ISiSm); a signal line consisting of a plurality of lines (where the 'row is any natural number of lSjSn); the switching element 'is set on the scan line and a cross section of the signal line; a pixel electrode connected to the output end of the switching element; a counter electrode; a pixel matrix of m columns xn rows, wherein the liquid crystal cell is disposed between the pixel electrode and the counter electrode; The auxiliary capacitor has one end connected to the output end of the switching element; and an auxiliary capacitance line composed of a switching element connected to each column and having the other end of the auxiliary capacitance of each column become a common plurality of columns; the scanning line driving circuit, The scan line output signal for each column has a drive signal for a scan line having a switch-on period in which the switching element is turned on and a period in which the switching element is turned off; the signal line driving circuit outputs a signal signal for the signal line to the signal line of each row; To the electrode driving circuit, which outputs a driving signal for the counter electrode to the counter electrode; and the auxiliary capacitor line driving circuit, which outputs the auxiliary capacitor line output auxiliary-13-200926128 for each column a line drive signal; and the auxiliary capacitance line drive circuit applies a first voltage to the auxiliary capacitance line in the first period of the counter electrode drive signal, and p + 1 after the first period of the counter electrode drive signal The second voltage is applied to the /2 cycle (here, p is 0 or a natural number), and in the hold period after the p+1/2 cycle, the output is set to be on with each drive line for each scan line. The signal of the state. According to the liquid crystal display device of the present invention, the auxiliary capacitor is driven by the auxiliary auxiliary P capacitor line driving circuit, and the boost state of the pixel voltage (Vpix) can be maintained during the holding period, and the contrast of the pixel can be improved. Therefore, the voltage within the voltage limit of the driver LSI used in the liquid crystal display device can be used, and the potential of the pixel can be raised. In the above configuration, it is preferable that the auxiliary capacitance line drive circuit is composed of the first and second driving transistors connected to each of the storage capacitor lines, and the first main electrode and the auxiliary capacitor of the first driving transistor. The other end is connected, and the second main electrode of the first driving transistor is connected to the g-electrode wiring (COM1) serving as the first common electrode, and the control electrode of the first driving transistor and the scanning line of the i-th column (Gi) The first main electrode of the second driving transistor is connected to the first main electrode of the first driving transistor, and the second main electrode of the second driving transistor is connected to the second common electrode wiring (COM2). The control electrode of the second driving transistor is connected to the scanning line (Gi + 2) of the i-th + 2 column. A second configuration of the liquid crystal display device of the present invention includes a display portion which is composed of a scanning line composed of a plurality of columns (here, the column is an arbitrary natural number of 1 S i S m ); a signal line , which consists of a plurality of lines (here, the line is an arbitrary natural number of lSjSn); the switching element, which is set in the scan-14-200926128, and the column-replica traces the pair of electric drives and the auxiliary f»SJ. Momentum: Arrangement: Capacity;

a cross section of the 线 line and the signal line; a pixel electrode connected to the output end of the switching element; a counter electrode; a pixel matrix of m columns xn rows, which is provided with a liquid crystal cell between the opposite electrodes of the pixel electrode An auxiliary capacitor having one end connected to an output end of the switching element; and an auxiliary capacitance line composed of a series connected to each switching element and having the other ends of the auxiliary capacitors of the respective columns become a common sequence; the scanning line driving circuit' The scan line output for each column has a drive signal for the sweep line in which the switching element is turned on and the off period; and the signal line drive circuit drives the signal line for the signal line of each line; To the electrode driving circuit, the driving signal for the counter electrode is opposite to the counter electrode; and the auxiliary capacitance line of the auxiliary capacitance line driving circuit's auxiliary capacitance line for outputting the auxiliary capacitance line; and the auxiliary line driving circuit is connected to Each of the auxiliary capacitor lines is composed of first and second operative transistors, and the first main electrode of the first driving transistor is connected to the other end of the auxiliary capacitor, and the first driving transistor is 2 The main electrode is connected to the counter electrode wiring (COM 1) of the first common electrode, and the control electrode of the first driving transistor is connected to the scanning line (Gi) of the i-th column, and the first main electrode of the second driving transistor The electrode is electrically connected to the first main conductor of the first driving transistor, the second main electrode of the second driving transistor is connected to the second common electrode line (COM2), and the control electrode of the second driving transistor and the i + 2 scan line (Gi + 〇 connection, the auxiliary capacitance line drive circuit is the auxiliary line, and the first voltage is applied to the counter electrode drive signal in the first cycle after the first cycle of the counter electrode driving signal. The second voltage is applied to the +1/2 cycle, p is 0 or a natural number. In the hold period after the p+1/2 cycle, the drive signal is used for each scan line of each column. -15- 200926128 A signal that is set to the on state. According to the above configuration, the auxiliary capacitance drive circuit can be realized by using the two transistors provided in each of the storage capacitor lines and the voltage applied to the counter electrode wiring and the scanning line voltage. The auxiliary capacitor can be driven by the auxiliary capacitor driving circuit to boost the pixel. A third configuration of the liquid crystal display device of the present invention includes a display portion composed of a scanning line composed of a plurality of columns (here, the column is an arbitrary natural number of 1 S i S m _ ); a line consisting of a plurality of lines (here, the line is any natural number of 〇lSjSn); a switching element disposed at an intersection of the scan line and the signal line; and a pixel electrode connected to the output end of the switching element a counter pixel; a pixel matrix of m columns xn rows, which is formed by arranging liquid crystal cells between the pixel electrode and the counter electrode; an auxiliary capacitor having one end connected to the output end of the switching element; the auxiliary capacitance line And consisting of a plurality of columns connected to the switching elements of the columns and having the other ends of the auxiliary capacitors of the respective columns become common; and a parasitic capacitance shielding wiring which is arranged to pass through the p signal lines of each row and the columns a scanning line driving circuit that outputs, for each of the scanning lines of the respective columns, a scanning line driving signal having a switching element in an on period and an off period; and a signal line driving circuit a signal line output signal line driving signal for the row; a counter electrode driving circuit for outputting a counter electrode driving signal for the counter electrode; and a auxiliary capacitance line driving circuit for outputting the auxiliary capacitance line for each column of the auxiliary capacitance line a driving signal; and the auxiliary capacitance line driving circuit is composed of first and second driving transistors connected to each of the auxiliary capacitance lines, and the first main electrode of the first driving transistor is connected to the other end of the auxiliary capacitor, The first main electrode of the first drive/16-200926128 is connected to the counter electrode wiring (COM 1) which is the first common electrode, and the control electrode of the second driving transistor and the scanning line of the third column (Gi The first main electrode of the second driving transistor is connected to the first main electrode of the first driving transistor, and the second main electrode of the second driving transistor is connected to the second common electrode wiring (COM2). The control electrode of the second driving transistor is connected to the scanning line (Gi + 2) of the i-th + 2 column, and the auxiliary capacitance line driving circuit applies the first period to the auxiliary capacitor line in the first period of the driving signal for the counter electrode. 1 voltage, in The second voltage is applied to the P+1/2 period (here, p is 0 or a natural number) after the first cycle of the counter electrode drive signal, and is matched during the hold period after the P+1/2 period. Each of the scanning lines of each column outputs a signal that is set to an on state by a drive signal. In the above configuration, preferably, the auxiliary capacitor is composed of the first and second auxiliary capacitors, and one of the first and second auxiliary capacitors is connected to the pixel electrode, and the other end of the first auxiliary capacitor is connected to the auxiliary capacitor line. a circuit, and the other end of the second auxiliary capacitor is connected to the counter electrode. The boosting of the pixels can be performed by driving an auxiliary capacitor separately provided in addition to the pixel auxiliary capacitor. In the above configuration, preferably, the display unit includes the first and second substrates, the scanning lines and the signal lines are provided on the first substrate, and the counter electrode is provided on the second substrate. The auxiliary capacitor is preferably composed of a wiring provided on the first substrate, an insulating film provided on the wiring, and a transparent electrode provided on the insulating film. The auxiliary capacitance line driving circuit is disposed adjacent to the display portion, and the auxiliary capacitance line driving circuit is composed of a thin film transistor using an amorphous germanium or a polycrystalline germanium. Thereby, it is possible to easily form an auxiliary capacitor driving circuit composed of a thin film transistor on the substrate -17-200926128. In the above configuration, it is preferable that a DC voltage is applied to the parasitic shield wiring. The drive signal for the counter electrode can also be applied to the parasitic shield wiring. Preferably, the parasitic capacitance shielding wiring is disposed between the switching element auxiliary capacitors and is disposed in parallel with the auxiliary capacitance line. The first gate insulating film and the second gate insulating film may be disposed on the first substrate, and the capacitor shielding wiring may be disposed on the first gate insulating film. Parasitic capacitance ^ The linear portion of the wiring is disposed on the first substrate, and the parasitic capacitance shielding intersection portion is disposed on the first gate insulating film, and the intersection portion and the upper portion can be disposed on the first gate The intersection of the contact hole of the pole insulating film and the connection of the raw capacitor shielding spring is preferably made of a transparent electrode material. In order to achieve the above other objects, in the liquid crystal display device driving method of the present invention, the liquid crystal display device is provided with a scan line composed of a plurality of columns (here, any natural number of ISiSm) and by a plural number: Q. a signal line composed of any natural number of lSjSn, a switching element is disposed at an intersection of the line and the signal line, and an m column xn of the liquid crystal cell is disposed between the pixel electrode and the counter electrode connected to the output end of the switch The pixel matrix of the row is formed by connecting one end of the auxiliary capacitor to the output end of the opening. The driving method is to increase the absolute difference of the potential difference between the electrode and the counter electrode by the following action: the application has an opening member The rectangular wave that is turned on and off is used as a scanning signal for the switching element, and a rectangular wave signal is applied to the signal line and the pole, and the opposite end of the auxiliary capacitor is shielded from the opposite direction. Pieces and lines at the parasitic line. The column to be set up by the carrier is ΐ (the first voltage is applied to the first period of the driving signal to the electric electrode -18-200926128 in the first element of the driving element, and the first period of the driving signal for the counter electrode is applied to the scanning element. In the subsequent P + 1/2 period (here, P is 〇 or a natural number), the second voltage is applied, and the holding period after the p + 1/2 period is in a floating state. Preferably, the first voltage is set to be the same voltage as the counter electrode, and the second voltage is set to be different from the counter electrode. Alternatively, the first voltage may be the same as that of the counter electrode. The voltage is set to be the same voltage as the inverted voltage of the counter electrode. Preferably, the first two columns of the scan line (Gi) of the i-th column to which the switching element is connected, that is, the first The scan line of i + 2 columns (the second voltage is applied synchronously during the turn-on period of Gi + 。. It is preferable to set the voltage applied to the storage capacitor to a voltage at which the amplitude of the signal applied to the counter electrode wiring is reduced. Alternatively, the voltage applied to the auxiliary capacitor may be set to be equivalent to being applied to the pair. The DC voltage at the center of the signal amplitude of the electrode wiring. @ With the above configuration, the auxiliary capacitor provided in the pixel is driven by a waveform having a predetermined timing with respect to the signal applied to the scanning line, the signal line, and the counter electrode. The boost state of the pixel voltage (Vpix) can be maintained during the holding period, and the contrast of the pixel can be improved. Therefore, the voltage within the voltage limit of the driver LSI used in the liquid crystal display device can be used, and the potential of the pixel can be raised. [Effects of the Invention] According to the liquid crystal display device of the present invention and the driving method thereof, the auxiliary capacitance driving circuit allows the auxiliary capacitance of the pixel to be driven independently of the counter electrode, thereby enhancing the potential of the pixel with a simple configuration. It is not possible to increase the contrast of the pixel by increasing the output voltage of the LSI by the driver -19-200926128. The auxiliary capacitor drive circuit can use the scan signal in the liquid crystal display device or the signal of the counter electrode wiring, so that it can be used at low cost. To improve the contrast of the pixels. [Embodiment] Hereinafter, the embodiment of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals are used for the same or corresponding components. Fig. 1 is a block diagram showing the configuration of a liquid crystal display device 1 of the present invention. Figs. 2 to 4 are views showing a liquid crystal display device of the present invention. As shown in Fig. 1, the liquid crystal display device 1 of the present invention is composed of a display unit 10 surrounded by a broken line, a scanning line drive circuit 20 disposed around the display unit 10, and a signal line. The driving circuit 22, the counter electrode driving circuit 24, and the auxiliary capacitance line driving circuit 26. The liquid crystal display device 1 is provided with a scanning line composed of a plurality of columns and a plurality of rows on a first transparent substrate (not shown). a signal line having a switching element 12 disposed at an intersection of the scanning line and the signal line, and a pixel 15 composed of a liquid crystal cell disposed between the pixel electrode 13 and the counter electrode 14 connected to the output end of the switching element 12, One end of the auxiliary capacitor 16 is connected to the output end of the switching element 12. Therefore, the column is composed of any natural number of ISiSm and is composed of any natural number of lSjSn. Further, the switching element 12 of the i-th row and the j-th row can be referred to as the switching element 12u. In the case of the illustration, the display unit 10 has a plurality of pixels 15 arranged in a matrix of m columns xn rows. In this case, the gate electrodes (also referred to as control electrodes) of the switching elements 1 2 of the pixels 15 arranged in the respective columns are connected to each other -20-200926128, and the gate electrode wiring is formed. Therefore, the electrode wirings of the 1, 2, 3, and m columns are connected to the scanning lines Gz and G3 to Gm of the scanning line driving circuit 20, respectively, and the scanning is performed. In the switching elements 12 of the pixels 15 arranged in the respective columns, the source (also referred to as the first main electrode) are connected to each other, and the source electrode wiring is formed, and the source electrode wirings of the 1, 2, 3, and n rows are formed. The signal lines 1, S2, S3 to S- are respectively connected to the signal circuit 22, and the display signal is applied to the counter electrode 14 and the drain connected to each of the switching elements 12 (also referred to as the second main electrode). The liquid crystal cell switching element 12 is disposed between the pixel electrodes 13 and is, for example, a transistor. The transistor 1 2 can be a thin crystal produced by using amorphous germanium or low-temperature polycrystalline germanium on the first transparent substrate. As described above, the gate of the transistor 12 is connected to the scanning line and is connected to the signal line S. The wiring of the counter electrode 14 and the counter electrode 14 is provided on the second transparent substrate (not shown) via the liquid crystal element 15. The scanning line driving circuit 20 outputs a scanning line driving signal having a period in which the element 12 is turned on and a period in which the element 12 is turned off for the scanning line of each column. The scanning line driving circuit 20 sequentially scans the respective scans Gi, G2, G3 to Gm, thereby selecting the pixel columns of the weights for each horizontal period. The signal line drive circuit 22 outputs a signal line signal of a predetermined timing which is substantially synchronized with respect to the ON period of the element 12 for the signal lines of the respective rows. In other words, the signal lines Si, S2, S3 to S are passed. To signal. For a liquid crystal cell of a column size selected by the scanning line driving circuit 20 during one horizontal period, the signal line driving circuit 22 passes through the gate electrode Gi > Because of the line drive number. The electrode at 15 ° of the electrode is connected to the trace between the switches and the selected crystal - 21 - 200926128 12 to output the pixel voltage. The counter electrode driving circuit 24 outputs a driving signal for the counter electrode, and applies a common counter electrode voltage (Vcom) to all the liquid crystal cells by the counter electrode 14 formed on the second transparent substrate (not shown). 15. One end of the auxiliary capacitor 16 is connected to the pixel electrode 13 to which the drain of the transistor 12 is connected, and the other end of the auxiliary capacitor 16 is connected to the auxiliary capacitor line driving circuit 26. As shown in Fig. 1, in other words, the other ends of the storage capacitors 16 of the pixels 0 15 arranged in the respective columns are commonly wired to form a storage capacitor line connected to the auxiliary capacitance line drive circuit 26. Therefore, the auxiliary capacitance lines of the 1, 2, 3, and m columns are connected to the first output terminal to the mth output terminal of the auxiliary capacitance line drive circuit 26, respectively. Vcs1 to Vcsm are output from the first output terminal to the mth output terminal, respectively. Further, in the above case, the pixel corresponding to the color display described in the liquid crystal display device 1 as a black-and-white display may be used. Fig. 2 is a plan view showing a part of the first substrate 41 of the color liquid crystal Q display device 1 according to the first embodiment of the present invention, and Fig. 3(A) is a cross section taken along line XX of Fig. 2; 3(B) is a cross-sectional view showing the second substrate 42 including a portion along the YY line of FIG. 2 . As shown in FIG. 2, on the first substrate 41, a plurality of scanning lines 44 and a plurality of signal lines 45 are extended in the column direction and the row direction, respectively. A thin film transistor 46 connected to the two lines 44 and 45 and a pixel electrode 47 driven by the thin film transistor 46 are disposed in the vicinity of the intersections of the two lines 44 and 45. Further, on the side opposite to the scanning line 44 with the pixel electrode 47 interposed therebetween, the auxiliary capacitance line 48 is overlapped with the pixel electrode 47 and arranged along the column direction. -22- 200926128 As shown in Fig. 3(B), in the color liquid crystal display device 1, the 'plate 41 and the plate 42 which is located above the first substrate 41 and which becomes the opposite substrate are substantially rectangular frame-shaped sealing materials. (not shown), the space is sealed by the seal member and the two substrates 41 and 42. Next, the manufacture of the thin film transistor 46 and the like will be described with reference to Fig. 3(A). On the upper surface of the first substrate 41, that is, a predetermined portion facing the second substrate 42, a scanning line 44 including a gate electrode 51 is provided, and a storage capacitor line 48 is provided at a predetermined place, and insulation is provided on the entire surface. Film 52. A semiconductor film 53 composed of the anode is provided at each of the upper surfaces of the gate insulating film 52. A channel protective film 54 is provided on the inner side of the intersection of the semiconductor film 53 and the gate electrode 51 on the upper side of the semiconductor film 53 to the inside. Contact layers 55, 56 made of n-type amorphous are provided on the upper surface of the channel protective film 54 and on the upper surface of the semiconductor thin film 53 on both sides. A drain electrode 57 is provided on the upper surface of one of the contact layers 55. The signal line 45 including the source electrode 58 is disposed on the upper surface of the contact layer 56 and the upper surface of the gate insulating film 52. The thin film transistor 46 is constituted by the gate electrode 51, the gate insulating film 52, the semiconductor film protective film 54, the contact layers 55 and 56, the drain electrode 57, and the source 58. A cover film 59 composed of an insulating material is disposed on the gate insulating film 52 including the thin film transistor 46 and the like. The cover film 59 is also bonded to the first base and the second base, and is placed on the surface of the liquid crystal structure, and the other gate is amorphous, and the other side of the ratio is set to 53. The entire electrode can be flat -23- 200926128 canned film. A contact hole 60 is provided in correspondence with a predetermined portion of the gate electrode 57 of the cover film 59. A pixel electrode 47 is provided at a predetermined portion of the upper surface of the cover film 59. The pixel electrode 47 is formed of transparent electricity composed of ITO. The pixel electrode 47 is connected to the gate electrode by the contact hole 60. Next, the second substrate 42 will be described with reference to Fig. 3(B). The black moments and the color filter elements 62R, 62G, 62B of R, G, and B are provided at predetermined positions on the lower surface of the second 42 (the surface facing the first substrate 41). Here, when the color filter elements 62R, 62G, 62B are disposed to face the corresponding electrode 47 black matrix 61 and the south of the color filter elements 6 2R, 62G, 62B consisting of ITO, the pair is formed. To the electrode 63. The pixel capacitor portion is formed by the liquid crystal sealed between the electrode 47 and the counter electrode 63 disposed opposite thereto. In this case, since the surface of the pixel electrode 47 is the same, the pixel capacitance of the pixel capacitance portion is the same. Here, as shown in Fig. 2, among the auxiliary capacitance lines 48, the portion overlapping the electrode 47 becomes the storage capacitor 48a provided for each pixel. Then, the auxiliary portion 16 shown in Fig. 1 is formed by the portions thus overlapped. In other words, in the color liquid crystal device 1 shown in FIGS. 2 and 3, the storage capacitor 16 is formed as a storage capacitor electrode 48a as a part of the wiring on the mooring substrate 41; insulation provided thereon The films 52, 59; and a pixel electrode 47 composed of transparent electrodes provided on the insulating films 52, 59. On the other hand, since the pixel electrodes 47 corresponding to the respective color filter elements 62R, 62G, and 62B are provided on the cover film 59, they are partially poled. In the substrate array 61, the prime electrode, the prime electrode 43 is used to accumulate the phase pixel electrode, and the first wiring is placed on the same plane of -24-200926128. Therefore, the respective pixels of R, G, and B are The gap is shown in Figure 3(B)). The parallax connected to the pixel 15 of Fig. 1 is a switch 7 film transistor, at least one circuit of the scanning line driving circuit 20, the signal line driving capacitance line driving circuit 26, or all of the liquid crystals in Fig. 2 to Fig. 3 Display device 1. For example, 12 and each of the above-described driving circuits use a low-temperature polysilicon Λ 1 transparent substrate 41 to constitute a TFT array substrate. Here, ί is filled in the gap between the first substrate 41 and the second substrate 42. Further, in the color liquid 1' shown in Figs. 2 and 3, the auxiliary capacitor 16 is formed in accordance with the color by providing the electrode 48a and the insulating films 52, 59 and the pixel electrode 47 on the first substrate 41. In the pixel structure of the liquid crystal display device 1, the fourth diagram shows an equivalent diagram of a pixel structure of one row and three rows, Clc represents a pixel capacitance, and Ccs represents an additional character representation column of the auxiliary capacitor @component 1 2 . Line, the fuse line is represented by CS 1 . Now, by applying a moment to the signal line and the counter electrode and selecting the scanning line, it is connected to the scanning line (the pixel 15 of the GO becomes an ON state, and a voltage 13 according to the display signal is applied. That is, it is turned on. In the state, the auxiliary circuit 26 shown in FIG. 1 is applied to the other end of the auxiliary capacitor 16, that is, the auxiliary 17 is applied to the driving signal for the counter electrode in the first period of the driving signal for the counter electrode. After the first cycle, the size is d (the thin film 22 of the reference device 12 and the auxiliary circuit can be formed into a thin film transistor formed by the auxiliary capacitor of the crystal display device, but other structures can also be used. Block 1 6. The switch uses the auxiliary wave signal of the first column, and the switching element 1 2 drives the first voltage of the auxiliary capacitor electrode on the pixel electrode capacitance line. Ρ+1/2 weeks-25- 200926128 period (here, P is 0 or a natural number) A signal for applying a second voltage 'output to an open state in a holding period after p + 1/2 cycles. The scanning signal for each column is outputted at a predetermined timing to output the counter electrode. Use the drive signal. The absolute value of the potential difference between 13 and the counter electrode 14 is increased. Fig. 5 is a waveform showing an example of a driving method of the liquid crystal display device 1 of the present invention, and (A) shows a driving signal for the counter electrode, and (B) The drive signal for the auxiliary capacitance line, (C) indicates the drive signal for the signal line, (D) indicates the drive signal for the scanning line, and (E) indicates the voltage applied to the pixel 15 together with the voltage of the pixel electrode 13 ( The voltage difference between the pixel electrode 13 and the counter electrode 14 is as shown in Fig. 5(A), and the driving signal for the counter electrode corresponds to the pulse width of the scanning line driving signal, and the high level (VcomH) and the low level are repeated. The rectangular wave of the amplitude of the quasi (VcomL) is a waveform having an amplitude of a high level (VcomH) and a low level (VcomL), respectively, in t0^~tl and t5~t6 where the scanning line driving signal is ON. The waveform shown in Fig. 5(C) is an example of a signal for driving a signal line when the maximum voltage of the liquid crystal is applied. As shown in Fig. 5(D), the driving signal for the scanning line is a rectangular wave and has t0 to t1 and The period from t5 to t6 becomes the so-called high level during charging The amplitude, and the period from t1 to t5 and t6 to 110 are the amplitudes of the low level of the holding period. In the time period of t1 to t5, it should be noted that not several cycles shown in the figure, but hundreds of Similarly, the pulse wave of the counter electrode is in the time period of t5 to t6 in the period of t5 to t6, and -26-200926128 is intended to be an inverted signal of a time period of t1 to t2. In this case, in the drive signal for the counter electrode, the drive signal for the auxiliary capacitance line, and the drive signal for the signal line, t0 to t2 are referred to as the first cycle 'T2 to t4 2 cycles. In addition, one cycle of the scanning line driving signal is a period in which the switching element 12 is turned on (also referred to as a charging period) and a period in which the switching element 12 is turned off in a non-conducting state. composition. The drive signal for the auxiliary capacitor line will be described. As shown in the fifth diagram (B), the auxiliary capacitance line drive signal Vcs is the first voltage when the scanning line drive signal is in the charging period (the period t0 to t1), in other words, is applied to the counter electrode 14 The same voltage Vcsl (Vcs = VcomH) of the voltage VcomH is the same VcomL as the voltage applied to the counter electrode 14 at t1 to t2, and is applied to the opposite direction at the next t2 to t3. The second voltage (Vcs2) of the electrode 14 having a different voltage VcomH. At t3 to t5, the storage capacitor 16 is in a floating state by the auxiliary capacitance line drive circuit 26. In other words, 'the scanning lines are selected and connected to the scanning lines (the switching elements 12 of the pixels 15 of the GO are turned on, and when the voltage of the display signal is applied to the pixel electrodes 13, the auxiliary capacitance line driving circuit 26 is for each The auxiliary capacitor line ' applies a first voltage to the first period of the driving signal for the counter electrode. Then, in the half period (t2 to t3) after the period of the driving signal for the counter electrode (from t0 to t2), The auxiliary capacitance line drive circuit 26 applies the other second voltage synchronized with the half cycle to each of the storage capacitor lines, and outputs a signal as an open state during the hold period (t3-27-200926128 to t6) after the half cycle. The auxiliary capacitance line drive circuit 26 applies the above-described voltage signal to the auxiliary capacitance lines of the respective columns by the drive signal for the scanning lines of the respective columns. Thereby, the voltage difference generated by the pixel 15 is held until the next write operation. As such, Vcom and Vcs respectively applied to the auxiliary capacitance line 48 and the counter electrode 14 are rectangular waves of 50% duty between the pulse waves of the scanning signal. The selection/charging action is in the sweep The line signal Vg (t0~ tl) is performed at a high level. When the levels of Vcom and Vcs are charged during t2~t3, when returning to the low level, Vcs will change from a high level to a low level, which occurs greatly in the liquid crystal 43. After the voltage difference (after t3), the voltage Vcs of the auxiliary capacitor line 48 is in a floating state in order to maintain a large voltage difference between the liquid crystal and the pixel 15 of the pixel 15. In order to communicate in an alternating current (AC) mode. Drive pixel 15, the high level and low level of these signals will be reversed in the next frame. Therefore, in the next frame (refer to t5~tlO in Figure 5), the level of Vcs will be at t5~ In the period of tlO, the voltage is changed from VcomL to a high voltage. In addition, the period during which the second voltage is applied is not limited to the half period ', and may be a P + 1/2 period (here, p is 0 or a natural number). In the description, the period during which the second voltage is applied is described in a half cycle. As shown in the fifth (B) diagram, the drive signal for the auxiliary capacitance line is at t5 to t6, in other words, the drive signal for the scan line is during the charging period. The time 'is the same as the voltage applied to the counter electrode 14 The voltage VcomL is the first voltage Vcsl (Vcsl=VcomH) which is the same as the voltage applied to the counter electrode 14 at t6 to t7, and is applied to -28 - 200926128 at the time t7 to t8. The second voltage (Vcs2) of the counter electrode 14 having a different voltage (VcomL). At the other end of the auxiliary capacitor 16 at t8 to t10, in other words, the auxiliary capacitor line 48 including the auxiliary capacitor electrode 17 is made of an auxiliary capacitor. The line drive circuit 26 is in a floating state. The principle of operation of the driving method of the present invention will be described in more detail. The capacitance (Clc) between the counter electrode 14 and the pixel electrode 13 and the capacitance (Ccs) between the pixel electrode 13 and the storage capacitor electrode 17 are fixed irrespective of changes in the dielectric constant of the liquid crystal. Further, the capacitance (Ccs) between the pixel electrode 13 and the auxiliary capacitor electrode 17 is also fixed. When the potential of the pixel electrode 13 when the charging of the pixel 15 is completed is Vpix1, the potential of the counter electrode 14 during charging is VcomW, and when the potential of the auxiliary capacitor electrode 17 for charging is Vcsl, In the pixel electrode 13 (Pix), charging is performed with a charge indicated by Q = Clcx (Vpixl - VcomW) + Ccsx (Vpixl - Vcsl). Since the charging of the pixel 15 (for example, referring to t1 in Fig. 5) ends, the transistor 12 of the pixel 15 is turned off, so that the pixel 15 is in a floating state, and the Q is charged until the next charging. Keep it fixed. In the conventional example, the potential including the entire Vpix from this state is matched with the potential of the opposing electrode 14 and vibrates as in the first five-fifth diagram.

Here, when only the voltage of the storage capacitor electrode 17 changes from Vcs1 to Vcs2, since Q and Clc and Ccs are fixed, the potential relationship changes shortly after charging. When the changed pixel potential is taken as Vpix2, the relationship between Q = Clc X (Vpix 1 - VcomW) + Ccs x (Vpix 1 - Vcs 1 ) = Clc x (Vpix2-VcomW) + Ccsx (Vpix2-Vcs2) is established. Therefore, the potential Vpix of the pixel electrode changes only Vpix2-Vpixl = Ccs/(Clc + Ccs) X -29- 200926128 (Vcs2-Vcsl). Since the voltage applied to the liquid crystal is Vpix-Vcom, the voltage of the pixel 15 is boosted when Vpix2-Vpixl>0, that is, Vcs2-Vcsl>0 (refer to t7 to t8 of Fig. 5) to set Vcs2. . If it is Vcs2 < Vcsl (refer to t2 to t3 in Fig. 5), it will be stepped down. This is similar to the charge pump used for boosting inside the LSI, but the potential related aspect of the V c 〇 m is different. At the time of charging of the pixel 15, Vcsl (corresponding to Vcom) is applied to the auxiliary-auxiliary capacitor electrode 17, after one cycle (that is, when the potential of the counter electrode becomes the same potential as that at the time of charging) When t2~t3 (or t7~t8), grant Vcs2. In the other timings, the driving power supply of the storage capacitor electrode 17 causes the auxiliary capacitor electrode 17 to be in an open state, in other words, to have a high impedance, and to set the storage capacitor line to a floating state. By performing such driving, the boost state of the pixel voltage (Vpix) caused by the application of Vcs2 can be maintained during the sustain period. In other words, the potential of the pixel 15 can be boosted and exceed 4.8 V while using Vcs1 and Vcs2 in the voltage limit of the driver LSI. p Here, although the focus is on, the voltage of the auxiliary capacitor electrode 17 is made from

When Vcsl is changed to Vcs2, Vcom will have the same potential as when pixel 15 is charged. Vcsl and Vcs2 are voltages that can be supplied together from the driver LSI (the difference between Vs and Vs is 4.8V or less) can be realized in this timing. The P+1/2 period after the first cycle of the counter electrode driving signal (p is 0 or a natural number) indicates a period satisfying this condition. In the first embodiment, the circuit operation similar to the charge pump that pushes up the pixel potential is changed as the potential of the storage capacitor electrode 17 is changed. Therefore, the liquid crystal can be driven with a voltage equal to or higher than the output voltage of the LSI. -30- 200926128 Since the auxiliary capacitance line 48 is separated from the counter electrode wiring, the signal necessary for such a boosting operation can be freely applied. In the first embodiment, the storage capacitor electrode 17 is driven by the wiring from the driver LSI. However, the driving of the thin film transistor composed of amorphous germanium or polycrystalline silicon may be added adjacent to the display region. The circuit is used to drive. In this case, since the number of wirings around the thin film transistor 12 and the liquid crystal display portion 10 is reduced, the effect of the LSI can be obtained without increasing the number of wirings. In the first embodiment, the boosting of the storage capacitor 16 is performed by a voltage change applied to the storage capacitor electrode 17. When the configuration of the conventional pixel auxiliary capacitor is the same, even if other electrodes are added as the storage capacitor 16, the same effect can be obtained. Fig. 6, Fig. 7(A) and Fig. 7(B) show other embodiments of the present invention. Fig. 6 is a block diagram showing the case where the auxiliary capacitor 16 and the pixel auxiliary capacitor 18 are respectively provided, and the seventh (A) and (B)th drawings show the specific pixel structure ❹. As shown in Fig. 6, the auxiliary capacitor is composed of the first and second storage capacitors 16 and 18. In the case of this configuration, the first auxiliary capacitor 16 is simply referred to as a storage capacitor, and the second auxiliary capacitor is referred to as a pixel auxiliary capacitor 18. Since the auxiliary capacitor electrode 17 forming the other end of the auxiliary capacitor 16 is connected to the CS terminal, the electrode at the other end of the pixel auxiliary capacitor 18 is connected to the COM electrode (also connected to the counter electrode 14), so the auxiliary capacitor 16 is provided. The voltage is applied independently of the electrodes of the pixel auxiliary capacitor 18. In other words, the auxiliary capacitor 16 and one of the pixel auxiliary capacitors 18 are commonly connected to the pixel power -31 - 200926128. The pole 13' auxiliary capacitor 16 and the other end of the pixel auxiliary capacitor 18 are individually disposed. The other end of the auxiliary capacitor 16 is connected to the auxiliary capacitance line driving circuit 26 while the other end of the pixel auxiliary capacitor is connected to the opposite electrode 14. In other words, the pixel auxiliary capacitor 18 is connected in parallel with the pixel 15. In Fig. 7, (A) is a plan view of a pixel structure, and (B) is a cross-sectional view thereof. In this case, the auxiliary capacitor electrode 17 is formed at the other end of the auxiliary capacitor 16 disposed in each of the pixels 15, and the auxiliary capacitor electrodes 17 are connected to each other by the auxiliary capacitor line 48. The electrode wiring of the auxiliary capacitor 16 can be disposed in parallel with the electrode wiring of the pixel auxiliary capacitor 18. Therefore, there is an advantage that the degree of freedom in pattern layout is increased. Patterns for forming opposing electrodes such as the auxiliary capacitor 16 and the pixel auxiliary capacitor 18 are arbitrarily designed. Thereby, the storage capacitor for holding the charge accumulated in the pixel is sufficient, and the auxiliary capacitor 16 for raising the voltage (Vpp, the voltage between the peaks and turns) applied to the liquid crystal cell 15 can be formed. Fig. 8 is a block diagram showing a second embodiment of the liquid crystal display device 30 of the present invention. The storage capacitor line drive circuit 26 is configured to include first and second storage capacitor driving transistors 31 and 32 connected to each of the storage capacitors 16 driven by the respective scanning lines. The n pixel electrodes 13 connected to the scanning lines of the scanning line driving circuit 20 are connected to one end of the auxiliary capacitor 16, and the other end of the auxiliary capacitor 16 is formed as a common electrode. This common electrode is provided with only the number of portions of the scanning line driving circuit 20. The wiring composed of the common electrode of the auxiliary capacitor 16 is referred to as a storage capacitor line (Cs1 to Csm) 48. In other words, each of the storage capacitor lines -32 to 200926128 is driven in a state of being separated, and is driven by the first and second storage capacitor driving transistors 31 and 32 provided at both ends. As shown in the figure, the first auxiliary capacitor driving transistor 31 is referred to as CTril~CTn^ because m of scanning lines are arranged along the scanning line driving circuit 20. In the same manner, the second storage capacitor driving transistor 32 is referred to as CTr21 to CTr2m because m of the number of scanning lines are arranged along the n rows of the switching element 12. The pixel electrode 13 is connected to the drain of the transistor 12. The counter electrode 14 which forms the liquid crystal cell 15 together with the pixel electrode 13 corresponding to one column is connected to each other, and is connected to the second main electrode of the first storage capacitor driving transistor 31. The auxiliary capacitor electrodes 17 which form the storage capacitor 16 together with the pixel electrodes 13 of the first column are connected to each other and to the first main electrode of the first storage capacitor driving transistor 31. The respective control electrodes of the first storage capacitor driving transistor 31 are connected to the corresponding scanning lines. The pixels in the second column and the third column are also constructed in the same manner. Then, the counter electrode 14 for the pixel auxiliary capacitor 18 is all connected to the counter electrode wiring (referred to as COM1) which is the first common electrode. » As shown in the figure, the second auxiliary capacitor driving transistor 32 is second. The main electrodes are all connected to the second common electrode wiring (referred to as COM2). The pixels in the second column and the third column are also constructed in the same manner. In this way, the voltage of the counter electrode 14 as the other end electrode forming the pixel auxiliary capacitor 18 is constantly controlled to the voltage level of COM1. The voltage applied to the storage capacitor line 48 is controlled to the voltage level of COM2 by the switching states of the first storage capacitor driving transistor 31 and the second auxiliary capacitor driving transistor 32. -33- 200926128 In the first auxiliary capacitor driving transistor 31 of the i-th column, the first main electrode is connected to the auxiliary capacitance line 48 connected to the auxiliary capacitor 16 of the i-th column, and the second main electrode becomes the first 1 The counter electrode wiring (COM 1) of the common electrode is connected, and the control electrode is connected to the scanning line Gi of the i-th column. In the second storage capacitor driving transistor 32 of the i-th + 2 column, the first main electrode is connected to the first main electrode and the storage capacitor 16 of the first storage capacitor driving transistor 31 of the i-th column. In the auxiliary capacitance line 48, all of the second main electrodes are connected to the second common electrode wiring (COM2), and the control electrodes are connected to the scanning lines Gi + 2 of the i-th + 2 column. Therefore, when n pixels 15 (15u to 151n) in the first column are controlled, the first storage capacitor driving transistor CTru and the second storage capacitor driving transistor CTr23 are used. Similarly, when controlling each pixel 15 of the i-th column, the transistor CTru and the transistor CT rr (i + 2 > are used. Further, when n pixels 15 of the m-1th column are controlled, The first storage capacitor driving transistor CTrum.u and the second storage capacitor driving transistor CTr21 are used. When n pixels in the mth column are controlled, the first storage capacitor driving transistor CTnm and the second auxiliary capacitor are used. Driving transistor CTrn. The auxiliary capacitance line driving circuit 26 is connected to the first and second storage capacitor driving transistors 31 and 32 for each scanning line, and is connected to the second main electrode of the first auxiliary capacitor driving transistor 31. In the counter electrode wiring (COM1), the second main electrode of the second auxiliary capacitor driving transistor 32 is connected to the common electrode wiring (COM2). When the scanning line is G in the first column, the first auxiliary The control electrode of the capacitor driving transistor 31 is connected to the scanning line G of the first column, and the control electrode of the second auxiliary capacitor driving transistor 32 is connected to the scanning line Ch of the third column of -34-200926128. The common electrode wiring (COM2) applies an inverted voltage of the counter electrode wiring (COM 1). In this case, of course, the COM inversion signal generating circuit may be provided in the COM driver, but an inverter circuit composed of a thin film transistor (not shown) may be connected to the counter electrode driving circuit 24, and the inverter may be used. The output (COM2) of the circuit can be easily connected to the common electrode wiring. Fig. 9 is a schematic diagram showing an equivalent circuit diagram of one pixel 15. In Fig. 8, the scanning lines Gr G2 and G3 are sequentially selected. Gm. Choose

When the scanning line is D, the switching element 12 connected to the scanning line G» is turned on (via), and the liquid crystal and the auxiliary capacitor 16 of each pixel 15 are respectively charged to the connected signal lines 31, 32, 33~^ The potential of 〇1. In the selection/charging period at this time, the auxiliary capacitance line 48 corresponding to the scanning line applies a voltage (C0M1) to the counter electrode 14 by the first storage capacitor driving transistor CTru. At this time, the second storage capacitor driving transistor CTr23 connected to the storage capacitor 16 is in a state of being interrupted (disconnected) because the scanning line G3 is not selected. Therefore, Vcom2 does not affect the voltage of the auxiliary capacitor electrode 17 forming the auxiliary capacitor 16. The storage capacitor electrode 17 is driven only by the first storage capacitor driving transistor CTru. When the selection/charging period of the scanning line G! is completed and the non-selected state is completed, and the scanning line G2 is being selected, the first and second storage capacitor driving transistors CTru and CTr23 are disconnected because the gate is extremely low. Open state. Therefore, the storage capacitor electrode 17 and the pixel electrode 13 are in a floating state, and the charge charged at the time of selection of the scanning line G! is maintained, and the same potential (COM1) as that of the counter electrode 14 is maintained. Thereby, even if Vcoml - 35 - 200926128 changes, the voltage difference between the liquid crystal 15 and the storage capacitor 16 can be maintained in the same state. When the selection/charging period of the scanning line G: is completed and the non-selected state is reached, when the scanning line 〇3 is selected, the second storage capacitor driving transistor CTr23 is turned on. This is because the scanning line 〇}3 connected to the gate of the second storage capacitor driving transistor CTn3 is at a high level. Thereby, Vcom2, which is the voltage of the COM2 line, is applied to the auxiliary capacitance line 48 (Cs1) in one column by the second auxiliary capacitor driving transistor CTr23. The voltage (COM2) from the storage line driver circuit is applied to the storage capacitor electrode 17 via the second storage capacitor driving transistor CTm. At this time, the potential of COM2 is a potential different from that of COM1, and the potential of the auxiliary capacitor electrode 17 is changed from COM1 to COM2. Therefore, at this time, the voltage Vcom1 is supplied to the counter electrode 14 of the liquid crystal cell 15 in one column, and on the other hand, the supply voltage Vcom2 is supplied to the auxiliary capacitor line 48 (Cs1). This potential change spreads the potential difference between the pixel electrodes 13 and COM1 via the auxiliary capacitance line 48. That is, the liquid crystal application voltage is increased by an effect similar to that of the charge pump. As described above, after the selection of the scanning line G3 is completed, the period until the scanning line Gi is selected becomes the holding period, and the first and second storage capacitor driving transistors CTru and CTr23 are continuously turned off. That is, the charge charged by the writing of COM2 is held by the auxiliary capacitor 16, and this effect maintains the boost state of the pixel voltage on the scanning line G. The boosting system of the pixel 15 is maintained in a state where a potential difference from COM1 is generated. This is because the auxiliary capacitance lines 48 (C si, Cs2 to Csm) are in a floating state. Fig. 10 is a waveform of the wave-36-200926128 of the driving method of the liquid crystal display device 30 of the present invention, wherein (A) indicates a driving signal for the counter electrode, and (B) indicates a driving signal (Vcom2) for the second common electrode, (C) indicates a signal line drive signal, (D) indicates a drive signal of the scan line Gi, (E) indicates a drive signal of the scan line G2, (F) indicates a drive signal of the scan line G3, and (G) indicates application to the auxiliary. The auxiliary capacitance line drive signal of the capacitance line 48, (H) represents the voltage of the pixel electrode 13 of the pixel 15, and the voltage difference between the liquid crystal cell 15 generated between the pixel electrode 13 and the counter electrode 14. 0 As shown in Fig. 10(A), the drive signal (VcomL) for the counter electrode is a rectangular wave, and the drive signal (Vcom2) for the second common electrode is an inverted signal for the drive signal (Vcoml) for the counter electrode (refer to Figure 10(B)). As shown in Fig. 10(C), the driving signal for the number line is a rectangular wave in which the driving signal for the counter electrode is inverted. As shown in Figs. 10(D) to 10(F), the scanning line driving signal is a rectangular wave having a high level of amplitude during the selection/charging period. In the scanning line drive signal G1, t0 to t1 and t5 to t6 have amplitudes at which the charging becomes high, and all of the above-described ON periods are turned off, in other words, φ has a waveform having a low level. Similarly, in the scan line drive signal G2, t1 to t2 and t6 to t7 have amplitudes at which the charge is turned on, and all of the above-described turn-on periods are turned off, in other words, have a low level of amplitude. Waveform. In the scanning line drive signal G3, t2 to t3 and t7 to t8 have amplitudes of a high level at which charging is turned on, and all of the above-described ON periods are turned off, in other words, waveforms having a low level of amplitude. The period in which the lower level of the scanning line driving signal is set is referred to as "holding time". The 10th (G) diagram shows the waveform applied to the storage capacitor electrode 17, and -37-200926128 when the scanning line drive signal is turned on (t0 to t1), the first storage capacitor driving transistor 31 is turned on. Vcoml is applied to the auxiliary capacitor electrode 17 during this period. When the scanning line drive signal G3 is turned on (t2 to t3), the second auxiliary capacitor driving transistor 32 is turned on, during which Vcom2 is applied to the auxiliary capacitor electrode 17 disposed to face the pixel electrode 13. . In the case of t3 to t5 other than the above-mentioned period, since the first and second storage capacitor driving transistors 31 and 32 are not turned on, the storage capacitor electrode 17 is in a floating state. By setting such a drive signal, the potential (Vcs) of the storage capacitor electrode 17 is applied to the scanning line drive signal G applied to the first storage capacitor driving transistor 31, and to the second auxiliary capacitor driving power. The scanning line of the crystal 32 uses a waveform in which the signal center fluctuates up and down in each cycle of the driving signal G3. For the same reason as described above, the pixel potential can be boosted by this change. The 10th (H) figure and the pixel electrode 13 together represent the waveform of the voltage difference of the liquid crystal pixels 15. As shown in the figure, during the period from t2 to t3, the waveform of the pixel electrode 13 changes due to the influence of the voltage of the auxiliary capacitance line 48, and the voltage applied to the pixel 15 during the period from t3 to t5 is increased. Thereby, a boosting effect of increasing the absolute 値 of the potential difference between the pixel electrode 13 and the counter electrode 14 by using the auxiliary electric grid line driving circuit 26 can be obtained. In the storage capacitor line drive circuit 26 of the second embodiment, signals from the original scanning line are used as control signals for the first and second storage capacitor driving transistors 31 and 32. Similarly, the voltage (Vcom1) applied to the main electrode of the first storage capacitor driving transistor 31 can be supplied from the counter electrode driving circuit 24. Further, Vcom2 applied to the main electrode of the second auxiliary capacitor driving -38 - 200926128 transistor 32 is supplied with an inverted signal from the counter electrode driving circuit 24. Therefore, in the storage capacitor line drive circuit 26 of the second embodiment, it is easy to form a signal for the auxiliary capacitor drive. In addition, the internal and external wiring for the new specification of the auxiliary capacitor drive is not required, and the drive LSI or the liquid crystal display device which does not require the auxiliary capacitor drive terminal of the liquid crystal display device 30 to be newly installed in the liquid crystal display device 30 is generated. The beneficial effect of the 30 circuit. The waveforms of _Vcoml and Vcom2 and their 値 can have many variations and variants. In the second embodiment, the signal driven by the storage capacitor is used as the Vcom inversion signal, but the signal may be a DC voltage (VcomDC) corresponding to the amplitude center of Vcom. In this case, there is an effect that the supply of the signal (Vcom2) becomes easier. Of course, it is also possible to reduce the amplitude while maintaining the timing of the Vcom inversion and the center of the amplitude. The state where the amplitude becomes 0 is the minimum 値, which is VcomDC. Further, the amplitude of Vcom2 shown in Fig. 10 can be changed to be smaller than that shown in Fig. 10(B). With respect to Vcom2, as long as the voltage applied to the liquid crystal cell 15 is boosted, the voltage or period of Vcom2 can be deformed a lot. In the second embodiment, the pixel auxiliary capacitor (Cp) 18 may be different from the boosting auxiliary capacitor (Cs) 16 in the same manner as in the first embodiment. As shown in Fig. 6 and Fig. 7, other auxiliary capacitors may be provided in parallel with the pixel auxiliary capacitor 18 for forming a liquid crystal. This example is shown in the 11th chart. Fig. 11 is a block diagram showing the arrangement of the pixel auxiliary capacitor 18 and the auxiliary capacitor 16, and Fig. 12 is a diagram showing a specific pixel configuration -39-200926128. As shown in Fig. 11, one end of the pixel auxiliary capacitor 18 and the auxiliary capacitor 16 is commonly connected to the pixel electrode 13, and the other end of the pixel auxiliary capacitor 18 and the auxiliary capacitor electrode 17 at the other end of the auxiliary capacitor 16 are respectively They are individually arranged. In the illustrated case, the other end of the pixel auxiliary capacitor 18 is connected to the counter electrode 14, and the other end of the auxiliary capacitor 16 is connected to the auxiliary capacitance line drive circuit 26. In Fig. 12, (A) is a plan view of a pixel structure, and (B) is a cross-sectional view thereof. In this case, the auxiliary capacitance line 48 is formed at the other end of the auxiliary capacitor 16 of the pixels 15 arranged in each column. This auxiliary capacitance line 48 can be arranged in parallel with the pixel auxiliary capacitance line. Therefore, there is an advantage that the pattern design is increased in degree of freedom. As shown in Fig. 11 and Fig. 12, the auxiliary capacitance 16 associated with each pixel and the structure of the pixel auxiliary capacitor 18 are the same as those shown in Figs. 6 and 7. In the above example, the independently driven auxiliary capacitance line 48 is disposed in parallel with the capacitance line connected to the opposite electrode of the pixel capacitor. Therefore, there is an advantage that the degree of freedom is increased in addition to the pattern design. Since the pattern for forming the opposite electrode of the capacitor and the pattern of the capacitor line can be arbitrarily designed, the degree of freedom in pattern design can be achieved. This is the advantage. For example, patterns for forming the opposing electrodes of the auxiliary capacitor 16 and the pixel auxiliary capacitor 18 are arbitrarily designed. Thereby, the storage capacitor for holding the charge accumulated in the pixel 15 can be made sufficient, and the pixel electrode can be obtained in such a manner that the voltage applied to the liquid crystal cell 15 (the voltage between the Vpp and the peak 値) is increased. 13 is combined with the capacitance generated by the auxiliary electrode -40-200926128. Here, the auxiliary capacitance line drive circuit 26 can be disposed adjacent to the display portion 10. As shown in FIGS. 2 and 3, the auxiliary capacitance line drive circuit 26 can be formed on the first transparent substrate 41 using an amorphous germanium or a polysilicon as in the case of the switching element 12 adjacent to the pixel 15, and constitutes a TFT array. Substrate. In the embodiment of the liquid crystal display devices 1 and 30 described above, each of the auxiliary capacitance lines 48 intersects with the signal line 45.

P Fig. 13 is a schematic cross-sectional view showing the intersection of the signal line 45 and the auxiliary capacitance line 48 of the pixel shown in Fig. 2. Fig. 13 is a cross-sectional view taken along line A-A of Fig. 2, and since each auxiliary capacitance line '48 intersects the signal line 45, a parasitic capacitance Cst is formed at each intersection. Fig. 14 is an equivalent circuit diagram showing a parasitic capacitance Cst in the liquid crystal display device 30. As shown in Fig. 14, since the parasitic capacitance Cst is formed at the intersection of the auxiliary capacitance line 48 and the signal line 45, the auxiliary capacitance line 48 in the floating state & has a parasitic capacitance C (occurring at each intersection) Parasitic capacitance) The combined capacitance of the number η of signal lines. Therefore, the auxiliary capacitance line 48 is subjected to potential fluctuation due to the influence of the average potential of the signal line 45 by the combined capacitance Cn. The potential variation of the storage capacitor line 48 is caused by a change in the voltage of the pixel column connected to the storage capacitor line 48. Therefore, the signal line potential, that is, the image data, causes the pixel to be in the auxiliary capacitance line 48. The voltage is affected. Next, a modification of the pixel-41-200926128 which can block the parasitic capacitance generated at the intersection of the signal line 45 and the auxiliary capacitance line 48 in the liquid crystal display devices 1 and 30 will be described. Fig. 15 is a partial perspective plan view showing a configuration of a modification of a pixel, and Fig. 16 is a sectional view taken along line X-X of Fig. 15. As shown in Fig. 15, the pixel 70 is provided with a parasitic capacitance shielding line 72 for shielding the parasitic capacitance Cst generated between the signal line auxiliary capacitance lines 48. As shown in Fig. 15, the parasitic capacitance shielding wiring 72 has a straight portion 72a and a convex portion 72b. The parasitic capacitance shielding wiring 72 has a straight portion 7 2a which is disposed on the auxiliary electric wire 48 and the auxiliary capacitance electrode 48a side in the region between the auxiliary capacitance line 48 and the switching element 46, and is parallel and parallel to the auxiliary capacitance. Line 48; and protrusion 72 cover the intersection of auxiliary capacitance line 48 and signal line. The convex portion 72b is elongated so as to be vertically bent from the signal straight portion 72a toward the paper surface. Therefore, the parasitic capacitance shielding wiring is disposed so as to pass through the signal line 45 of each row and the intersection of the auxiliary capacitance lines 48 of the respective columns. Further, since the convex portion 7 2b is provided at the intersection of the signal line 45 and the auxiliary capacity line 48, it is also simply referred to as an intersection portion. As shown in Fig. 16, in the pixel 70, the gate insulating 52 formed on the first substrate 41 of the liquid crystal display device 1 shown in Figs. 2 and 3 is referred to as the first gate insulating film 74 and the first gate insulating film 74. In the two-layer structure in which the gate insulating film 75 is laminated, a pattern of the capacitance shielding line 72 is formed on the first gate insulating film 74. The auxiliary wiring 48 is formed on the first substrate 41 in the same manner as the liquid crystal display device 1. In the pixel 70, the auxiliary capacitance line 48 formed on the gate insulating film 52 of the liquid crystal device 1 shown in FIGS. 2 and 3 and the wiring pattern on the surface 45 of the wiring auxiliary capacitor 45 are sequentially formed. The capacitance number - 42 - 72 200926128 is formed on the second gate insulating film 75. The parasitic capacitance shielding wiring is formed in accordance with each of the storage capacitor lines Cs1 and Cs2 to Csm shown in Fig. 1 . Fig. 17 is a schematic cross-sectional view showing the capacitance generated at the intersection of the parasitic capacitance shielding wiring 72 and the signal line by the addition of the parasitic capacitance shielding wiring 72 of the pixel 70. As shown in the figure, the auxiliary capacitance line 48 and the storage capacitor shielding line 72 are opposed to each other with the first gate insulating film 74 interposed therebetween. Therefore, the first intersection portion is formed between the auxiliary capacitance line 48 and the parasitic capacitance shielding line 72. In addition, the parasitic capacitance shielding wiring 72 and the signal line 45 face each other with the second gate insulating film 75 interposed therebetween, so that the parasitic electric# shielding wiring 72 and the signal line 45 generate the second intersection portion 77» Therefore, between the auxiliary capacitance line 48 and the signal line 45, the first and second intersection portions 76 and 77 are formed together with the parasitic capacitance shielding wiring 72, but the auxiliary capacitance line 48 and the signal are not formed. The parasitic capacitance directly combined between the lines. The φ parasitic capacitance shielding wiring 72 is formed in accordance with each of the auxiliary electric wires Cs1 and Cs2 to Csm shown in Fig. 1, but is provided with a potential of all m. The common potential applied to the m parasitic capacitance shielding wires 72 can be a fixed potential such as GND. The material of the parasitic capacitance shielding 72 is preferably a low-resistance metal in order to prevent a voltage signal which is a common potential applied from being delayed. As explained above, in the pixel 70, the unfavorable parasitic capacitance generated between the auxiliary capacitance line and the signal line 45 is removed. Then, as explained above, the auxiliary capacitor line 48 in the floating state has been utilized (Cs (the resulting surface number is in the electric power 45 capacity common line 48: s2 -43-200926128 ~ Csm) Since the boosting effect is not affected by the potential fluctuation of the signal line 45 by the parasitic capacitance shielding wiring 72, the boosting state of the pixel 70 can be stabilized and maintained. The parasitic capacitance of the pixel 70 is shielded from the wiring 72. The potential is a fixed potential such as GND, but may be a voltage applied to the counter electrode 14 (COM 1). In this case, a capacitance is formed in a region where the parasitic capacitance shielding line 72 and the pixel electrode 47 overlap. In the same manner as the conventional auxiliary capacitor for the pixel, the effect of stabilizing the potential of the pixel 70 is obtained. 0 The pixel 70 can be produced by the following manufacturing method. The metal layer is deposited on the first substrate 41. The pattern of the gate electrode 51 and the auxiliary capacitance line 48 is formed by patterning. The metal layer can be made of a light-shielding chromium, a chromium alloy, aluminum, an aluminum alloy, molybdenum, or the like. Next, a gate electrode 51 is formed to cover the surface. The first gate insulating film 74 of a predetermined thickness is deposited on the entire surface of the first substrate 41 of the pattern of the auxiliary capacitance line 48. The first gate insulating film 74 is made of tantalum nitride and oxidized in the same manner as the gate insulating film 52. Next, a metal layer is deposited on the first gate insulating film 74, and a parasitic capacitance shielding wiring 7 is formed by patterning. The material of the parasitic capacitance shielding wiring 72 can be used as a gate electrode. 51. The same material as the metal layer of the auxiliary capacitance line 48. The second gate insulating film 75 of a predetermined thickness is deposited on the entire surface of the first gate insulating film 74 forming the pattern of the parasitic capacitance shielding line 72. The second gate insulating film Similarly to the gate insulating film 52, the film 75 may be made of an insulating material such as tantalum nitride or hafnium oxide, or may be the same material as the first insulating film 74-44-200926128. In the subsequent steps, if The manufacturing steps described in the liquid crystal display device 1 of Fig. 2 are the same. Next, other pixels 80 will be described in addition to the liquid crystal display devices 1 and 30. Fig. 18 shows the configuration of the pixel 80. Partial perspective plan, section 19 is a cross-sectional view taken along line XX of Fig. 18. As shown in the figure, in the pixel 80, the parasitic capacitance shielding wiring 82 is composed of a straight portion 82a which is provided on the first substrate 41. The contact portion is provided in parallel with the storage capacitor line 48, and the convex portion 82b is disposed in a region of the intersection of the storage capacitor line 48 and the signal line 45 on the second gate insulating film 75. The first gate insulating film 74 is provided. A contact hole 84 for exposing the parasitic capacitance shielding wiring 82 is disposed. The convex portion 82b of the parasitic capacitance shielding wiring is disposed on the second gate insulating film 75, and is connected to the parasitic capacitance shielding wiring line through the contact hole 84. Part 82a. Fig. 20 is a schematic cross-sectional view showing the capacitance generated in the intersection of the parasitic capacitance shielding wiring 82 of the pixel 80 and the signal line 45. As shown in the figure, since the auxiliary capacitance line 48 and the convex portion 82b of the parasitic capacitance shielding wiring face each other with the first gate insulating film 74 interposed therebetween, the auxiliary capacitance line 48 and the parasitic capacitance shielding wiring portion 82b are A first intersection capacitor 76 is generated. In addition, since the convex portion 8 2b of the parasitic capacitance shielding wiring and the signal line 45 face each other with the second gate insulating film 75 interposed therebetween, a difference occurs between the convex portion 72 of the parasitic capacitance shielding wiring and the signal line 45. 2 Intersection capacitor 77. Therefore, between the auxiliary capacitance line 48 and the signal line 45, the first and second intersections -45 - 200926128 fork capacitances 76, 77' are formed between the parasitic capacitance shielding wiring 82 and the same, but are not formed. A parasitic capacitance Cst directly coupled between the auxiliary capacitance line 48 and the signal line 45. The convex portion 82 of the parasitic capacitance shielding wiring is connected to the linear portion 82a' of the parasitic capacitance shielding wiring by the contact hole 84. Therefore, the parasitic capacitance is shielded between the auxiliary capacitance line 48 and the signal line 45 in the same manner as the pixel 70. In the eighteenth diagram, the contact hole 84 is formed on the overlapping portion between the signal line 45 and the parasitic capacitance shielding wiring 82. However, this is not a requirement, as long as the parasitic capacitance shielding wiring 82 is provided. It can be formed at any position. In the above-described embodiment, similarly to the parasitic capacitance shielding wiring 72 of the pixel 70, a fixed potential such as GND or a voltage applied to the counter electrode 14 (COM1) is applied to the parasitic capacitance shielding wiring 82 of the pixel 80. Therefore, since the influence of the potential fluctuation of the signal lines S:, S2, S3 to S» is eliminated by the provision of the parasitic capacitance shielding wiring 82, the boosting state of the pixel 80 can be stabilized and maintained. In the above-described embodiment, when the same potential as that of the counter electrode 14 is applied to the parasitic capacitance shielding wiring 82, the effect of adding the auxiliary capacitor for the conventional pixel is increased, and the stability of the potential of the pixel 80 is improved. The pixel 80 of the embodiment shown in Fig. 18 can be manufactured in the following manner. First, the same low-impedance conductive film is used on the first substrate 41 to form a pattern of the auxiliary capacitance line 48 and the linear portion 82a of the parasitic capacitance shielding wiring. Then, the first gate insulating film 74 is deposited to a predetermined thickness. A contact hole 84 is provided in the linear portion 82a of the parasitic capacitance shielding wiring. -46 - 200926128 Next, the convex portion 82b of the parasitic capacitance shielding field is deposited to a predetermined thickness, and a pattern connecting with the parasitic capacitance shielding wiring is formed. The material of the convex portion 82b of the parasitic capacitance shielding wiring may be electrostatically shielded. therefore. The projection of the parasitic capacitance shielding wiring does not require the use of a transparent conductive film of ITO or the like in which a low-impedance gold for preventing the delay of the voltage signal is used as the parasitic capacitance of the pixel 70 shown in Fig. 15. Thereby, the opening efficiency is further improved as compared with the above-described picture_pixel 80.

D Next, the second gate insulating film 75 is formed to have a predetermined thickness over the entire first gate insulating film 74. After this step, the manufacturing steps described in the display device of Fig. 2 may be performed in the same manner. Further, in the above-mentioned fifth, tenth, and twenty-fifthth drawings, it is noted that the parasitic capacitance generated between the gates and the gates of the transistor 12 is not explicitly described. However, as shown by Vpt in Fig. 26, it is self-evident that the small voltage drop generated by this parasitic capacitance should be considered in addition to the appropriate p-waveform. The present invention is not limited to the above-described embodiments, and various modifications can be made to the invention of the liquid crystal display device and the driving method thereof as described in the patent range, and these are of course included in the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing the configuration of a liquid crystal display device of the present invention. Fig. 2 is a view showing that the color electrode layer portion 82a of the first embodiment of the present invention can cover the wiring genus, and the liquid crystal that is deposited in the prime 70 is extremely limited, and the range in which the request is actually determined is It is a plan view of a part of the first substrate of the display device which is a square color liquid crystal-47-200926128. Fig. 3(A) is a cross-sectional view taken along line X-X of Fig. 2. Fig. 3(B) is a cross-sectional view showing the second substrate including the portion along the Y-Y line of Fig. 2; Fig. 4 is a block diagram showing an equivalent circuit of a pixel structure of one column and three rows. Fig. 5 is a waveform showing an example of a driving method of the liquid crystal display device 1 of the present invention, wherein (A) indicates a driving signal for the counter electrode, (B) indicates a driving signal for the auxiliary capacitance line, and (C) indicates a signal. The line drive signal, (D) represents the scan line drive signal, and (E) represents the voltage applied to the pixel (the voltage difference between the pixel 'electrode and the counter electrode) and the voltage of the pixel electrode. Figure 6 shows the @block diagram when the pixel auxiliary capacitor and the auxiliary capacitor are separately set. Fig. 7(A) is a plan view showing a pixel structure. The seventh (B) diagram shows a cross-sectional view of the pixel structure. Fig. 8 is a block diagram showing a second embodiment of the liquid crystal display device of the present invention. Fig. 9 is a schematic diagram showing an equivalent circuit diagram of one pixel. Fig. 10 is a waveform diagram showing a driving method of a liquid crystal display device of the present invention, wherein (A) indicates a driving signal for a counter electrode, (B) indicates a driving signal for a second common electrode (Vcom2), and (C) indicates a signal line. The driving signal, (D) indicates the driving signal of the scanning line G!, (E) indicates the driving signal of the scanning line G2, (F) indicates the driving signal of the scanning line G3, and (G) indicates the auxiliary capacitance applied to the auxiliary capacitance line. The line drive signal, (H) represents the voltage of the pixel electrode of the pixel, the voltage difference between the liquid crystal cell generated between the pixel electrode and the counter electrode. Fig. 11 is a block diagram showing the arrangement of the pixel auxiliary capacitor and the auxiliary capacitor, respectively. Fig. 12 is a view showing a specific pixel structure of Fig. 11, (A) a plan view of a pixel structure, and (B) a cross-sectional view. Fig. 13 is a schematic cross-sectional view showing the intersection of the signal line and the auxiliary capacitance line of the pixel shown in Fig. 2. Fig. 14 is an equivalent circuit diagram showing a parasitic capacitance Cst in a liquid crystal display device. Fig. 15 is a partial perspective plan view showing the constitution of a modification of the pixel. Fig. 16 is a sectional view taken along line X-X of Fig. 15. Fig. 17 is a schematic cross-sectional view showing the capacitance generated at the intersection of the parasitic capacitance shielding wiring and the signal line by the addition of the parasitic capacitance shielding wiring of the pixel. Figure 18 is a partial perspective plan view showing the composition of pixels. Figure 19 is a cross-sectional view taken along line X-X of Figure 18. Fig. 20 is a schematic cross-sectional view showing the capacitance generated in the intersection of the parasitic capacitance shielding wiring and the signal line of the pixel. Fig. 21 is a view schematically showing the structure of one pixel component of a conventional liquid crystal display device. Figure 22 is a diagram schematically showing the structure of a column of pixels. Fig. 23 is a view showing a waveform applied to a pixel. Fig. 24 is a block diagram of a liquid crystal display device disclosed in Patent Document 1 -49-200926128. Fig. 25 is a timing chart showing the operation of the liquid crystal display device of Patent Document 1, (A) showing the gate signal output from each scanning line, and (B) showing the auxiliary capacitance line driving voltage output from the auxiliary capacitance line driving circuit. Variety. Fig. 26 is a waveform diagram of voltages applied to respective pixels of the liquid crystal display device of Patent Document 1. [Main component symbol description]

1, 30 liquid crystal display device 10 display unit 12, 46 switching element (thin film transistor) 13, 47 pixel electrode 14, 63 counter electrode 15, 70, 80 pixel 16 auxiliary capacitor 17 auxiliary capacitor electrode 18 pixel auxiliary capacitor 20 scanning line driving circuit 22 signal line driving circuit 24 counter electrode driving circuit 26 auxiliary capacitance line driving circuit 3 1 first auxiliary capacitor driving transistor 32 second auxiliary capacitor driving transistor 4 1 first substrate 42 second substrate -50- 200926128

43 Liquid crystal 44 Scan line 45 Signal line 48 Auxiliary capacitor line 5 1 Gate electrode 52 Gate insulating film 53 Semiconductor film 54 Protective film 55 ' 56 Connect frmt Contact layer 57 Dip electrode 58 Source electrode 59 Cover film (planar film 60, 84 contact hole 6 1 inner matrix 62 color filter element 72 ' 82 parasitic capacitance shielding wiring 72a, 82a straight portion 72b ' 82b convex portion 74 first gate insulating film 75 second gate insulating film 76 first cross Capacitor 77 2nd intersection capacitance -51 -

Claims (1)

200926128 X. Patent application scope: 1. A liquid crystal display device comprising: a display portion 'its® consisting of: a scan line composed of a plurality of columns (here, the column is an arbitrary natural number of lSi$m); a signal line composed of a plurality of lines (where the 'row is an arbitrary natural number of lgjSn); a switching element disposed at an intersection of the scan line and the signal line; and a pixel electrode connected to the switching element Output terminal; opposite electrode; m column xn row pixel matrix 'which is formed by arranging liquid crystal cells between the pixel electrode and the opposite electrode; auxiliary capacitor 'one end connected to the output end of the switching element And a storage capacitor line 'which is composed of a plurality of columns connected to the switching elements of the above-described columns and having the other ends of the auxiliary capacitors of the respective columns common. a scanning line driving circuit that outputs, to the scanning lines of the respective columns, a driving signal for a scanning line having a switching period in which the switching element is turned on and a period in which the switching element is turned off; and a signal line driving circuit that is adjacent to each of the lines a signal line, an output signal line driving signal; a counter electrode driving circuit that outputs a driving signal for the counter electrode to the counter electrode; and an auxiliary capacitance line driving circuit that supplies auxiliary capacitance lines to the respective columns a capacitance line driving signal; and the auxiliary capacitance line driving circuit applies a first voltage to the auxiliary capacitance line in the first period of the counter electrode driving signal, after the first period of the counter electrode driving signal The second voltage is applied to the p+1/2 period (in '52-200926128, 'p is 0 or a natural number), and each scan of the above columns is matched during the hold period after the p+l/2 period The line outputs a signal that is set to an on state with a drive signal. 2. The liquid crystal display device of claim 1, wherein the auxiliary capacitance line drive circuit is composed of first and second drive transistors connected to each of the storage capacitor lines, and the first drive is used. The first main electrode of the transistor is connected to the other end of the auxiliary capacitor, and the second main electrode of the first driving transistor is connected to the counter electrode wiring (COM1) serving as the first common electrode, and the first driving is performed. The control electrode of the transistor is connected to the scanning line of the nest row (GO connection, the first main electrode of the second driving transistor is connected to the first main electrode of the first driving transistor, and the second driving transistor The second main electrode is connected to the second common electrode & wiring (COM2), and the control electrode of the second driving transistor is connected to the scanning line (Gi + 2) of the i + 2 column. The liquid crystal display device of the first or second aspect, wherein the auxiliary capacitor is composed of first and second auxiliary capacitors, and one of the first and second auxiliary capacitors is connected to the pixel electrode, and the first auxiliary The other end of the capacitor The auxiliary capacitance line driving circuit is connected to the auxiliary capacitance line driving circuit, and the other end of the second auxiliary capacitor is connected to the counter electrode. 4. The liquid crystal display device according to any one of claims 1 to 3 is -53-200926128 In the above, the first and second substrates are provided, the scanning lines and the signal lines are provided on the first substrate, and the counter electrode is provided on the second substrate. The liquid crystal display device of claim 4, wherein the auxiliary capacitor is composed of: a wiring provided on the first substrate; an insulating film provided on the wiring; and a wiring provided on the insulating film The liquid crystal display device of claim 1 or 2, wherein the auxiliary capacitance line driving circuit is disposed adjacent to the display portion, and the auxiliary capacitance line driving circuit is made of amorphous A thin film transistor composed of germanium or polycrystalline silicon. 7. A liquid crystal display device comprising: a display portion, which is composed of: a scan line, which is composed of a plurality of columns (here, the column is a signal line consisting of a plurality of lines (here, the line is any natural number of 1 $ j S η); a switching element, μ is disposed on the scan line; And a cross section of the signal line; a pixel electrode connected to the output end of the switching element; a counter electrode; a pixel matrix of mn rows of m columns, between the pixel electrode and the counter electrode a storage capacitor is formed; one end of the auxiliary capacitor is connected to the output end of the switching element; and the auxiliary capacitor line 'is connected by the switching elements of the respective columns and the other ends of the auxiliary capacitors of the respective columns become common plural a scanning line driving circuit that outputs a scanning signal for a line having a switching period in which the switching element is turned on and a period in which the switching element is turned on for the scanning line of each of the above columns; the signal line driving circuit a signal signal for each of the above rows, a driving signal for the output signal line; a counter electrode driving circuit for outputting a driving signal for the counter electrode to the counter electrode; and an auxiliary capacitor line driver a driving circuit that outputs a driving signal for the auxiliary capacitance line to the auxiliary capacitance line of each of the columns; and the auxiliary capacitance line driving circuit is composed of first and second driving transistors connected to each of the auxiliary capacitance lines The first main electrode of the first driving transistor is connected to the other end of the auxiliary capacitor, and the second main electrode of the first driving transistor is connected to the counter electrode wiring (COM1) serving as the first common electrode. The control electrode of the first driving transistor is connected to the scanning line (Gi) of the i-th column, and the first main electrode of the second driving transistor is connected to the first main electrode of the first driving transistor. The second main electrode of the second driving transistor is connected to the second common electrode wiring (C Ο Μ 2), and the control electrode of the second driving transistor and the scanning line of the i + 2 column (Gi + 2) The auxiliary capacitance line drive circuit is configured to apply a first voltage 'in the first period of the auxiliary capacitance line to the driving signal for the counter electrode to P+1/ after the first period of the driving signal for the counter electrode. 2 cycles (at -55- In the case where P is 0 or a natural number, the second voltage is applied, and in the holding period after the p+1/2 period, the signal for the ON state is output by the drive signal for each of the scanning lines in each of the above columns. . 8. The liquid crystal display device of claim 7, wherein the auxiliary capacitor is composed of a first and a second auxiliary capacitor, wherein one of the first and second auxiliary capacitors is connected to the pixel electrode, and the first The other end of the auxiliary capacitor is connected to the auxiliary capacitance line drive circuit, and the other end of the second auxiliary capacitor is connected to the counter electrode. 9. The liquid crystal display device of claim 7 or 8, wherein the display unit and the auxiliary capacitance line drive circuit include first and second substrates, and the scan lines and signal lines are provided in the first On the first substrate, the counter electrode is provided on the second substrate. 10. The liquid crystal display device of claim 9, wherein the auxiliary capacitor is composed of: a wiring provided on the first substrate; an insulating film provided on the wiring; and an insulating film disposed on the insulating film Transparent electrode on top. 11. The liquid crystal display device of claim 7, wherein the auxiliary capacitance line driving circuit is disposed adjacent to the display portion, and the auxiliary capacitance line driving circuit is a thin film transistor using amorphous germanium or polysilicon. Composed of. 12. A method of driving a liquid crystal display device, wherein the liquid crystal display device is provided with a scan line composed of a plurality of columns (here, the column is an arbitrary natural number of 1 S i S m ) and a plurality of rows (here, The line is a signal line composed of any natural number of lSjSn. At the intersection of the scan line and the signal line, a -56-200926128 switch element 'the pixel electrode and the pair connected to the output end of the switching element are provided. A pixel matrix of m columns xn rows composed of liquid crystal cells is disposed between the electrodes, and one end of the auxiliary capacitor is connected to an output end of the switching element. The driving method is to perform the above pixel by the following operation. Absolute increase in potential difference between the electrode and the counter electrode: a rectangular wave signal having the on-period and the off-hold period in which the switching element is turned on is applied as a scanning line driving signal of the switching element, a rectangular wave signal is applied to the signal line and the counter electrode, and a first voltage is applied to the other end of the auxiliary capacitor for the first period of the driving signal for the counter electrode The second voltage is applied to the p+1/2 cycle (here, p is 〇 or a natural number) after the first cycle of the drive signal for the counter electrode, and the hold period after the p+ 1 /2 cycle is set. It is a floating state. The method of driving a liquid crystal display device according to claim 12, wherein the first voltage is the same voltage as the counter electrode, and the second voltage is different from the counter electrode. Voltage. 14. The method of driving a liquid crystal display device according to claim 12, wherein the first voltage is the same voltage as the counter electrode, and the second voltage is inverted from the counter electrode. The same voltage voltage. 15. The method of driving a liquid crystal display device according to claim 14, wherein the scan line (Gi + 2) of the second column -57-200926128 before the scan line (Gi) to which the switching element is connected is connected. The second voltage is applied synchronously during the turn-on period. 16. The method of driving a liquid crystal display device according to claim 13 or claim 14, wherein the voltage applied to the auxiliary capacitor is a voltage for reducing a signal amplitude applied to the counter electrode wiring. 17. The driving method of a liquid crystal display device according to claim 13 or claim 14, wherein the voltage applied to the auxiliary capacitor is a DC voltage corresponding to a center of a signal amplitude applied to the counter electrode wiring. A liquid crystal display device comprising: a display portion, which is composed of a scan line composed of a plurality of columns (here, the column is an arbitrary natural number of 1 S i S m ); a signal line, It consists of a plurality of rows (here, the row is any natural number of 1 S j S η); a switching element, which is disposed at the intersection of the scan line and the signal line; and a pixel electrode connected to the switch An output terminal of the component; a counter electrode; a pixel matrix of mn rows of m columns, wherein a liquid crystal cell is disposed between the pixel electrode and the counter electrode; and an auxiliary capacitor having one end connected to the output of the switching element And a storage capacitor line, which is composed of a plurality of columns connected to the switching elements of the respective columns and having the other ends of the auxiliary capacitors of the respective columns become common; and a parasitic capacitance shielding wiring which is disposed through the respective rows a signal line and an intersection of the auxiliary capacitance lines of the respective columns; and a scanning line driving circuit that outputs a scanning line drive having a switching period in which the switching element is turned on and a period in which the switching element is turned off for the scanning lines of the respective columns a signal line driving circuit for outputting signal lines for the signal lines of the respective rows; -58-200926128 a counter electrode driving circuit for outputting a driving signal for the counter electrode to the counter electrode; and an auxiliary capacitor a line driving circuit that outputs a driving signal for the auxiliary capacitance line to the auxiliary capacitance lines of the respective columns; and the auxiliary capacitance line driving circuit is connected to the first and second driving transistors connected to each of the auxiliary capacitance lines In the composition, the first main electrode of the first driving transistor is connected to the other end of the auxiliary capacitor, and the second main electrode of the first driving transistor is connected to the counter electrode wiring (COM1) serving as the first common electrode. The control electrode of the first driving transistor is connected to the scanning line (Gi) of the first driving transistor, and the first main electrode of the second driving transistor is connected to the first main electrode of the first driving transistor. The second main electrode of the second driving transistor is connected to the second common electrode wiring (COM2), and the control electrode of the second driving transistor and the scanning line of the i + + column ( Gi + Ο connection, the auxiliary capacitance line drive circuit applies a first voltage to the auxiliary capacitance line in the first period of the driving signal for the counter electrode, and P after the first period of the driving signal for the counter electrode The second voltage is applied to the +1/2 cycle (here, P is 0 or a natural number), and in each of the sustain periods of the P + 1/2 period, the output signals for each of the scanning lines are outputted. The liquid crystal display device of claim 18, wherein the auxiliary capacitor is composed of first and second auxiliary capacitors, and the first and second auxiliary capacitors are provided. One end is connected to the pixel electrode, the other end of the first auxiliary capacitor is connected to the auxiliary capacitance line driving circuit, and the other end of the second auxiliary capacitor is connected to the opposite electrode. 20. The liquid crystal display device of claim 18, wherein a direct current voltage is applied to the parasitic capacitance shielding wiring. 21. The liquid crystal display device of claim 18, wherein the driving signal for the counter electrode is applied to the parasitic capacitance shielding wiring. [22] The liquid crystal display device of claim 18, wherein the display unit and the auxiliary capacitance line drive circuit comprise first and second substrates, and the scan lines and signal lines are provided on the first substrate. The counter electrode is provided on the second substrate. 23. The liquid crystal display device of claim 22, wherein the auxiliary capacitor is composed of: a wiring provided on the first substrate; an insulating film provided on the wiring; and an insulating film disposed on the insulating film Transparent electrode on top. [24] The liquid crystal display device of claim 18, wherein the auxiliary capacitance line driving circuit is disposed adjacent to the display portion, and the auxiliary capacitance line driving circuit is a film using amorphous germanium or polycrystalline sand. The crystal is composed of. The liquid crystal display device of claim 18, wherein the parasitic capacitance shielding wiring is disposed between the switching element and the auxiliary capacitance, and is disposed in parallel with the auxiliary capacitance line. The liquid crystal display device of claim 22, wherein the first gate insulating film and the second gate insulating film are disposed on the first substrate, and the parasitic capacitance shielding wiring is matched. It is provided on the first gate insulating film. [27] The liquid crystal display device of claim 22, wherein a linear portion of the parasitic capacitance shielding wiring is disposed on the first substrate, and an intersection of the parasitic capacitance shielding wiring is disposed in the first gate The intersection portion and the linear portion are connected by a contact hole disposed in the second gate insulating film. The liquid crystal display device of claim 27, wherein the intersection of the parasitic capacitance shielding wiring is composed of a transparent electrode material. -61-