TW573291B - Active matrix type display device - Google Patents

Description

573291 V. Description of the invention (1) One by one [...] [Technical field to which the technology belongs] The present invention relates to ~ dynamic matrix display devices. [Prior technology] In a kind of thin matrix transistor (TFT: Thi-n Fi lm st0rj) switching elements, respectively, to the independent pixel electrode to supply a k-number of dynamic matrix image ^ ιέ ώ # + # j- ^ a In the AC potential application device for the auxiliary capacitor, the AC drive method of the counter electrode and the hair trimming position is used to prevent the liquid crystal from deteriorating, and L & Η 2 2 to 'and the pole drive (drain driVer) of the video signal between the positive and negative polarities you 萁, nu ^ to achieve low power consumption. "Reducing the current and voltage of the drain driver 'No. pole: :: video will be supplied to each drain line during the period Letter period gate connection; 5 中 Inverted counter electrode ac drive, because in each horizontal electrode and full auxiliary ϊ ^ capacitor 'line voltage polarity, and the opposite is cited: power consumption is still a large J load And from the polarity reversal 1 2-8 1 60 No. 6 is now reduced in power consumption, in Japanese JP Kaiping ’s counter electrode voltage problem, the polarity of the voltage is reversed, which can reduce 时 ΐϋ ^ house 'And can reduce the current consumption of the actuator and the potential difference = = =' and reduce the electrodeless display device. Left foot will be described using the dynamic matrix type liquid SC driver of the panel significantly Shi t ':. Ϊ: c] drive: ± 3 matrix type liquid crystal display apparatus α μ I of the road section with a plurality of drain lines 5 to 1 vertical square

$ 5 pages 314297.ptd 573291 V. Explanation (2) Straight direction configuration 'A plurality of gate lines 107 are arranged in the horizontal-horizontal direction, and a TFT1 〇9 as a switching element is placed at the intersection. The gate of the TFT1 〇9 is fast connected to the gate line 107, and the drain is connected to the drain line} 〇5-it is connected to the single-sided electrode of the liquid crystal cell Π2. The only side electrode of the liquid crystal cell * 112 is the counter electrode 1 1 1, which is integrally provided on the opposite side substrate that sandwiches the liquid crystal together with the substrate on which the TFT 1 09 is provided. "In addition, the auxiliary electrode of the TFT 109 is connected to the auxiliary capacitor." The electrode on the other side of the auxiliary capacitor i is connected to the auxiliary capacitor line i 08. The auxiliary capacitor line 108 is arranged in parallel with the gate line 107, and is in common with the column_a plurality of auxiliary capacitors 11o. Figure 12 shows the signals and waveforms of the driving display panel focusing on one pixel. The gate voltage V g, day voltage V p, source voltage 'f V s, and video are shown in the figure. The signal voltage V d, the auxiliary capacitor voltage v # and the counter electrode voltage VCC) M. The gate voltage V will have a turn-on period between a frame and a frame. During the -gate ON period, the gate voltage applied to the question line 107 is at a high level (hereinafter referred to as "High"). During this period, TFT1109 is g '(ON), and there is conduction between the source and the source, and the source voltage vs will follow the video signal voltage V 両 applied to < 1 line 105 Level. In addition, the f zero voltage V is applied to the electrode of one of the liquid crystal capacitor i 丨 2 and the auxiliary capacitor 丨 10. As soon as the gate's 0FF period is reached, the gate voltage Vg will change to a low level (hereinafter referred to as “Low” —) level, and the TFT1 09 is turned off (non-conducting): while the source 1 voltage V is determined, As the gate house V drops approximately, the level is only low △ Vfn becomes VPL. 1 cow

314297.ptd Page 6 573291 V. Description of the invention (3) The counter electrode voltage VCD is a certain voltage, which is located at a level V higher than the center of the video_signal voltage VD, which is only lower than the previously reduced source voltage V type △ V Standard. For each auxiliary capacitor line 108, after the gate voltage V G applied to the corresponding gate line 107 decreases, the auxiliary capacitor voltage V sc whose level is reversed is applied. The auxiliary capacitor voltage V sc is reversed at two levels, V% to V SCL. For example, during the positive polarity of the source voltage V and the counter electrode voltage V CGN, after the gate voltage V G decreases, the voltage V sa rises from the low level V sa to the high level V SCH. Therefore, the gate voltage V G decreases, and the source voltage V s-once determined, the pixel voltage V p will be affected by the increase in the auxiliary capacitor voltage V% through the auxiliary capacitor 110, and only increase by △ VP. At this time, the pixel voltage VP will be maintained during the gate OFF period, that is, one frame. In this way, as the auxiliary capacitor voltage V s increases, a charge redistribution occurs between the liquid crystal capacitor 11 2 and the auxiliary capacitor 110, and the pixel voltage V pK increases ΔV VV — V PL. During the period when the source voltage V resists the negative polarity of the counter electrode voltage VCD, on the contrary, since the auxiliary capacitor voltage V sc decreases from the positive side to the negative side, the pixel voltage V P will only decrease by 厶 V P. As a result, the amplitude of the pixel voltage V P is increased, and the voltage applied to the liquid crystal capacitor 112 can be increased. In other words, by setting the auxiliary capacitor voltage V s to two levels, even if the counter electrode voltage V is a DC voltage, the video signal voltage V can be reduced in amplitude, and a sufficient voltage can be applied to the liquid crystal capacitor 1 12. _ In general, since the auxiliary capacitor 110 will be much larger than the liquid crystal capacitor 112, the variation of the auxiliary capacitor voltage V (V se "V sc0) in one column can control the change part of the daytime voltage △ VP. Therefore To make the auxiliary electricity of auxiliary capacitor line 108

314297.ptd Page 7 573291 V.-Explanation of the invention (4) If the capacitance voltage changes, a larger voltage can be applied to the liquid crystal capacitor 11 2. In other words, by changing the auxiliary capacitor voltage, the video 〃 signal voltage V 妁 amplitude can be reduced. _-However, at present, the following driving methods are generally used, that is, with the increase of the power of the day, at the same time, a plurality of "polar lines 1 05" are turned on, and the plurality of liquid crystal capacitors 1 1 2 and The auxiliary capacitor 110 simultaneously applies a video signal voltage V-type driving method. In this way, it is possible to sufficiently ensure that the drain line 105 applies the video signal voltage V & time to the liquid crystal capacitor 11 2 and the auxiliary capacitor 1 110. In particular, When sequentially driving a dot-nine or high-definition display panel, the tens of drain lines 105 are turned on at the same time, and the video signals are simultaneously applied to dozens of liquid crystal capacitors 11 2 and auxiliary capacitors 1 1 0. Voltage VD. In this way, when dozens of drain lines 105 are turned on at the same time, the overlapped portion of drain lines 105 and auxiliary capacitor lines 108 that are already on-state is on. A large capacitance combination occurs during this. Through this capacitance combination, the voltage of the auxiliary capacitor line 108 or the gate line 107 is affected by the voltage of the drain line 105, and changes. _ Subject to this voltage change, Will cause the drain line 1 0 5 which is on at the same time to produce day image in-unit [Inventive content]-· In the present invention, voltages with different polarities can be applied to the adjacent singular or plural ones, which can be called dot inversion. The present invention has The rows of the element electrodes correspond to each other, and a plurality of first and second auxiliary electric capacity lines are extended in the horizontal direction, and the rows of the above-mentioned day electric power 1 are arranged in correspondence with the first and second auxiliary capacitor lines Auxiliary capacitor / In this way, signals with different polarities can be supplied to each auxiliary capacitor line.

314297.ptd Page 8 573291 V. Description of the invention (5) Therefore, using the first and second auxiliary capacitor lines, voltages of different polarities can be applied to each adjacent day element, which is to achieve the so-called point inversion drive. Further, it is preferable that the first and second auxiliary capacitor lines are supplied with the first and second auxiliary capacitor voltages that change in opposite phases from each other while the switching element is in the off state. In this way, while realizing the dot inversion driving caused by the aforementioned auxiliary capacitor line, the amplitude of the video signal voltage can be reduced, and a sufficient voltage π can be applied to the pixel electrode. [Embodiment] The first embodiment will be described. Fig. 1 is a plan view of a display panel of a dynamic matrix display device, Fig. 2 is a plan view of a display panel of the first embodiment, and Fig. 3 is a temple effect circuit diagram of a display panel. First, in FIG. 1, on the display panel 1, a drain driver 2 (draindri ν er) 2 is arranged in a horizontal direction as a horizontal driver (r 〇w driver), and is arranged in a vertical direction as a vertical driver (co 1 umndriver) gate driver (gatedriver) 3. In a region surrounded by the drain driver 2 and the gate driver 3, a display region 4 for displaying images is arranged. [Note: In Japanese, '' row π is r 〇 w (column), π column '' is c ο 1 u mη, in the translation of this article, according to Chinese convention, r 〇 w is a column, and c ο 1 u m η is a row. In the display area 4, as shown in FIG. 2 and FIG. 3, a plurality of drain lines 5 which are data lines and a plurality of straight rectangular pixel electrodes 6 are arranged in the vertical direction in the horizontal direction. In the direction, a gate line 7 as a selection line, and a first auxiliary capacitor line 8a and a second auxiliary capacitor line 8b are provided. A TFT 9 and either the first auxiliary capacitor line 10a or the second auxiliary capacitor line 10b are arranged in a region where each pixel electrode 6 is disposed (hereinafter referred to as a "pixel region").

314297.Ptd page 9 573291 V.-Description of invention (6). -TFT.9 is formed by the gate electrode 9g extending from the gate line 7, the channel region of the "semiconductor layer" below, and the semiconductor layer electrically connected to the contacts through the drain line 5 • The electrode region 9 d, the semiconductor region that is electrically connected to the contacts through the day element electrode 6 and the source region 9 s of the layer. In this example, the TFT 9 is provided with two gate electrodes 9 g The first auxiliary capacitor 10a is an auxiliary capacitor electrode 10x formed by a semiconductor layer connected to the TFT9, and an auxiliary capacitor electrode 100y extended and formed from the first auxiliary capacitor line 8a. The second auxiliary capacitor 1 Ob is formed by the auxiliary auxiliary electrode 1 Ox and the trap capacitor electrode 10 z formed from the second auxiliary capacitor line 8 b. —… ▲ In addition, the substrate on which the TFT 9 is provided and A counter electrode 1 1 ′ is provided on the Hunan-side substrate sandwiching the liquid crystal to constitute a capacitor electrode on the opposite side corresponding to the day electrode 6 of the liquid crystal capacitor 12. In this embodiment, the TFT 9 is used as the -N channel. For the sake of TFT, the material line is referred to as "> and the polar line" and the driver is called "> and the polar driver I s. No, TFT9 can also be composed of P-channel TFT. · As shown in Figure 1, the input to the drain driver 2 has the first video signal voltage VDa and the second video signal voltage VDb of opposite polarity. Sequence selection No. # 5 applies either the first video signal voltage VDa or the second video it Μ f: presses VDb. ~ · The gate driver 3 sequentially selects the gate line 7 to apply the gate signal GV. Display Area 4 is an area in which a plurality of day element electrodes 6 are arranged in a determinant type, and a force_voltage is applied between the day element electrodes 6 and the counter electrode 11 to perform image display.

314297.pld Page 10 573291 V. Description of Invention (7) Domain. The drain line 5 refers to a voltage applied to either the first video signal voltage VDa or the second video signal voltage VDb having opposite polarities, and the video signal voltage VDa or VDb is transmitted to the drain of the TFT 9 through a contact. Wiring. The day element electrode 6 constitutes a day element region of a display unit, and together with the counter electrode 11, the electrode of the liquid crystal is driven by the video signal voltage VD transmitted from the drain line 5 through the TFT 9. The gate line 7 is selected by the gate driver 3, and a gate signal GV is applied, and the connected TFT 9 is turned ON by the applied voltage. The first auxiliary capacitor line 8a is formed on the same layer as the gate line 7, and is arranged in parallel with the gate line. The first storage capacitor line 8a has a plurality of storage capacitor electrodes 1 0 y which are integrally formed in the horizontal direction. Therefore, the auxiliary capacitor electrodes 1 0 y of the first auxiliary capacitors 10 a in each row are connected to each other. The second auxiliary capacitor line 8 b is formed on the same layer as the gate line 7, and is also arranged in parallel with the gate line 7. The second storage capacitor line 8b has a plurality of storage capacitor electrodes 10 z integrally formed in a row direction. Therefore, the storage capacitor electrodes 1 0 z of the second storage capacitors 10 b in each row are connected to each other. A first auxiliary capacitor voltage is supplied to the first auxiliary capacitor line 8a, and a second auxiliary capacitor voltage having an opposite polarity to the first auxiliary capacitor voltage is supplied to the second auxiliary capacitor line 8b. TFT9 is a switching element. Only when a voltage is applied to the gate electrode 9 g, the current will flow from the source region 9 s to the direction of the electrode region 9 d or from the drain region 9 d to the source region. In any direction of the direction of 9 s, the semiconductor layer channel region directly below the gate 9 g flows. 1st

314297.ptd Page 11 573291 V.-Description of the invention (8) Electric power valley 1 0 a and the second auxiliary capacitor 1 0 b combined with the video signal supplied by TFT 9 through the TFT 9 ^ frame from the drain Compensate for the loss of charge of the liquid crystal capacitor 12. The X-shaped spoon contains a voltage that corresponds to the video signal voltage VD applied to the counter electrode 11 with a certain lightning segment pole 6. The electric factor =: the charge held by the liquid crystal cell 12 and the counter electrode 11 , Is the electricity% caused by the video signal voltage VD supplied from the & line 5 through the TFT9. No, in contrast to the charge held by 帛 1 auxiliary capacitor 10a or the second auxiliary capacitor 10b, the electric charge held by the liquid crystal capacitor 12 is very small. Therefore, τρτ9 = leakage current or Leakage from impurities in the liquid crystal easily flows out. Therefore, the held charges of the liquid crystal capacitor 12 are supplemented by the charges · held by the first storage capacitor 10a and the second storage capacitor 10b. Next, the driving method will be explained. Fig. 4 is a timing chart showing the relationship between various signals in the display panel. In the figure, it is shown that: the vertical start signal STV and the gate signals GV1, GV2, GV3; the horizontal start signal STH and the horizontal day can pulse ## CKH, the potential SCa of the first auxiliary capacitor line 8a and the second auxiliary The timing of the voltage change of the potential SCb of the S capacitance line 8b. First, corresponding to the fall of the vertical start signal STV pulse, the pulse of the gate signal GV1 rises, and the gate signal GV1 is supplied to the gate line 7 of the i-th column, so that the gate signal GV1 is connected to the gate line 7 The TFT9 is turned on. · Then, the pulse of the horizontal start signal STH rises, and the pulse of the first horizontal clock signal CKH in the period selected by the gate line 7 in the first column will decrease with the pulse ^ Π ·· 3Μ297.ptd page 12 573291 V. Description of the invention (9) Rise synchronously. While the gate signal GV 1 is being supplied to the gate line 7 in the first column, the pulses of the horizontal clock signal CKH will rise in sequence, and the drain line 5 will be selected in sequence in synchronization with the rise of the pulse, and the video signal voltage VD Then, the pixel electrode 6 and the first auxiliary capacitor 10a and the second auxiliary capacitor 10b are sequentially applied through the TFT9. Further, the first video signal voltage Vda is applied to the day element electrode 6 and the first auxiliary capacitor 1 Oa, and the second video signal voltage VDb is applied to the day element electrode 6 and the second auxiliary capacitor 1 Ob. After the video signal voltage VD is applied to all the drain lines 5, the gate signal GV 1 to the gate line 7 in the first column are no longer supplied, so that the TFT 9 connected to the gate line 7 is turned off. . Next, the pulses of the gate signal GV2 and the gate signal GV 3 rise in order, and the gate signal GV2 is applied to the gate line 7 in the second column, respectively, and the gate signal 7 is applied to the gate line 7 in the third column. The GV3 method repeats the above actions. The TFT 9 connected to the gate line 7 is in a cut-off state, that is, while the gate signal GV is not being supplied to the gate line 7, the potential SCa and the second auxiliary capacitor of the first auxiliary capacitor line 8a in the row The polarity of the potential SCb of the line 8b is reversed. Here, the polarities of the auxiliary capacitor voltages VCa and VCb of the first auxiliary capacitor line 8a and the second auxiliary capacitor line 8b are opposite polarities at the beginning. Due to the level reversal, the video applied to the pixel at that time The signal voltages will have the same polarity, and then they will be set to maintain this state. The level inversion is performed immediately after the TFT9 is turned off. Therefore, after the first or second video signal voltage is applied to any one of the auxiliary capacitors 1 Oa or 1 Ob, the TFT9 is in the off state, causing the The potential difference between the counter electrodes 11 of the pole voltage V s is

314297.pid Page 13 573291 V. Description of the Invention (ίο) will become small for a time. However, by applying the first or second auxiliary capacitor voltage, the potential difference between the counter electrode 11 and the counter electrode 11 will increase. 'Next, after the gate signal GV is supplied to all the gate lines 7, the pulse of the vertical start-start signal STV rises again, and the gate-line " 7 of the first column is supplied with the gate signal GV in synchronization with the pulse, And repeat the same action. Fig. 5 is a signal waveform diagram showing a driving method of the display device according to the first embodiment of the present invention, and shows a signal waveform between one frame in a daylight region adjacent to the gate line direction. Figure 5 (a) shows the signal waveform of the first auxiliary capacitor 10a, and Figure 5 (b) shows the signal waveform of the second auxiliary capacitor 10b. ·: A) The signal waveform shown in Figure 12 is roughly the same as that shown in Figure 12; however, the signal waveform shown in Figure 5 (b) is exactly the reverse of the polarity of Figure 12. • As shown in Figure 1, the first auxiliary capacitor 10a and the second auxiliary capacitor 1 Ob are arranged horizontally on adjacent daylight elements. Therefore, in adjacent pixels, the video signal voltages VDa and VDb of opposite polarity are applied, and the first storage capacitor 10a of the pixel to which the video signal voltage VDa has been applied is a storage capacitor of the same polarity as the video signal voltage VDa. Voltage VCa. On the second auxiliary capacitor 1 Ob to which the video-bit voltage VDb has been applied, the auxiliary capacitor voltage VCb of the same polarity as the video signal voltage VDb is applied, and the auxiliary capacitor voltage VCa is performed while the TFT 9 is turned off. The polarity of VCb is reversed. Therefore, P is cut off from the TFT9, so the source voltage Vs of the TFT9 is reduced by only ΔVs. However, the change in the voltage of the daytime electrode due to the inversion of the auxiliary capacitor voltage V C ΔV P will promote the voltage between the electrodes of the liquid crystal capacitor 12 to increase, and the liquid crystal can be driven at a sufficient voltage. In this way, in the dynamic matrix display device of this embodiment,

314297.ptd Page 14 573291 V. Description of the invention (11) Any one of the auxiliary capacitor 10a or the auxiliary capacitor 10b arranged in each day element region forming the day element electrode 6. One side of the plurality of auxiliary capacitors 10a and 10b arranged in the row direction is connected to the source of the daytime TFT 9 respectively. In the other direction, the electrodes on the other side of the auxiliary capacitors 10 a arranged in the horizontal direction are connected to the first auxiliary capacitor line 8 a. In addition, the electrode system on the other side of the auxiliary capacitors 1 0 b arranged in the horizontal direction is connected to the second auxiliary capacitor line 8 b. In addition, during each frame period, the drain line 5 is supplied with a video signal voltage which reverses the polarity. The video signal voltage includes a first video signal voltage and a second video signal voltage of opposite polarities. The first video signal voltage and the second video signal voltage are applied to adjacent drain lines 5, respectively. Next, the TFT 9 is turned on by the first video signal voltage, and when the t-th auxiliary capacitor 10 a is charged, the polarity of the first auxiliary capacitor voltage VCa applied to the first auxiliary capacitor line 8 a of the pixel is reversed. And the same polarity as the first video signal voltage. In addition, when the TFT 9 is turned on by the second video signal voltage, when the second storage capacitor 1 Ob is charged, the polarity of the second storage capacitor voltage VCb applied to the second storage capacitor line 8b of the day element is reversed, and The same polarity as that of the second video signal voltage. · In this way, by using the auxiliary capacitor lines 8 a and 8 b, the so-called dot reverse driving can be realized. Next, in the dynamic matrix display device, while the TFT 9 is on, the first auxiliary capacitor 8a connected to the first auxiliary capacitor line 8a is supplied with the first video signal power I, and the second auxiliary capacitor 8a is also provided. The second auxiliary capacitor of the capacitor line supplies a second video signal voltage. Then, the TFT9 is turned off.

314297.ptd Page 15 573291 In the description of the 5 'invention (12) accompanying the above situation, the source voltage of the TFT 9 Vs will decrease by 5 and the auxiliary capacitors 1 0 a and 1 0 b connected to it will decrease in voltage 0 'According to this embodiment, when the TFT 9 is in the off state, the supply level to the first auxiliary capacitor line 8 a will change to the first: The voltage polarity maintained by the U capacitor (at this time, the source voltage of the day element) (V s or day electrode voltage V (polarity)), and the second auxiliary capacitor line 8 b is supplied with a polarity opposite to that of the first auxiliary capacitor voltage VCa, and the level will be Change to the first auxiliary power. The voltage polarity (capacity of the day voltage source voltage Vs or the day electrode voltage V 容 polarity) of the second auxiliary capacitor 7 capacitor voltage VCb. It can be borrowed • TFT9 To cut off the holding voltage of the first and second auxiliary capacitors that have changed, and to increase the electric-voltage held by the first and second auxiliary capacitors. In this embodiment, by performing a dot reverse driving, the influence caused by the voltage of the adjacent video signals can be eliminated, and the image streaks (unevenness) caused by the capacitor combination can be prevented. During the period when the switching element (TFT9) is in the off state, the first and second auxiliary capacitor lines are inverted at the same time. 5 The first or second auxiliary capacitor voltages of opposite polarity are applied, respectively. 0 The amplitude of the video signal voltage is narrowed, a sufficient voltage can be applied to the liquid crystal, and power consumption can be reduced. «≫ In this embodiment, in order to reduce the daytime image streaking or flickering phenomenon as much as possible, the first and second auxiliary capacitor lines 8 a and 8 b are in units of one pixel, and δ is set to have an interaction in the row direction. Structure of auxiliary capacitor electrode. However, the present invention is not limited to this. In the row direction, a continuous plural number of daylight elements is used as the unit 9. It is set as an interactive arrangement. The structures of the first and second auxiliary capacitors 10a and ‘10b are also

314297.ptd Page 16 573291 V. Description of the invention (13) " bj- 〇 For example, it can also be applied to the three daylight elements displaying the RGB primary colors as a unit, and each unit is configured with the first or second subsidy The auxiliary capacitors 10a and 10b are connected to any one of the capacitance lines 8a and 8b. Next, a second embodiment will be described. In the first embodiment, as shown in FIG. 2, the first storage capacitor line 8 a and the second storage capacitor line 8 b are formed to overlap with all the storage capacitor electrodes 10 ×. On the other hand, only in the pixel region where the auxiliary capacitor electrode 10z that forms the first auxiliary capacitor line 8a and the second auxiliary capacitor line 8b exists, there is a semiconductor connected to the first auxiliary capacitor line 8a and the auxiliary capacitor electrode 10z. The layer f overlaps the overlapping portion 1 3. In this overlapping portion, parasitic capacitance C PAR will be generated. The second embodiment is to solve the problem caused by the parasitic capacitance C PARH formed in the second auxiliary capacitance 10 b. Fig. 6 is a plan view of a display panel according to a second embodiment of the present invention, and Fig. 7 is an equivalent circuit diagram thereof. Those having the same configuration as the first embodiment are given the same reference numerals and descriptions are omitted. This embodiment is different from the first embodiment in that a dummy area extending from the auxiliary capacitor electrode 10 y and overlapping the second auxiliary capacitor electrode 8 b is provided in a pixel region having the auxiliary capacitor electrode 10 y. Wiring 1 4. The dummy wiring 14 is formed with an overlapped portion 1 3 ′ with a second auxiliary capacitor line 8 b where no auxiliary capacitor is formed, thereby forming a heavy portion 13 with the auxiliary capacitor electrode 10 z and the auxiliary capacitor line 8 a. The parasitic capacitance C ρα ^ C par of the temple. In the first embodiment, since the parasitic capacitance CPAR is generated only in the overlapping portion 13 of the auxiliary capacitor electrode 10 Z and the first auxiliary capacitor line 8a, only the second auxiliary capacitor having the auxiliary capacitor electrode 1 0 z. 1 0 b The potential will decrease. therefore,

314297.ptd Page 17 573291 V. Description of the invention (14) Between the daylight region where the auxiliary capacitor electrode is 10 y and the daylight region where the auxiliary capacitor electrode is 10, for the daylight region in each daylight region The magnitude of the optimal counter electrode voltage of electrode 6 will vary, so comparison (c ο ntrast) is prone to shift or flicker. However, in this embodiment, by forming the dummy wiring 14 on the first storage capacitor electrode 1 Ox ', a voltage equal to the first storage capacitor is formed. 1 0 X \ and a second storage capacitor that does not form a storage capacitor is formed. Since the line 8 b and the dummy wiring 14 overlap with each other, the overlapping portion 1 3 ′ generates a parasitic capacitance C PAR ′. As a result, by balancing the polarity between the first auxiliary capacitor 10a and the second auxiliary capacitor 10b, it is possible to eliminate the difference in the magnitude of the optimal opposing electrode voltage of each pixel electric-electrode 6, and eliminate Contrast-(c ο ntrast) shift or flicker caused by this difference. Next, a third embodiment will be described. FIG. 8 is a plan view of a display panel according to a third embodiment of the present invention, and FIG. 9 is an equivalent circuit diagram thereof. The same components as those in the first embodiment are denoted by the same reference numerals and explanations are omitted. In this embodiment, the arrangement of the drain line 5 and the day element electrode 6 is the same as that of the first to second embodiments. This embodiment differs from the first and second embodiments in that the gate line 7 is located in the center of the day electrode, and is sandwiched between the first auxiliary capacitor line 8 a and the second auxiliary capacitor line 8 b. Way configured. Furthermore, the pixel lines are integrally formed with the gate lines 7 in each pixel region, and the gate system constituting the TFT 9 is formed in a region where the complementary capacitor electrodes 10 × are arranged with the gate line 7 as a boundary line. In the second embodiment, since the auxiliary capacitor electrode which is originally required is added to arrange the virtual wiring, the type (pa 11 e r η) is complicated, and the aperture ratio is reduced.

314297.ptd Page 18 573291 V. Description of Invention (15) Low.

^ However, in this embodiment, the gate line 7 is arranged between the first auxiliary capacitor line 8 a and the second auxiliary capacitor 8 b. Since all the auxiliary capacitor electrodes 1 0 X are only auxiliary Either the first auxiliary capacitor line 8 a or the second auxiliary capacitor 8 b of the capacitor overlaps, so the overlapping portion 13 and the overlapping portion 1 3 ′ are not needed, and the parasitic capacitance C generated in the overlapping portion can be eliminated. PAR ° —— Furthermore, in this embodiment, the distance between the second auxiliary capacitor line 8 b and the TFT 9 can be shortened to reduce the wiring resistance. In addition, since the semiconductor layer and the area required for forming the auxiliary capacitor electrode 10 z of the first embodiment or the dummy wiring 14 of the second embodiment can be reduced, the aperture ratio can be increased. In each embodiment, although the dual-gate TFT is taken as an example, the present invention is not limited to this, and the gate may be constituted by one or three or more gates. Furthermore, although the auxiliary capacitor line is formed on the same layer as the gate line, the auxiliary capacitor line may be formed on a different layer from the gate line. Furthermore, in each embodiment, although a dynamic matrix liquid crystal display device is taken as an example, the present invention is not limited to this, and it can also be applied to a dynamic matrix type electroluminescence (EL) display device. As described above, in this embodiment, the first and second auxiliary capacitor lines corresponding to the columns of the pixel electrodes and extending in the horizontal direction are provided, and the rows of the pixel electrodes are alternately arranged. The auxiliary capacitor corresponding to the first and second auxiliary capacitor lines. In this way, signals having different polarities can be supplied to the respective auxiliary capacitor lines. Therefore, the voltages of different polarities are applied to each adjacent pixel by the first and second auxiliary capacitor lines, thereby realizing

314297.ptd Page 19 573291 V. Description of the invention (16) _ The so-called dot inversion drive. In addition, by applying the first video signal voltage whose polarity is reversed during each frame applied to the day element electrode, either the first video signal voltage or the second video signal voltage which has the opposite polarity to the first video signal voltage- It is preferable that the display is performed, and the first and second auxiliary capacitor voltages are supplied to the first and second auxiliary capacitor lines in opposite phases to each other and which change during the switching element OFF (OFF). In particular, the polarities of the first video signal voltage and the first auxiliary capacitor voltage are the same, and the polarities of the second video signal voltage and the second auxiliary capacitor voltage are the same. In this way, the dot inverse driving caused by the aforementioned auxiliary capacitor line can be realized, and the amplitude of the video signal voltage can be reduced. In addition, it is preferable that the first and second auxiliary capacitor lines have a plurality of continuous day-electrode electrodes in a unit of a row and have auxiliary capacitor electrodes alternately. For example, if the celestial electrodes of the three primary colors RGB of the display color are a group, a voltage of opposite polarity can be applied to each adjacent group. In this way, reverse driving of the group unit can be realized. 'Furthermore, it is preferable that the first and second auxiliary capacitor lines overlap each of the rows forming the day-electrode-corresponding arrangement of all auxiliary capacitor electrodes. In this way, it is possible to balance the polarities of the parasitic capacitances generated in the area where the auxiliary capacitor line and the auxiliary capacitor electrode do not form the auxiliary capacitor, so that Φ prevents daytime image streaks. Furthermore, in the daytime pixel region where the pixel electrode is formed, the gate line is preferably disposed between the first and second auxiliary capacitor lines. In this way, the area overlapping with the storage capacitor line and the storage capacitor electrode that do not form the storage capacitor can eliminate the parasitic capacity generated in the area, and can prevent image streaks.

314297.ptd Page 20 573291 V. Description of the invention (17) In the daylight region, it is extremely suitable to form a gate constituting a switching element in the area where the auxiliary capacitor electrode is arranged for the gate line as the boundary line. . In this way, the area that is complementary to the auxiliary capacitor line and the auxiliary capacitor electrode that do not form the auxiliary capacitor can eliminate the parasitic capacity generated in the area and prevent daytime image streaks. In this dynamic matrix display device, a common electrode (counter electrode 1 1) is arranged on the second substrate, and a certain voltage is applied to the common electrode. In this way, the voltage of the common electrode with a large area can be prevented from changing, and the dynamic matrix display device can be driven with a lower voltage and power consumption. In addition, during the period when the switching element (TFT9) is turned off, the levels of the first and second auxiliary capacitor voltages are reversed immediately after the switching element is turned off. Due to the influence, the charge of the auxiliary capacitor that has been changed can be filled during the period when the voltage held by the first and second auxiliary capacitors is small. Therefore, the first and second auxiliary capacitors can be obtained. The more charge the voltage increases. Therefore, according to this embodiment, a dynamic matrix display device with high display quality can be provided. … Here, voltages of the same polarity can be applied to daylight electrodes adjacent to each other in the direction of the drain line. At this time, the vertical reverse driving is performed as shown in Fig. 10 (a). However, when considering characteristics, as shown in Fig. 10 (b), it is appropriate to apply dot inversion driving to all pixels adjacent to the top, bottom, left, and right to the opposite polarity. As shown in the figure, in any driving method, each frame will be applied with the previous one.

314297.ptd Page 21

57329L V. Description of the invention (18) Voltages with opposite polarities in the frame. By performing dot inversion driving, liquid crystal degradation can be prevented in one direction, and K can effectively prevent capacitor combination.

3M297.ptd Page 22 573291 Schematic description [Schematic description] '' Figure 1 is a plan view of a display panel of a dynamic matrix display device. Fig. 2 is a plan view of a display panel according to a first embodiment of the present invention. Fig. 3 is an equivalent circuit diagram of a display panel according to the first embodiment of the present invention. Fig. 4 is a timing chart showing the relationship between signals in the display panel according to the first embodiment of the present invention. Figures 5 (a) and 5 (b) are signal waveform diagrams showing a method for driving the display device according to the first embodiment of the present invention. Fig. 6 is a plan view of a display panel according to a second embodiment of the present invention. Fig. 7 is an equivalent circuit diagram of a display panel according to a second embodiment of the present invention. Fig. 8 is a plan view of a display panel according to a third embodiment of the present invention. Fig. 9 is an equivalent circuit diagram of a display panel according to a third embodiment of the present invention. Figures 10 (a) and 10 (b) are conceptual diagrams showing vertical inversion driving and dot inversion driving. FIG. 11 is an equivalent circuit diagram of a conventional display panel. Fig. 12 is a signal waveform diagram showing a driving method of a conventional display device. 1 Display panel 2 Drain driver 3 Gate driver 4 Display area

314297.ptd Page 23 573291 Brief description of the diagram 5 Drain line 7, 1 0 7 Gate line 8b Second auxiliary capacitor line 9 g Gate 9 s Source area I 0 b Second auxiliary capacitor II Counter electrode 1 3, 1 3 'overlapping part 1 0 5 没 极 线 # 0 auxiliary capacitor 1 1 2 liquid crystal capacitor CKH horizontal clock signal GV BU GV2, GV3 gate signal STV vertical start signal V (; gate voltage V s source Voltage Vse auxiliary capacitor voltage 6 day element electrode 8a first auxiliary capacitor line-.

9, 109 TFT 9d Drain region 10a: 1st auxiliary capacitor 1 0 X, 1 0 y, 1 0 z auxiliary capacitor electrode 1 2 liquid crystal capacitor 14 virtual wiring 1 0 8 auxiliary capacitor line 1 1 1 counter electrode-CKV vertical Clock signal C PAK Parasitic capacitance SCa, SCb Potential STH level Start signal VP Daylight voltage VD, VDa, VDb Video signal voltage V COM Counter electrode voltage

314297.ptd Page 24

Claims (1)

573291 VI. Application for patent scope 1. A dynamic matrix display device, which is arranged in a matrix type, and controls the display of each day element; this device has a plurality of lines extending in the horizontal direction, and A gate line for transmitting the gate voltage; _ A plurality of data lines extending in the vertical direction for transmitting the voltage of the video signal, a switching element arranged corresponding to the intersection of the gate line and the aforementioned data line; A component, a pixel electrode connected to the aforementioned data line; and a plurality of first and second auxiliary capacitor lines extending in the horizontal direction corresponding to the respective rows of the pixel electrode; 2 Any one of the auxiliary capacitor lines is arranged to overlap the auxiliary capacitor electrode at each day element. 2. For example, the dynamic matrix type display device of the scope of application for the patent, wherein the first and second auxiliary capacitor voltages which are opposite to each other and change during the switching period of the switching t element are supplied to the aforementioned first and second, respectively. The second auxiliary capacitor line. 3. For example, the dynamic matrix display device of the scope of patent application, wherein a certain voltage is applied to the counter electrodes formed on the counter substrate opposite to the substrate on which the daylight electrode is formed, which will be opposite to each other and The first and second auxiliary capacitor voltages that change during the aforementioned switching element cut-off period are supplied to the aforementioned .1 and second auxiliary capacitor lines, respectively. 314297.ptd Page 25 573291 VI. F patent scope 4. For the dynamic matrix display device of the first scope of the patent application, the auxiliary capacitor electrode of each day element is based on each line of day element, and 'Either the first or second auxiliary capacitor line overlaps alternately. 5. For example, the dynamic matrix display device of the scope of patent application, wherein the auxiliary capacitor electrode of each day element is in the unit of continuous plural lines of the day element, and is the same as the first or second subsidy. Any one of the capacitor lines overlaps alternately. 6. For example, the dynamic matrix type display device of the scope of the patent application, wherein the aforementioned first and second auxiliary capacitor lines are all the aforementioned auxiliary capacitors arranged corresponding to the columns of Lu Zhisu forming such auxiliary capacitor lines. The electrodes overlap. • 7. The dynamic matrix type display device according to item 6 of the scope of patent application, wherein the auxiliary capacitor electrode has: among the first or second auxiliary capacitor lines, one side forms the auxiliary capacitor and does not form the auxiliary capacitor line. The auxiliary capacitor line on the other side of the auxiliary capacitor is a virtual wiring. .8. In the dynamic matrix type display device according to item 1 of the scope of patent application, in the pixel region forming the pixel electrode, the gate line is disposed between the first and second auxiliary capacitor lines. _ For example, the dynamic matrix display device of the eighth scope of the patent application, wherein, in the aforementioned daylight region, the aforementioned gate line, the aforementioned gate line as a boundary line, and the aforementioned area of the auxiliary capacitor electrode are formed, The gate of the switching element is formed. 1 0. —A kind of dynamic matrix display device, which is arranged in a matrix type for multiple days 314297.ptd Page 26 573291 6. Apply for a patent range and control its display for each day element; it has, on the first substrate, a plurality of pixel electrodes arranged in rows and columns; A switching element connected to a pixel electrode; an auxiliary capacitor electrode disposed in each of the day pixel regions where the aforementioned day electrode is disposed; first and second auxiliary capacitor lines disposed corresponding to the aforementioned pixel electrodes in each column; and, The first and second auxiliary capacitors which are opposite to any of the first or second auxiliary capacitor lines and the auxiliary capacitor electrodes; wherein the daylight electrode and the auxiliary capacitor electrode are applied to each During a frame, either the first video signal voltage whose polarity is reversed or the second video signal voltage whose polarity is opposite to the aforementioned first video signal voltage is displayed in a manner that is cut at the switching element During the off state, the first and second auxiliary capacitor voltages that have changed in the supply level of the first and second auxiliary capacitor lines, respectively. 11. The dynamic matrix display device according to item 10 of the scope of patent application, wherein the first video signal voltage is supplied to the first auxiliary capacitor electrode while the second auxiliary capacitor is in the period when the switching element is in the on state. The electrode supplies the second video signal voltage, and the level of the first auxiliary capacitor voltage supplied to the first auxiliary capacitor electrode is changed with the same polarity as the first video signal voltage while the switching element is in an off state. This level supplies the second auxiliary capacitor voltage to the second auxiliary capacitor electrode. 314297.pid Page 27 573291 6. The level of patent application shall be changed with the same polarity as the voltage of the second video signal. -1 2. The dynamic matrix type display device according to item 10 of the patent application scope, wherein the first video signal voltage is supplied to the first auxiliary capacitor electrode while the switching element is in an on state, and the first video signal voltage is supplied to the first auxiliary capacitor electrode. The auxiliary capacitor line is supplied with the polarity of the first video signal voltage. The first auxiliary capacitor voltage is supplied to the second auxiliary capacitor electrode before the second video signal voltage, and is supplied to the second auxiliary capacitor line. The second auxiliary capacitor voltage with the opposite polarity of the video signal voltage; during the period when the switching element is in the off state, the level of the first auxiliary capacitor voltage will change with the same polarity as the first video signal voltage. The level of the second auxiliary capacitor voltage is changed with the same polarity as the voltage of the second video signal. 1 3. The display device of the dynamic moment 7 type vehicle according to item 10 of the patent application, wherein a common electrode is arranged on the second substrate, and a certain voltage is applied to the aforementioned common-electrode. 1 4. The dynamic matrix type display device according to item 10 of the scope of patent application, wherein during the period when the switching element is in the off state, the first and second auxiliary capacitor voltages are in the position after the switching element is turned off instantaneously. Change will happen immediately. 314297.ptd Page 28