TWI395315B - 在超高壓元件的高壓路徑上提供esd保護的結構 - Google Patents

在超高壓元件的高壓路徑上提供esd保護的結構 Download PDF

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TWI395315B
TWI395315B TW099113056A TW99113056A TWI395315B TW I395315 B TWI395315 B TW I395315B TW 099113056 A TW099113056 A TW 099113056A TW 99113056 A TW99113056 A TW 99113056A TW I395315 B TWI395315 B TW I395315B
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Jian Hsing Lee
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41758Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
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    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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Description

在超高壓元件的高壓路徑上提供ESD保護的結構
本發明係有關一種超高壓元件(ultra-high voltage device),特別是關於一種為超高壓元件提供靜電放電(Electro-Static Discharge;ESD)保護的結構。
在本文中,超高壓係指500V以上的電壓。圖1係習知的超高壓元件的垂直剖面圖,在P型基板10上形成P型磊晶層12,其上形成P型井14與高壓N型井16,高壓N型井16上成長氧化物28,從其未覆蓋的開口摻雜而形成接觸區18,其經接點柱20、第一金屬層22、導孔26及第二金屬層24等結構而連接到高壓端HV,此即超高壓元件之高壓路徑。高壓N型井16使超高壓元件具有較高的崩潰電壓,以便提供高壓操作。
超高壓元件通常具有非常巨大的尺寸,而ESD保護結構會增加電路佈局的尺寸,因此不適合再施作於超高壓元件上。即使超高壓元件的尺寸已經非常巨大,但是仍然不能達到最小的ESD要求,其問題在於超高壓元件的不均勻。由於ESD是一種大電流的現象,超高壓元件不均勻處將導致電流的聚集使電流無法均勻分散。參考圖2,其中的上圖係圖1的超高壓元件的布局圖,下圖係該布局中的部份區域30的局部放大,在水平剖面上,連接柱20具有長條形狀的結構。圖2中的接觸區末端32為超高壓元件常見的不均勻處,當有ESD般的大電流通過時將造成電流的聚集,同時產生相當大的熱導致局部高溫而使超高壓元件熔毀。只要超高壓元件的高壓路徑有任一區段熔毀,該超高壓元件便失去承受高壓的能力而無法繼續使用。
目前尚未有為超高壓元件的高壓路徑提供ESD保護的技術,只能依賴超高壓元件的自身保護結構。
本發明的目的之一,在於提出一種為超高壓元件提供ESD保護的結構。
根據本發明,一種超高壓元件的高壓路徑建立於從高壓N型井經第一金屬層至第二金屬層,在該高壓N型井及第一金屬層之間有連接柱,其在水平剖面上具有分散式的結構以提高該超高壓元件的均勻度,使該高壓路徑上的電流均勻地散佈,因而避免電流分佈不均勻所導致的局部熱聚集的情況發生,降低該超高壓元件的損毀率。
較佳者,更包含多個熔絲裝置彼此獨立地連接該第一金屬層,該熔絲裝置含有多晶矽熔絲在承載的電流過大時熔毀。
圖3係本發明之第一實施例,其垂直剖面圖與圖1相同,但是連接柱20在水平剖面上具有分散式的結構,接觸區18在水平剖面上隨形於連接柱20,因而呈現點狀分布的多個隔離島區域。此分散式的結構可以提高超高壓元件的均勻度,使高壓路徑上的電流均勻地散佈,當有ESD般的大電流通過時,因而避免電流分佈不均勻所導致的局部熱聚集的情況發生,降低超高壓元件的損毀率。在此實施例中,要形成分開的接觸區18及分散式的連接柱20,只要改變其定義的圖案即可,因此不會增加製程的步驟,也不會增加電路的尺寸。
圖4及圖5係本發明之第二實施例的垂直剖面圖與局部布局圖,除了連接柱20在水平剖面上具有分散式的結構,更增加多個熔絲裝置40於高壓路徑上。每一熔絲裝置40包含多晶矽熔絲42,其兩端分別經接點柱44及46連接第一金屬層22的第一部份48及第二部份50。第一部份48及第二部份50都是第一金屬層22的一部份,但是彼此隔離。因為第二金屬層24經多個導孔26與第一金屬層22的每一第二部份50連接,所以全部的熔絲裝置40係並聯在接觸區18及第二金屬層24之間。由於接點柱20、44、46、第一金屬層22及第二金屬層24皆是金屬材質,因此適當長度的多晶矽熔絲42在遭受過大電流時會先行毀損。當流經某一區段的多晶矽熔絲42的電流到達其飽和電流時,多晶矽熔絲42會變成一具有高阻抗的電阻,迫使電流流往其他未達飽和電流的多晶矽熔絲42,雖然電壓可能持續增加但是電流不會再增加,因此電流便均勻的分佈在所有的熔絲裝置多晶矽熔絲42上。即使某一區段的多晶矽熔絲42上的電流超過其飽和電流時,則電流會先將該區段的多晶矽熔絲42熔毀而形成斷路,因此電流就不會流向接觸區18,避免接觸區18燒毀形成短路,而其餘具有完好的多晶矽熔絲42的區段仍能使超高壓元件正常動作。多晶矽熔絲42係由多晶矽層提供,接點柱44及46係在製作接點柱20時一併形成,因此本實施例不會增加製程的步驟。熔絲裝置40係配置在氧化物28的上方,因此不會擴大電路布局。
圖6係結合前述兩實施例的第三實施例,除了圖5的結構,接觸區18也跟隨著連接柱20個別地獨立分開,因而呈現點狀分布的多個隔離島區域。
如以上各實施例所示,本發明在不改變超高壓元件的尺寸、電流電壓特性及製程的情況下,將其ESD性能改善到可接受的程度。
以上對於本發明之較佳實施例所作的敘述係為闡明之目的,而無意限定本發明精確地為所揭露的形式,基於以上的教導或從本發明的實施例學習而作修改或變化是可能的,實施例係為解說本發明的原理以及讓熟習該項技術者以各種實施例利用本發明在實際應用上而選擇及敘述,本發明的技術思想由以下的申請專利範圍及其均等來決定。
10...P型基板
12...P型磊晶層
14...P型井
16...高壓N型井
18...接觸區
20...接點柱
22...第一金屬層
24...第二金屬層
26...導孔
28...氧化物
30...超高壓元件的局部區域
32...接觸區末端
40...熔絲裝置
42...多晶矽熔絲
44...接點柱
46...接點柱
48...第一金屬層的第一部份
50...第一金屬層的第二部份
圖1係習知的超高壓元件的垂直剖面圖;
圖2係習知的超高壓元件的水平面布局圖;
圖3係本發明之第一實施例的水平面布局圖;
圖4係本發明之第二實施例的垂直剖面圖;
圖5係本發明之第二實施例的水平面布局圖;以及
圖6係本發明之第三實施例的水平面布局圖。
16...高壓N型井
18...接觸區
20...接點柱
26...導孔
28...氧化物

Claims (3)

  1. 一種在超高壓元件的高壓路徑上提供ESD保護的結構,該高壓路徑係建立於從高壓N型井經第一金屬層至第二金屬層,該提供ESD保護的結構包含:連接柱連接於該高壓N型井及第一金屬層之間,在水平剖面上具有分散式的結構;以及接觸區在該高壓N型井上,供該連接柱電性接觸,且在該水平剖面上隨形於該連接柱而呈現點狀分布的多個隔離島區域。
  2. 一種在超高壓元件的高壓路徑上提供ESD保護的結構,該高壓路徑係建立於從高壓N型井經第一金屬層至第二金屬層,該提供ESD保護的結構包含:連續的接觸區在該高壓N型井上;第一連接柱在水平剖面上具有分散式的結構電性接觸該接觸區且連接該第一金屬層;以及多個熔絲裝置彼此獨立地連接該第一金屬層;其中,每一該熔絲裝置包含:由該第一金屬層提供的彼此隔離的第一部份及第二部份,該第一部份連接該第一連接柱,該第二部份經導孔連接該第二金屬層;第二及第三接點柱分別連接該第一金屬層的第一及第二部份;以及多晶矽熔絲連接該第二及第三接點柱。
  3. 一種在超高壓元件的高壓路徑上提供ESD保護的結構,該高壓路徑係建立於從高壓N型井經第一金屬層至第二金屬層,該提供ESD保護的結構包含:第一連接柱連接於該高壓N型井及第一金屬層之間,在水平剖面上具有分散式的結構;以及接觸區在該高壓N型井上,供該第一連接柱電性接觸,且在該水平剖面上隨形於該第一連接柱而呈現點狀分布的多個隔離島區域;以及多個熔絲裝置彼此獨立地連接該第一金屬層;其中,每一該熔絲裝置包含:由該第一金屬層提供的彼此隔離的第一部份及第二部份,該第一部份連接該第一連接柱,該第二部份經導孔連接該第二金屬層;第二及第三接點柱分別連接該第一金屬層的第一及第二部份;以及多晶矽熔絲連接該第二及第三接點柱。
TW099113056A 2010-04-26 2010-04-26 在超高壓元件的高壓路徑上提供esd保護的結構 TWI395315B (zh)

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TWI521659B (zh) 2013-05-02 2016-02-11 乾坤科技股份有限公司 電流導通元件
US9768283B1 (en) * 2016-03-21 2017-09-19 Vanguard International Semiconductor Corporation High-voltage semiconductor structure
CN107611121B (zh) * 2016-07-11 2020-12-29 联华电子股份有限公司 用于静电放电保护的半导体结构

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