九、發明說明： 【發明所屬之技術領域】 本發明係_-種電路板的製作方法，尤指—種利用二次壓 膜法’填充位於電路板上之導電通孔啊製作增層絶緣層 ，以提 供更佳的細線路良率。 【先前技術】 如熟習該項技藝人士所知，印刷電路板通常採用增層法來進 行導線線路的製作。增層方式可採用膜狀介電材(DielectricFilm) 壓合而成，另外也有採用背膠銅箔(Rcc)，或預浸材(Prepreg)壓 合而成。 一般來說，增層法的步驟包括：取一基板包含貫穿基板的導 電通孔以及一電路圖案層，之後於導電通孔内填入一填充材，然 後再於基板的表面壓合一介電層作為增層絶緣層，其中該介電層 覆蓋前述之電路圖案層以及其間隙，經過固化後，再於介電層上 進行雷射鑽孔，然後進行表面粗化，並覆蓋晶種層，再用光阻形 成線路圖案’接著進行導電層之電鍍，最後去除光阻層及外露之 晶種層形成所謂之增層線路層(build up fllm)。 前述的利用填充材填滿導電通孔之步驟，於習知技術中一般 是使用油墨或是含銅導電膏填滿導電通孔，之後以刷磨製程去除 多餘的介電層，以維持基板表面平坦。但刷磨製程在刷磨過後產 1378752 生介電層殘留和刷磨過度的問題。 此外，前述之介電層通常是一含纖維之樹脂型材料，例如： bismaleimide triazine (BT) ’其優點在於材質堅硬，可有效支標後續 增層線路’但是其表面卻無法提供均勻的粗链化效果，造成後續 的細線路便無法與其緊密貼合。IX. Description of the Invention: [Technical Field] The present invention relates to a method for fabricating a circuit board, in particular, a method of using a secondary lamination method to fill a conductive via hole on a circuit board to form a build-up insulating layer To provide better fine line yield. [Prior Art] As is known to those skilled in the art, printed circuit boards are usually formed by a build-up method for wire routing. The layering method can be formed by pressing a dielectric material (DielectricFilm), or by using a backing copper foil (Rcc) or a prepreg (Prepreg). Generally, the step of the build-up method includes: taking a substrate including a conductive via hole penetrating the substrate and a circuit pattern layer, and then filling a conductive material into the conductive via hole, and then pressing a dielectric on the surface of the substrate The layer serves as a build-up insulating layer, wherein the dielectric layer covers the circuit pattern layer and the gap thereof, and after curing, laser drilling is performed on the dielectric layer, and then the surface is roughened and the seed layer is covered. Then, the photoresist is used to form the wiring pattern', followed by electroplating of the conductive layer, and finally the photoresist layer and the exposed seed layer are removed to form a so-called build up fllm. The foregoing step of filling the conductive via holes with a filler material generally fills the conductive via holes with ink or a copper-containing conductive paste in the prior art, and then removes the excess dielectric layer by a brushing process to maintain the surface of the substrate. flat. However, the brushing process produced 1378752 problems of residual dielectric layer and excessive brushing after brushing. In addition, the aforementioned dielectric layer is usually a fiber-containing resin type material, for example: bismaleimide triazine (BT) 'The advantage is that the material is hard and can effectively support the subsequent build-up line' but the surface cannot provide a uniform thick chain. The effect is that the subsequent fine lines cannot be closely attached to them.
再者’隨著電路板上的線路越做越細，對於基板表面平坦度 的要求也因此日趨祕。在傳統增層法中所使用的介電層在固化 時’由於其包麵賴會隨著烘烤加熱而揮發， 層表面會軸_異常、表面平坦度不佳的現象 細線路製程的良率。 固化後，在介電 ，影響到後續的 【發明内容】 本— •糊输絶_介刪直接填滿 、續的刷磨製程。或是含銅導電膏填導電通孔及後 使製程簡單化並且降低電路板之製作成本。 介電綱料恤—層第一 過固化製程後，再料圖案上並且填滿導電通孔，待其經 緣層，是經過衫第二介電層，也就是說同-層増層絶 -經過固化時，其内二所;之形成和固化步驟所製成。第一介電層 、鬥邛所包含的溶劑會在固化過程揮發，使得第一 7 在其表面形成凹陷’尤其是覆於導電通孔之正 其凹陷極為嚴重，接著，藉由塗佈第二介電#， 電層，：1 電層表面的凹陷填平。她於傳統製程只塗饰-層曰介 θ發明之縣可提供更佳的增層介電材料表面平坦度。 八本發明的另-特徵是使用相同材料作為第—介電層和及第二 W電層’其優點在於以相_介電材料進行後續的盲孔加工製 2其盲孔孔控大小容易控制，此外，於相同的介電材料做表面 ，其表面及孔内的粗糙均勻性較易控制。 、根據本㈣之紐實侧，本發贿供—種電路板的製造方 法*包含有町步驟：提供—基板，其上設有―第—導線圖案及 一貫穿該基板之導電通孔；於該基板上覆蓋—第—介電層，使該 第-介電層㈣住該第—導制钱且填滿該導電通孔；固化該 第一介電層；於該第-介電層表面覆蓋—第二介電層；以及固化 該第一介電層；其中該第—介電層與該第二介電層為相同的樹脂 材料所構成者。 【實施方式】 請參閱第1圖至第5圖，其繪示的是本發明電路板製造方法 之較佳實施例的剖面示意圖。首先，如第i圖所示，提供一基板 10，於基板10上形成有貫穿基板1〇之導電通孔，再經過鍵銅 及圖案化製程，於基板10之表面以及導電通孔12之表面上形成 1378752 °C〜200°C ’廢力可以為1〜l〇kg/cmz。此外，介電層16的材料可以 為ABF (Ajinomoto Build-up Film)、環氧樹脂、非纖維環氧樹脂、 氰脂、玻璃纖維、雙順丁烯二酸醯亞胺、BT或混合環氧樹脂與玻 纖材料。值得注意的是：本發明之介電層丨6、18係使用相同材料， 例如’介電層16、18之材料為皆為ABF或皆為BT等材料。 接著，進行烘烤製程，將介電層18固化，此時即完成電路板 上的一增層絶緣層17。值得注意的是，以本發明製程所形成的增 層絶緣層17，其平均凹陷值可有效控制在1//m之内。此外，本 發明不限疋只覆蓋二層介電層，如介電層16、18覆蓋於導線圖案 14表面以及填充導電通孔12，若是介電層18經過固化後其凹陷 值依然過大，亦可於介電層18之表面依前賴壓膜、固化等步驟 繼續重獅成與介電層18綱材制介電層，直酬層絶緣層之 表面平坦度達到要求。 然後，如第5圖所示，於增層絶緣層17上進行雷射鑽孔，形 成數個盲孔，讀，於騎、層n之表面進行去縣及粗化製 程。接著’於增層絶緣層17上形成—導電圖㈣， 2〇可以是金射，例如銅層，或者 ’、導财案 其匕任何可以導電之材料所 構成。本發明之製程可視需求，依據前述步驟 緣層的製程，以形成—具有多層線路之電路板。▲色 如上所述，本發明提供—種電路板製程，針對傳統技術在製 1378752 作電路板時使用填充材填滿導電通孔再進行刷磨使基板表面平坦 之步驟加以改進，因傳統製程經常在刷磨過程中造成刷磨過度或 是介電材料殘留的缺失，因此本發明以作為增層絶緣層的介電材 料直接填滿導電通孔，所以可省略傳統製程所使用的填充材並且 也不需要後續的刷磨製程。不但簡化了電路板製程同時也降低了 電路板之製作成本。 ^ 再者，傳統技術在製作電路板之增層時，經常產生增層絶緣 層之表面不平坦，尤其以位於導電通孔上方的增層絶緣層其出現 凹陷的情形最為嚴重，為此，本發明提供有效的解決方式，改善 增層絶緣層表面的凹陷問題，增加後續細線路之良率。 此外，本發明的另一特徵是所形成的第一層介電層和第二層 介電層係使用侧介電材料，其優點於後續在增層絶緣層上進行 雷射鑽孔時’孔徑大小較易控制，此外在粗化增層絶緣層時，其 # 表面及孔内的粗糙均勻性亦較易控制。 以上所述僅林發明讀佳實_，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 請參閲第1圖至第5圖，其繪示的是本發明板製造方法之較 佳實施例的剖面示意圖。Furthermore, as the lines on the board become thinner, the requirements for the flatness of the surface of the substrate are becoming more and more secret. The dielectric layer used in the conventional build-up method is volatilized during curing due to its cladding surface, and the surface of the layer will have an abnormal axis and abnormal surface flatness. . After curing, in the dielectric, affecting the subsequent [invention] This - the paste into the _ to delete the direct filling, continued brushing process. Or the copper-containing conductive paste fills the conductive vias and then simplifies the process and reduces the manufacturing cost of the board. After the first over-curing process, the dielectric pattern is filled and filled with conductive vias, and the via layer is passed through the second dielectric layer of the shirt, that is to say, the same layer is layered. When cured, it is made in two parts; the formation and curing steps. The solvent contained in the first dielectric layer and the bunk will volatilize during the curing process, so that the first 7 forms a recess on the surface thereof, especially the conductive via hole is extremely severely depressed, and then, by coating the second Dielectric #, electric layer,: 1 The depression on the surface of the electric layer is filled. She only painted in the traditional process - the layer of the invention θ can provide better surface flatness of the dielectric layer. Another feature of the eight inventions is that the same material is used as the first dielectric layer and the second W electrical layer', which has the advantage of subsequent blind hole processing by phase-dielectric material. In addition, the surface of the same dielectric material is used to make the surface and the roughness uniformity in the hole is easier to control. According to the (4) of the new side, the method for manufacturing a bribe supply board includes a step of providing a substrate with a "first-conductor pattern and a conductive via extending through the substrate; The first overlying dielectric layer is cured on the substrate, and the first dielectric layer is cured; the first dielectric layer is cured; the first dielectric layer is cured; and the first dielectric layer is cured on the surface of the first dielectric layer Covering the second dielectric layer; and curing the first dielectric layer; wherein the first dielectric layer and the second dielectric layer are composed of the same resin material. [Embodiment] Referring to Figures 1 to 5, there is shown a cross-sectional view of a preferred embodiment of a method of fabricating a circuit board of the present invention. First, as shown in FIG. 1, a substrate 10 is provided, and a conductive via hole penetrating through the substrate 1 is formed on the substrate 10, and then subjected to a key copper and a patterning process on the surface of the substrate 10 and the surface of the conductive via 12. Formed on 1378752 °C ~ 200 °C 'The waste force can be 1~l〇kg/cmz. In addition, the material of the dielectric layer 16 may be ABF (Ajinomoto Build-up Film), epoxy resin, non-fiber epoxy resin, cyanide, glass fiber, bis-maleimide, BT or mixed epoxy. Resin and glass fiber materials. It should be noted that the dielectric layers 丨6, 18 of the present invention are made of the same material, for example, the materials of the dielectric layers 16, 18 are all ABF or both are BT. Next, a baking process is performed to cure the dielectric layer 18, at which point an build-up insulating layer 17 on the board is completed. It is to be noted that the average insulating value of the build-up insulating layer 17 formed by the process of the present invention can be effectively controlled within 1/m. In addition, the present invention is not limited to covering only two dielectric layers, such as the dielectric layers 16, 18 covering the surface of the conductor pattern 14 and filling the conductive vias 12. If the dielectric layer 18 is cured, the recess value is still too large. The dielectric layer of the heavy lion and the dielectric layer 18 can be continued on the surface of the dielectric layer 18 according to the steps of laminating, curing, etc., and the surface flatness of the direct compensation layer is required. Then, as shown in Fig. 5, laser drilling is performed on the build-up insulating layer 17, and a plurality of blind holes are formed, read, and the surface of the riding and layer n is subjected to the de-counting and roughening process. Next, a conductive pattern (4) is formed on the build-up insulating layer 17, and the second layer may be a gold shot, such as a copper layer, or a material that is electrically conductive. The process of the present invention can be visually in accordance with the process of the aforementioned step edge layer to form a circuit board having a multilayer wiring. ▲ Color As described above, the present invention provides a circuit board process for improving the steps of flattening the surface of the substrate by using a filler material to fill the conductive via hole and then smoothing the surface of the substrate for the conventional technology. In the brushing process, excessive brushing or lack of dielectric material remains. Therefore, the present invention directly fills the conductive vias with the dielectric material as the build-up insulating layer, so that the filler used in the conventional process can be omitted and No subsequent brushing process is required. It not only simplifies the board process but also reduces the manufacturing cost of the board. ^ Furthermore, in the conventional technology, when the circuit board is added, the surface of the build-up insulating layer is often uneven, especially in the case of the build-up insulating layer located above the conductive via, which is the most serious. The invention provides an effective solution to improve the depression of the surface of the build-up insulating layer and increase the yield of subsequent fine lines. In addition, another feature of the present invention is that the first dielectric layer and the second dielectric layer are formed using a side dielectric material, which has the advantage of subsequently performing a laser drilling on the build-up insulating layer. The size is easier to control, and in addition, when roughening the insulating layer, the roughness uniformity of the surface and the hole is also easier to control. The above-mentioned average changes and modifications made by the invention in accordance with the scope of the present invention should be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Referring to Figures 1 through 5, there is shown a cross-sectional view of a preferred embodiment of the method of fabricating the panel of the present invention.
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