TWI374529B - Stacked die for battery power management - Google Patents

Stacked die for battery power management Download PDF

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Publication number
TWI374529B
TWI374529B TW097135477A TW97135477A TWI374529B TW I374529 B TWI374529 B TW I374529B TW 097135477 A TW097135477 A TW 097135477A TW 97135477 A TW97135477 A TW 97135477A TW I374529 B TWI374529 B TW I374529B
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TW
Taiwan
Prior art keywords
battery protection
mosfets
protection package
shared
package structure
Prior art date
Application number
TW097135477A
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English (en)
Other versions
TW200924146A (en
Inventor
Lu Jun
Chang Allen
Tian Zhang Xiao
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Alpha & Omega Semiconductor
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Publication of TW200924146A publication Critical patent/TW200924146A/zh
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Publication of TWI374529B publication Critical patent/TWI374529B/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H02J7/0031—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits using battery or load disconnect circuits
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Battery Mounting, Suspending (AREA)

Description

1374529 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種電·池防護元件’特別是指一種用於電池電源管理 的堆疊式晶粒封裝。 【先前技術】 用於可攜式電子裝置的一般電池組包含有數個裸露的電池、一電路 防護模組（PCM)，其内具有一防護電路，以控制裸露電池的充放電； 以及一終端線（terminalline)，其係用以電性連接裸露的電池至防護電 路間。此裸露的電池、PCM與終端線可以容設於一已經事先設定好的 殼體内。 電流管理系統與電池防護1C提供大量的電池過電壓與過電流防 護、電池預充電（pre-conditioning)與百分之一的充電準確度（one percent charger voltage accuracy)。電流管理系統與電池防護ic是設 置於一小體積的熱散逸導線架封裝結構中，其可以是一個小尺寸的表面 黏著元件（SMD)。 傳統的技術為了更進一步縮小電池防護整合電路（丨c)的尺寸，面， 臨了許多技術上的困難點與限制。傳統的電池防護1C 一般包含有一電 •源控制丨C與整合式雙共用汲極金屬氧化物半導體場效應電晶體 (MOSFETs) ’其是封裝於一導線架内並且封裝成如同2x5麵大小。 第1圖為先前技術中的電池防護丨C封裝結構的電路圖，而第i圖之電 池封裝結構的俯視圖係如第2圖所示。 如第1圖所示，一防護電路模組100可包含有一電源控制丨〇1〇2 .與雙共用汲極MOSFETs 1()6、伽，其係共同封裝於—封裝模組内。 在第1圖中，VCCS-輸入供應接腳，其可經由一電阻器連接至一電 池的陽極，此電池可以是雜子或者㈣分子電池。vss是指一接電 端，其可以連接至内部放電端M0SFET 106的源極S1與電池的陰極 端。VM是指一過充電與充電器電壓監控端。〇UTM是指一輸出端，其 5 1374529 可連接至内部充電端MOSFET 108的源極S2。DO與CO是指電源控 制丨C 102的接腳’其可各自連接放電端M〇SFET 1〇6與充電端, MOSFET 108的閘極。MOSFETs 106與108可以是雙共用汲極 MOSFETs，其係架構於單-半導體晶片上且具有相同的没極輝塾作為 汲極D1與D2，但是不同的源極與閘極銲墊。一電流限制電阻器％ 與一電容器C1構成一低通濾波器（丨ow pass mter)，以減少供應電壓 波動。電阻^ R2提供ESD防護與在反轉電流的事件巾作為電流限制。 電容器C1與兩個電阻器R1與町可以設置於封裝1〇〇的外部。接聊 VM與控制IC102的VCC可以電性連接至迴路模組1〇〇的vcc接腳。 _控制IC102的源極電壓輸入VSS可以連接至迴路模組1〇〇的vss接 腳。 ’ 電源控制器丨C 102可以設置於導線架晶粒銲墊112上並且整合雙 共用沒極MOSFETs 106與108，雙共職極M〇SFETs 1〇6與1〇8 可設置於另-晶粒銲墊104上。兩晶粒鮮墊1〇4與112可以是包含於 —導線架封裝内。第1 g中所示的迴路巾的電極與引線_連接可以由 打線來配置。為了減少打、線的寄生效應，導線架封裝的vss引線與VCC 引線可以設置於封裝__，但當封裝是裝設於—印刷電路板時，這 並不是-個較佳的接腳佈局。在這樣的先前技術封裝上，因為電源控制 丨c 102與雙共用及極MOSFETs 106與108是分設於兩個個別的晶粒 2墊’並且因為控制IC 1Q2需要-有限定的大小的晶粒銲塾112以裝 設，IC上，晶粒銲墊104為容設雙共同汲極m〇sfeTs 1〇6與1〇8最 可能的最大尺寸所使用的尺寸是更進—步_ 了導線架封裝的佔地面 f大小’其可能更導致雙共同錄MOSFETs的啟動電阻。現有的導 線架封裝的尺寸一般是2 πΐβΐχ5臟。 _㈣封裝（batterypiOtection package)的最佳性能一般是利 用，大可能的M0SFET晶粒尺寸來達成，以減少汲極至源極的啟動電 阻Rds^on)。然而，電源控制丨C 1〇2也佔用導線架的空間，其限制了， 6 1374529 motets 106㈣8的空間使用率。只有相對小尺寸m〇sfets，一 般是具有-最大·極至雜電阻，大約是48__Ω，其包含有打線 至MOSFETs的電阻’趨向於安裝在_個2χ5 _導線架封裝。這樣減 乂在相同尺寸下電源管理器封裝結構的效率。假如是設定較低啟動電 阻’那需要具有較佳較大佔地面積_裝以符合這個需求。 有鑑於此’本發明遂針對上述習知技術之缺失，提出一種用於電池 電源（power)管理的堆疊式晶粒封裝，以有效克服上述之該等問題。 【發明内容】
本發Θ之主要目的在&供—種用於電池電源（pGwe「）管理的堆疊 式晶粒封裝，級用_或較顿封裝來整合雙共肢極m〇sfets 成為具有較大尺寸與較小Rds^n的理想封裝結構。 本發>^之：^目的在&供—種用於電池電源（p〇we「）管理的堆疊 式晶粒封裝’其產生具有封裝厚度較_理想封裝。 本發3之^目的在提供—種用於電池電源（ρ〇_「）管理的堆疊 式bb粒封裝其將VSS與VCC接則丨導至封裝的相同側端，達到較 的應用虚3?。 < 底下藉由具體實酬詳加制，#更容純解本發明之目的 内容、特點及其所達成之功效。 【實施方式】 雖然下列的洋細說明包含有許多特殊細節，以供描述本發明之目 的，但熟知該項技術者當知可依據下列的詳細說明加以許多變化、潤飾， ，修改來實施’但這仍不能麟本㈣之精摘在。依據本發明下列所 提出的具體實蘭僅是概括的描述，並*能作為請求項的限制。 本發明的具體實編列提供一種較佳，吐能的電池防護封裝結構 (battery pr〇tecti〇n package arrangement)、較小的外型因素^佳 的接腳排列（pin_QUt)方式。在本發明之具體實 c、 堆昼於整合式狀酿極_ETS _料μ/兩== 1374529 MOSFETs上，並且單一晶粒銲塾可用以貼設所有結構的m〇SFETs。 第2A圖是電池防護封裝的俯視圖，其包含有整合式雙共用沒極 MOSFETs ’其在本發明的具體實補巾是指則目侧尺寸且近似的 MOSFETs ’並且在底面共享同一個汲極銲整。如同第2A圖所示，由 單一半導體晶片所組構之雙共用汲極M〇SFETs 2〇6與2〇8可具有相 同源極與閘極尺寸，且貼設於晶粒銲塾2QQ j^雙的源極 ，閘極佈局可以是對稱地沿著M0SFETs的中心線4源控制丨c 2〇2 疋堆疊於雙MOSFETs 206與208的頂面上並且疊設於M〇SFETs 206 與208的兩源極區域部分，但並非閘極區域。在這個具體實施例中， 馨VCC與VSS引線疋在電池防護封裝結構的右側。電壓監控器vm與電 源控制IC 202的供應電壓VCC的輸入銲墊可以透過打線212與213 各自電性連接至封裝的VM與VCC引線。電源控制丨〇2〇2的輸出C〇 與DO銲塾是各自利用打線214與215電性連接至MOSFETs 206與 208的閘極銲墊G1與G2。電源控制丨C 202的VSS銲墊是透過打線 216電性連接至MOSFETs 208的頂面源極銲墊S2。MOSFET 206的 源極銲墊S1與MOSFET 208的頂面源極銲墊S2可以透過數個打線 210與222電性連接至溶接的輸出模態（〇υτΜ)引線與溶接的VSS 引線220。此外，打線210彼此間的距離與打線222彼此間的距離是 鲁沒有連累的（compromised)，藉此提供較低的電阻。打線是利用適當 的金屬材質所製做，舉例來說如金、鋼或者是銘，但是並不侷限於此。 反之，雙MOSFETs 206與208的源極銲墊S1與S2可各自透過鋁帶 (aluminum ribbons) 211與209電性連接至熔接的〇UTM引線218 與熔接的VSS引線220，如第2C圖所示。電源控制IC202上的銲墊' • 位置與雙MOSFETS206與208的可不同於第2A-2C圖所示。 經由具體實施例，整合式雙共同汲極MOSFETs 206與208可以 是美國加州（California)的 Alpha and Omega Semlcoductor of Sunnyvale 的 AOSN651、DN652S 或者 DN653S 的模組。控制 ic 202 8 1374529 可以是日本 Chiba 的 Seiko Instruments Inc 的模組 S-8211CAA-WAP3 或者8211BAB-WAP3電池防護IC或者是日本Osaks的Ricoh Co丄td 的 R5407W124CC-S2 模組。 晶粒採兩個彼此堆疊會有一個不好的效應就是增加了封裝厚度，將 導致限制應用的範圍或者甚至產生元件無法使用的結果。為了減少疊置 的封裝厚度’可使用厚度小於標準8哩（mils)較薄的晶粒。最佳作為 IC 102的晶粒厚度與雙共用汲極MOSFETs晶粒207是小於6哩 (mils)。MOSFET晶粒207所減少的厚度更減少了雙共用汲極 MOSFETs 106與108啟動時的電阻。為了完全利用薄晶粒的優點，厚’ • 度為2哩的超薄晶粒也可用於IC 102與MOSFET晶粒207兩者。產 生超薄晶粒的技術範例是揭示於申請日為2007年2月28號申請的美 國專利11/712846 ; 2007年3月30號申請的美國專利11/694888與 2007年7月2〇號申請的美國專利11/880455，其係皆讓渡給相同的 受讓人且列為前技術的參考資料。 第2B圖係第2A圖之電池防護封裝沿著B-B線的剖面示意圖。如 同第2B圖所示，電源控制丨〇2〇2是堆疊於雙MOSFETs 206與208 的頂面，因此電源控制IC疊置於雙MOSFETS206與208的兩個源極， 區域。雙共用汲極MOSFETs 106與108的3-5微米厚度鋁材的閘極 鲁金屬銲墊與源極金屬銲墊可以設置於MOSFETs 106與108的頂表 面。雙共用没極MOSFETs 106與108之由鈦鎳銀金屬所構成的1〜3 微米厚度的汲極金屬銲墊是設置於MOSFETs 106與108的底表面 上° 一絕緣黏著層203 ’例如非導電樹脂層，是形成於電源控制ic 2〇2 與雙共用汲極MOSFETs 206與208間。此絕緣黏著層203不僅提供 IC與MOSFETs間的機械接合力，但也扮演電性絕緣緩衝層，因為丨c 202與MOSFETs 206、208間存在著電位能差，因此若沒有適當絕緣，， 將導致元件不正常運作。 傳統的樹脂配方與依附於lC封裝内的晶粒無法提供MOSFETs 9 1374529 206、208與IC202足夠的絕緣》為了確保適當的絕緣，可依照特殊的 步驟來形成高品質的絕緣層203。在一具體實施例中，一非導電膠，例· 如由 California 的 Rancho Dominguez 的 Abelstik Labortories 所製之 Ablesbond 8006NS或者Ablecoat 8008NC ’是塗佈在1C晶圓的背面， 此塗佈在1C晶圓背面的樹脂隨後在烤箱内進行半硬化。背面塗佈有半 硬化樹脂之丨C隨後被切成小塊並且在高溫下貼附於M0SFET上，隨 後完全固化。在另一具體實施例中，在丨C晶粒塗上第一樹脂前，一第 二非導電樹脂施加於M0SFET頂表面上。在另一具體實施例中，雙共 用汲極M0SFET晶粒更包含有一純化層形成於源極的頂上，以進一步 φ 絕緣。 整合的雙共用没極MOSFETs 206與208是相依付的並且 MOSFETs 206與208的共用没極銲墊是透過導電接合媒介2〇1電性 連接至導線價晶粒銲墊200,此導電接合媒介可以是軟焊、導電膠與其 它導電黏著劑。因為額外的絕緣防護材料，所以整合式共用及極 MOSFETs的源極區域的一部分是正位於電源ic 202的底下，但些微 地大於IC 202的佔地面積，IC 202可能塗佈有額外的鈍化層（_中未 示）’例如氮化梦，因此MOSFETS206與208的源極區域與IC 202界 面的部分是完全被鈍化層所覆蓋。 鲁 第2D圖是本發明之另一種電池防護封裝結構的俯視示意圖。第2D· 圖的電池防護封裝基本上是與第2A圖相似，除了 VCC與VSS引線是 在電池防護封裝的左側。在這個具體實施例中，M0SFET 206的源極 銲墊S1是電性連接至VSS引線220，M0SFET 208的源極銲塾S2 是連接至0UTM引線218。第2E〜2F圖另一種電池防護封裝結構的 俯視圖，其具有整合式雙共用汲極MOSFETs 217與219，此整合式雙 共用沒極MOSFETs 217與219是在一半導體晶片上且尺寸相異。在 這個實施例中，第一 M0SFET 217是小於第二M0SFET 219。在第
2E〜2F圖中’ VCC與VSS引線是在電池防護封裝的右側。在第2E 10 1374529 圖中，一電源IC202是僅堆疊在第：MOSFET219上，在這樣的方式 下，電源IC 202的長側是平行於第二M0SFET 219的短側。在第 圖中，電源控制器IC 202是僅堆疊於第二MOSFET 219上，在這樣的 方式下，電源IC202的長側是垂直於第二M〇SFET 219的短側。電源 控制丨C的VM與VCC銲墊是透過打線2彳2與213各自電性連接至VM 與VCC引線。電源控制丨C 202的輸出CO與DO是透過打線214與 215各自電性連接至m〇SFETs217與219的閘極銲墊G1與G2»電 源控制丨C 202的VSS銲墊是透過打線2彳6電性連接至第二MOSFET 219的頂面源極銲墊S2。第一 MOSFET 217的源極銲墊S1與第二 # M0SFET 219的頂面源極銲墊S2是透過打線21〇與222各自電性連 接至OUTM引線218與VSS引線220。 第2G-2H圖是另一種具有相異尺寸之整合式雙共用汲極 MOSFETs的電池防護封裝結構俯視圖。在這些實施例中，vcc與vss 引線是位於電池防護封裝的左側。第一 M〇SFET 221是大於第二 MOSFET。在第2G圖中，電源控制丨C2〇2是僅堆疊於第一 m〇sfet 221上，在這樣的方式下，電源控制丨c 2〇2的長側是平行於第一 MOSFET 221的短侧。在第2H圖中，電源控制ic 202是僅堆疊於第 一 MOSFET221上’在這樣的方式下，電源控制丨〇2〇2的長側是垂直 •於第一 MOSFET 221的長側。電源控制IC2〇2的VM與^/〇〇是透過 打線212與213各自電性連接至VM與VCC。電源控制丨C 202的輸 出DO與CO銲墊是透過打線214與215各自電性連接至MOSFETs 221與223的閘極銲墊G1與G2。電源控制|C 202的VSS銲墊是透 過打線216電性連接至第一 MOSFET 221的源極銲墊$1。第一 MOSFET 221的源極銲墊S1與MOSFET 223的頂面源極銲墊S2是 透過打線222與210各自電性連接至vss引線220與0UTM引線218。 第3A圖是本發明之一具體實施例之包含有兩個等尺寸且分離不連 續之MOSFETs的電池防護封裝結構俯視圖。如同第3A圖所示，兩個 1374529 等尺寸且不連接的MOSFETs 306與308是以一間距d而肩並肩設置 於導線架晶粒鋅墊300上。電源控制丨C 302是堆疊且疊置於MOSFETs 306與308兩者頂面上。在這個具體實施例中，vcc與vss引線是位 於電池防護封裝的右側。電源控制丨C3〇2的乂!^與vcc銲墊是透過打 線312與313各自電性連接至VM與VCC引線。電源控制1C 302的 輸出CO與DO銲塾是透過打線314與315各自電性連接至MOSFETs, 306的閘極銲墊G1與G2 〇電源控制丨c 302的VSS銲墊是透過打線 316電性連接至MOSFET 308的頂面源極銲墊S2。MOSFET 306的 源極銲墊S1與MOSFET 308的頂面源極銲墊S2是透過打線310與. # 322各自電性連接至OUTM引線318與VSS引線320。 第3B圖是第3A圖之電池防護封裝沿著c-c截面的剖視圖。如同 第3B圖所示’不連續的MOSFETs 306與308以一間距d肩並肩設置》 在這個具體實施例中，電源控制IC 302是透過一絕緣黏著層301堆疊. 且疊置於MOSFETs 306與308兩者的頂面。兩MOSFETs 306與308 的/及極324與326是透過導電膠或者錫銲層3〇3依附且電性連接至導 線架晶粒焊塾300。 第3C圖係依據本發明之另一電池防護封裝結構的俯視圖。第3D 圖係本發明之電池封裝結構具體實施例的剖視示意圖。第3C至第3D 泰圖的電池防護封裝基本上是與第3A-3B圖相似，除了 VCC與VSS引 線疋位於電池防護封裝的左側上。在這個具體實施例中，m〇SFET3〇6 的源極銲塾si是電性連接至VSS 5丨線32G，而M〇SFET3⑽的祕 銲墊S2是連接至OUTM引線318。電源控制丨〇302的vss銲墊是電 性連接至MOSFET 306的源極銲墊S1。 第3E〜3F圖是具有兩個不連續且不同尺寸之M〇SFETs以間距 d1肩並肩設置的電池防護封裝結構示意圖。—般來說，第二M〇SFE丁 3JI9是大於第一 MOSFET 317。在第3E〜3F圖中VCC與VSS引線 是位於電池防護封裝的右侧。如同第3E圖所示，電源控制|C 3〇2是 1374529 僅堆疊於MOSFET 319上，在這樣的方式下，電源控制丨c 3〇2的長侧 平行於MOSFET 319的長側。在第3F圖中，電源控制丨c 3〇2是僅堆 疊於MOSFET 319上，以這樣的方式下’電源控制3〇2的長側是垂 直於MOSFET 319的長侧。電源控制lc 3〇2的VM與vcc鲜塾透過 打線312與313各自電性連接至VM與VCC引線。電源控制丨c 3〇2 的輸出C0與DO銲塾是透過打線314與315各自電性連接至 MOSFETs 317與319的閘極銲墊G彳與G2。電源控制丨c 3〇2的vss 鲜塾是透過打線316電性連接至MOSFET 319的頂面源極銲塾S2。 MOSFET 317的源極銲塾S1與M0SFET 319的頂面源極料沒是， •透過數個打線3彳〇與322各自電性連接至0UTM引線Mg與vss 線 320。 ' 第3G〜3H圖是另一種具有兩個不連續且不同尺寸之m〇sfeTs 以間距d1肩並肩設置的電池防護封裝結構示意圖。在這個實施例中， VCC與VSS引線是設置在這個電池防護封裝的左侧。一一 MOSFET 321是大於第二M0SFET 323。在第3G圖中，電游控制|c 302是僅堆疊於第- M0SFET 312上，在這樣的方式下，電源控制|c 302的長側平行於第一 MOSFET 321的長侧。在第3H圖中，電源控， 制IC 302是僅堆疊於第-M0SFET321上，以這樣的方式下電源控 鲁制IC302的長側是垂直於第一 MOSFET321的長侧。電源控制|〇3〇2 的VM與VCC銲墊透過打線312與313各自電性連接至VM與vcc 引線。電源控制IC302的輸出CO與DO銲塾是透過打線314與315 各自電性連接至MOSFETs 321與323的閘極銲墊G1與G2 ^電源控 制IC 302的VSS銲墊是透過打線316電性連接至第一 M0SFET321 的頂面源極銲墊S1。第一 MOSFET 321的源極銲墊S1與第二 MOSFET 323的頂面源極銲墊S2是透過數個打線322與31〇各自電 性連接至VSS引線320與0UTM引線318。 上述係本發明之較佳具體實施例的完整描述，但仍是可以有許多變 13 1374⑽ 為判= 。因此，本發明之精神應當無法僅以上述描述作 ，而是應該以中請專利範園作為判斷。更者，無論是否為較 皆可結合其它特徵4下列專咐請範肋，”―”係指項目是 二^上的量除非有特別指出其它含意。附加的請求項並不包含有 j性的限制，除非這樣的限制是明白地詳述於使用”麵 的特定請求項。 唯以上所述者’僅為本發明之較佳實施條已，並非聽限定本發 明實施之範®。_驗本發g种純目所软概及精神所為之均等 變化或修飾，均應包括於本發明之申請專利範圍内。
【圖式簡單說明】 第1圖係習知技術之電池防護封裝的電路示意圖。 第2A圖係一電池防護結構的俯視圖，此電池防護結構具有相同尺寸之 整合式雙共舰極MOSFETs，且VCC與VSS位於此電池防護封裝的 右側。 第2B圖係沿著第2A圖之電池防護封裝之b-B截面的剖面示意圖。 第2C圖另一種電池防護封裝結構的俯視圖。 第2D圖係一電池防護結構的俯視圖，此電池防護結構具有相同尺寸之 整合式雙共用汲極MOSFETs，且VCC與VSS位於此電池防護封裝的 # 左側。 第2E-2F圖係一電池防護結構的俯視圖，此電池防護結構具有相異尺 寸之整合式雙共用汲極MOSFETs，且VCC與VSS位於此電池防護封 裝的右側。 第2G-2H圖係一電池防護結構的俯視圖，此電池防護結構具有相異尺 寸之整合式雙共用汲極MOSFETs，且VCC與VSS位於此電池防護封 裝的左側。 第3A圖係一電池防護結構的俯視圖，此電池防護結構具有兩個相同尺 寸之分離式共用汲極MOSFETs，且VCC與VSS位於此電池防護封裝. 1374529 的右側。 第3Β圖係沿著第3Α圖之電池防護封裝之d-D截面的剖面示意圓。 第3C圖係一電池防護結構的俯視圖，此電池防護結構具有兩個相同尺 寸之分離式共用汲極MOSFETs，且VCC與VSS位於此電池防護封裝 的左側® 第3D圖係沿著第3C圖之電池防護封裝之e-E截面的剖面示意圖。 第3E-3F圖係一電池防護結構的俯視圖，此電池防護結構具有兩個相 異尺寸之分離式共用汲極MOSFETs，且VCC與VSS位於此電池防護 封裝的右側。 φ 第3G-3H圖係一電池防護結構的俯視圖，此電池防護結構具有兩個相 異尺寸之分離式共用汲極MOSFETs，且VCC與VSS位於此電池防護 封裝的左側。 【主要元件符號說明】 100防護電路模組 102電源控制IC _ 104晶粒銲墊 106 M0SFET 108 M0SFET 籲112晶粒銲墊 200晶粒銲墊 201導電接合媒介 202電源控制IC 203絕緣黏著層
206 M0SFET 207 M0SFET 晶粒 208 M0SFET 209鋁帶 15 1374529 210打線 211鋁帶 212打線 213打線 214打線 215打線 216打線
217 MOSFET
218 0UTM 引線 φ 219 MOSFET 220 VSS引線
221 MOSFET 222打線 223 MOSFET
300導線架晶粒銲墊 301絕緣黏著層 302電源控制丨C 303錫銲層 • 306 MOSFET
308 MOSFET 310打線 312打線 313打線 314打線 315打線 316打線 317 MOSFET 1374529 318 0UTM 引線
319 MOSFET 320 VSS引線 321 MOSFET 322打線 323 MOSFET 324汲極 326汲極

Claims (1)

  1. 十、申請專利範圍： I·—種電池防護封裝結構，其包含有： —導線架； —电源控制整合式迴路（ic); 第金屬氧化物半導體場效應電晶體 S ) ^、係％性連接至該電源控制IC，· 其中該電源㈣li IC與該第―料二共舰 =體(M0SFETS)是共同封細導練架之一共二:
    八属二中原控制ic是直立式堆疊於該第—與第二共用沒極 至屬乳化物半導體場效應電晶體（MOSFETs)的兩者頂面上，因 此錢源控制ic疊置於該第—與第二共贿極M〇sFETs的兩者 上其中連接至遠電源控制的-供應電壓輸入（vcc)與一 接地（VSS)的引線是位於該共用晶粒銲塾的一第一側上，而該 連接至該電池防護封裝結構之輸出（〇UTM)與該電源控制K之 电壓&控（VM)接腳的引線是位於該共用晶粒銲墊的—第二 側，其係相對於該第一側。 —
    101年3月23日修正替換頁 2，如申請專利範圍第]項所述之電池防護封裝結構，其中該第—與 二MOSFETs是雙共用及極M〇SFETs，其在單一半導體晶片中呈 分開的源極舆汲極，但是共享—共用的汲極。 ” 3. 如申請專利範圍第1項所述之電池防護封裝結構，其中該第—與第 -共用/及極MOSFETs是相同源極與閘極尺寸且是沿著該雙共用及 極MOSFETs的中心線對稱。 4. 如申請專利範圍第1項所述之電池防護封裝結構，其中連接至該電 源控制ic的該供應電壓輪入（vcc)與該接地（vss)的引線是位 於該共用晶粒銲墊的-左側上，而該連接至該電池防護封裝結構之 該輸出（0UTM)與該電源控制丨c之該電整監控（VM)接腳的弓丨 線是位於該共用晶粒銲墊的一右側。 18 1374529 5. 6. 如申請專概目帛丨項所狀電細制裝換頁 沒極廳SFET的源極雜是雜連接 ς 共用 輸出OUTM。 4池防瘦封裝結構的該 如申請專利範圍第5項所述之電池防護封 =^ΕΤ_ 麵蝴峨
    如申請專利範圍第6項所述之電池防護封敦 I】的輸出端是電性連接至該第-與第二共用及極贿 與第二閘極銲墊（G)。 巧弟 如申請專利範圍第2項所述之電池防護封裝結構，其中該第_ /及極MOSFET在尺寸上是小於該第二共用沒極M〇SFETs。 9·如申/t專利範圍第8項所述之電池防護封裝結構，其中該電源控制 ic是直立式封裝於該第二共用汲極1^〇8]?£丁的頂面上。 瓜如申請專纖圍第9項所述之電池防護封裝結構，其中該電源控制 1C的一長側是平行於該第二共用汲極m〇SfE丁的一長側。 11.如申请專利範圍帛10項所述之電池防護封裝結構，其中該電源控制 1C的一長側是與該第二共用汲極MOSFET的一長側成直角。 丨2.如申明專利範圍第丨項所述之電池防護封裝結構，其中該第一與第-共用汲極MOSFETs是採肩並肩方式嵌設，且該第-與第二共用 汲極MOSFETs間具有一間距。 8. 13. 如申請專利範圍第12項所述之電池防護封裝結構，其中該第一與第 二共用汲極MOSFETs是相同尺寸。 14. 如申請專利範圍第]2項所述之電池防護封裝結構，其中該電源控制 ic是直立式堆疊於該第—與第二共用汲極M〇SFETs兩者的頂面 上’因此該電源控制丨C疊置於該第一與第二共用汲極MOSFETs兩 者。 15. 如申請專利範圍第丨2項所述之電池防護封裝結構，其中該第一共用 19 101年3月23曰修正替 ，及極M〇SFEJ的尺寸是小於該第二共用汲極丄sL 第1述之電池防護封裝結構，其中該電源、控制 疋式隹®於該第二共用沒極MOSFET的頂面。 專繼_16項賴之電祕護職、 1S IC的—長側是平行於料二如祕MGSFET的—長側私制 範圍第16項所述之電池防護雖結構’其 匚的:長側係與該第二共_iMQSFET的，_ t專纖_16項所述之電池防護域結構，其中-正施Μ =cc與負施加電墨vss是在該共用晶轉塾的一右側， % 與—調變輸出文 〇·—種電池防護封裝結構，其包含有： 側 —晶粒銲塾； 電源控制整合迴路（ic); έέ _ --偽马 a ____ . 二 、用汲極金屬氧化物半導體場效應電曰辦 ic是係共同封裝於該晶粒鲜塾上’其中該電源了空制 置tiri )的兩者頂面上，因此該電源控制lc疊 Λ弟 沒極M0SFETS的兩者上，其中連接至节 ii；" (vcc) (vss) 裝社構上，而該連接至該電池防護封 裝、..。構之輸出（〇υτΜ)與該電源 !:的”線是位於該共用晶粒的-第二上= 20
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US20090128968A1 (en) 2009-05-21
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