TWI373918B - - Google Patents

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Publication number
TWI373918B
TWI373918B TW97145445A TW97145445A TWI373918B TW I373918 B TWI373918 B TW I373918B TW 97145445 A TW97145445 A TW 97145445A TW 97145445 A TW97145445 A TW 97145445A TW I373918 B TWI373918 B TW I373918B
Authority
TW
Taiwan
Prior art keywords
state
clock signal
phase
locked loop
control signal
Prior art date
Application number
TW97145445A
Other languages
English (en)
Chinese (zh)
Other versions
TW201021425A (en
Inventor
Ching Tsung Tung
Chuen An Lin
Original Assignee
Holtek Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Holtek Semiconductor Inc filed Critical Holtek Semiconductor Inc
Priority to TW97145445A priority Critical patent/TW201021425A/zh
Publication of TW201021425A publication Critical patent/TW201021425A/zh
Application granted granted Critical
Publication of TWI373918B publication Critical patent/TWI373918B/zh

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  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
TW97145445A 2008-11-25 2008-11-25 Digital phase-locked loop (PLL) state architecture for receiving and recovering universal serial bus (USB) clock TW201021425A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW97145445A TW201021425A (en) 2008-11-25 2008-11-25 Digital phase-locked loop (PLL) state architecture for receiving and recovering universal serial bus (USB) clock

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW97145445A TW201021425A (en) 2008-11-25 2008-11-25 Digital phase-locked loop (PLL) state architecture for receiving and recovering universal serial bus (USB) clock

Publications (2)

Publication Number Publication Date
TW201021425A TW201021425A (en) 2010-06-01
TWI373918B true TWI373918B (https=) 2012-10-01

Family

ID=44832630

Family Applications (1)

Application Number Title Priority Date Filing Date
TW97145445A TW201021425A (en) 2008-11-25 2008-11-25 Digital phase-locked loop (PLL) state architecture for receiving and recovering universal serial bus (USB) clock

Country Status (1)

Country Link
TW (1) TW201021425A (https=)

Also Published As

Publication number Publication date
TW201021425A (en) 2010-06-01

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MM4A Annulment or lapse of patent due to non-payment of fees