TW201021425A - Digital phase-locked loop (PLL) state architecture for receiving and recovering universal serial bus (USB) clock - Google Patents
Digital phase-locked loop (PLL) state architecture for receiving and recovering universal serial bus (USB) clock Download PDFInfo
- Publication number
- TW201021425A TW201021425A TW97145445A TW97145445A TW201021425A TW 201021425 A TW201021425 A TW 201021425A TW 97145445 A TW97145445 A TW 97145445A TW 97145445 A TW97145445 A TW 97145445A TW 201021425 A TW201021425 A TW 201021425A
- Authority
- TW
- Taiwan
- Prior art keywords
- state
- clock
- signal
- clock signal
- phase
- Prior art date
Links
- 230000005540 biological transmission Effects 0.000 claims abstract description 18
- 230000007246 mechanism Effects 0.000 claims description 14
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 230000007704 transition Effects 0.000 claims description 5
- 230000001360 synchronised effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 23
- 230000008859 change Effects 0.000 description 18
- 238000007796 conventional method Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012552 review Methods 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW97145445A TW201021425A (en) | 2008-11-25 | 2008-11-25 | Digital phase-locked loop (PLL) state architecture for receiving and recovering universal serial bus (USB) clock |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW97145445A TW201021425A (en) | 2008-11-25 | 2008-11-25 | Digital phase-locked loop (PLL) state architecture for receiving and recovering universal serial bus (USB) clock |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201021425A true TW201021425A (en) | 2010-06-01 |
| TWI373918B TWI373918B (https=) | 2012-10-01 |
Family
ID=44832630
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW97145445A TW201021425A (en) | 2008-11-25 | 2008-11-25 | Digital phase-locked loop (PLL) state architecture for receiving and recovering universal serial bus (USB) clock |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TW201021425A (https=) |
-
2008
- 2008-11-25 TW TW97145445A patent/TW201021425A/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| TWI373918B (https=) | 2012-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5933899B2 (ja) | プログラマブルロジックデバイス回路に結合されるクロックデータリカバリ回路 | |
| US8363773B2 (en) | Digital phase interpolation control for clock and data recovery circuit | |
| US6260152B1 (en) | Method and apparatus for synchronizing data transfers in a logic circuit having plural clock domains | |
| TWI410791B (zh) | 用以傳送及接收複數個資料位元的裝置與方法 | |
| US7684531B2 (en) | Data recovery method and data recovery circuit | |
| TW201342804A (zh) | 用於平衡高速串列數位介面之信道之間的偏斜之方案 | |
| JPH10117185A (ja) | データを転送するためのシンクロナイザ、方法及びシステム | |
| CN113765514B (zh) | 具有可选择的源端延迟和目的地端延迟控制的源同步接口 | |
| CN113300799B (zh) | 适用于jesd204b协议的时钟同步方法、电路及逻辑设备 | |
| JP2005506798A (ja) | 遷移検出、妥当正確認および記憶回路 | |
| US8588341B2 (en) | Data transfer circuit and data transfer method for clock domain crossing | |
| US7696801B2 (en) | Reset method for clock triggering digital circuit and related signal generating apparatus utilizing the reset method | |
| Mekie et al. | Interface design for rationally clocked GALS systems | |
| TW201021425A (en) | Digital phase-locked loop (PLL) state architecture for receiving and recovering universal serial bus (USB) clock | |
| CN101751357B (zh) | 一种数字锁相回路装置 | |
| US6920578B1 (en) | Method and apparatus for transferring data between a slower clock domain and a faster clock domain in which one of the clock domains is bandwidth limited | |
| JPH11331137A (ja) | 信号同期装置 | |
| JP2010283816A (ja) | クロックを並列データに整列させるための回路 | |
| JPH0946326A (ja) | 位相同期装置、デコーダ及び半導体集積回路装置 | |
| JPH1168861A (ja) | 同時双方向送受信方法および同時双方向送受信回路 | |
| US20060198479A1 (en) | Data synchronizer system | |
| US7466783B2 (en) | Method and system to implement a double data rate (DDR) interface | |
| CN115956341A (zh) | 用于同步模数转换器或数模转换器的方法以及对应的系统 | |
| JPH03149930A (ja) | ビット位相同期回路 | |
| JPH0795188A (ja) | 非同期ディジタル通信方法および装置 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |