TWI369685B - Method of testing a non-volatile memory device - Google Patents

Method of testing a non-volatile memory device

Info

Publication number
TWI369685B
TWI369685B TW097120666A TW97120666A TWI369685B TW I369685 B TWI369685 B TW I369685B TW 097120666 A TW097120666 A TW 097120666A TW 97120666 A TW97120666 A TW 97120666A TW I369685 B TWI369685 B TW I369685B
Authority
TW
Taiwan
Prior art keywords
testing
memory device
volatile memory
volatile
memory
Prior art date
Application number
TW097120666A
Other languages
English (en)
Other versions
TW200939227A (en
Inventor
Jae Won Cha
Duck Ju Kim
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200939227A publication Critical patent/TW200939227A/zh
Application granted granted Critical
Publication of TWI369685B publication Critical patent/TWI369685B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50004—Marginal testing, e.g. race, voltage or current testing of threshold voltage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
TW097120666A 2008-03-14 2008-06-04 Method of testing a non-volatile memory device TWI369685B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080023838A KR100938045B1 (ko) 2008-03-14 2008-03-14 불휘발성 메모리 소자의 테스트 방법

Publications (2)

Publication Number Publication Date
TW200939227A TW200939227A (en) 2009-09-16
TWI369685B true TWI369685B (en) 2012-08-01

Family

ID=40983777

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097120666A TWI369685B (en) 2008-03-14 2008-06-04 Method of testing a non-volatile memory device

Country Status (6)

Country Link
US (1) US7697341B2 (zh)
JP (1) JP2009224011A (zh)
KR (1) KR100938045B1 (zh)
CN (1) CN101533673B (zh)
DE (1) DE102008002237B4 (zh)
TW (1) TWI369685B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100933838B1 (ko) * 2008-03-10 2009-12-24 주식회사 하이닉스반도체 불휘발성 메모리 소자의 테스트 방법
KR101069013B1 (ko) * 2010-07-09 2011-09-29 주식회사 하이닉스반도체 반도체 메모리 장치 및 그의 동작 방법
US8482987B2 (en) 2010-09-02 2013-07-09 Macronix International Co., Ltd. Method and apparatus for the erase suspend operation
KR101162000B1 (ko) * 2010-12-30 2012-07-03 에스케이하이닉스 주식회사 반도체 메모리 장치 및 이의 동작 방법
CN102610280B (zh) * 2011-01-20 2015-05-27 北京兆易创新科技股份有限公司 修复存储芯片的方法和装置、存储芯片
KR101184803B1 (ko) * 2011-06-09 2012-09-20 에스케이하이닉스 주식회사 반도체 장치 및 이의 프로그램 방법
CN102890971B (zh) * 2012-10-22 2016-08-03 上海华虹宏力半导体制造有限公司 存储器的可靠性测试方法
US10825529B2 (en) 2014-08-08 2020-11-03 Macronix International Co., Ltd. Low latency memory erase suspend operation
CN105989899B (zh) * 2015-03-05 2019-04-02 旺宏电子股份有限公司 存储器修补方法及其应用元件
US11522724B2 (en) * 2017-12-11 2022-12-06 International Business Machines Corporation SRAM as random number generator
CN108683423B (zh) * 2018-05-16 2022-04-19 广东工业大学 一种多级闪存信道下的ldpc码动态串行调度译码算法及装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3859912B2 (ja) * 1999-09-08 2006-12-20 株式会社東芝 不揮発性半導体記憶装置
KR100437461B1 (ko) 2002-01-12 2004-06-23 삼성전자주식회사 낸드 플래시 메모리 장치 및 그것의 소거, 프로그램,그리고 카피백 프로그램 방법
CN100365787C (zh) * 2003-07-29 2008-01-30 华为技术有限公司 支持写缓冲的flash内部单元测试方法
KR100642911B1 (ko) * 2004-11-30 2006-11-08 주식회사 하이닉스반도체 페이지 버퍼 및 이를 이용한 플래쉬 메모리 소자의 검증방법
US7430138B2 (en) * 2005-03-31 2008-09-30 Sandisk Corporation Erasing non-volatile memory utilizing changing word line conditions to compensate for slower erasing memory cells

Also Published As

Publication number Publication date
CN101533673A (zh) 2009-09-16
CN101533673B (zh) 2012-07-04
US20090231927A1 (en) 2009-09-17
KR100938045B1 (ko) 2010-01-21
US7697341B2 (en) 2010-04-13
DE102008002237A1 (de) 2009-09-24
JP2009224011A (ja) 2009-10-01
DE102008002237B4 (de) 2012-04-05
TW200939227A (en) 2009-09-16
KR20090098438A (ko) 2009-09-17

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