TWI345710B - Prefetch control in a data processing system - Google Patents

Prefetch control in a data processing system Download PDF

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Publication number
TWI345710B
TWI345710B TW093112996A TW93112996A TWI345710B TW I345710 B TWI345710 B TW I345710B TW 093112996 A TW093112996 A TW 093112996A TW 93112996 A TW93112996 A TW 93112996A TW I345710 B TWI345710 B TW I345710B
Authority
TW
Taiwan
Prior art keywords
access
pickup
control
master
interconnect
Prior art date
Application number
TW093112996A
Other languages
English (en)
Chinese (zh)
Other versions
TW200517856A (en
Inventor
William C Moyer
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW200517856A publication Critical patent/TW200517856A/zh
Application granted granted Critical
Publication of TWI345710B publication Critical patent/TWI345710B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6026—Prefetching based on access pattern detection, e.g. stride based prefetch
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
TW093112996A 2003-05-07 2004-05-07 Prefetch control in a data processing system TWI345710B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/431,285 US6871246B2 (en) 2003-05-07 2003-05-07 Prefetch control in a data processing system

Publications (2)

Publication Number Publication Date
TW200517856A TW200517856A (en) 2005-06-01
TWI345710B true TWI345710B (en) 2011-07-21

Family

ID=33416427

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093112996A TWI345710B (en) 2003-05-07 2004-05-07 Prefetch control in a data processing system

Country Status (7)

Country Link
US (1) US6871246B2 (https=)
EP (1) EP1623329A4 (https=)
JP (1) JP2007500402A (https=)
KR (1) KR20060009307A (https=)
CN (1) CN100435122C (https=)
TW (1) TWI345710B (https=)
WO (1) WO2004102402A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI607316B (zh) * 2013-03-15 2017-12-01 美商谷歌有限責任公司 高效率輸入輸出操作

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US7181556B2 (en) * 2003-12-23 2007-02-20 Arm Limited Transaction request servicing mechanism
US7328312B2 (en) 2005-02-03 2008-02-05 International Business Machines Corporation Method and bus prefetching mechanism for implementing enhanced buffer control
JP2006251923A (ja) * 2005-03-08 2006-09-21 Oki Electric Ind Co Ltd 先読み制御方法
US9304773B2 (en) * 2006-03-21 2016-04-05 Freescale Semiconductor, Inc. Data processor having dynamic control of instruction prefetch buffer depth and method therefor
US9652413B2 (en) 2009-07-20 2017-05-16 Nxp Usa, Inc. Signal processing system and integrated circuit comprising a prefetch module and method therefor
US8307164B2 (en) 2009-12-15 2012-11-06 International Business Machines Corporation Automatic determination of read-ahead amount
US8583894B2 (en) * 2010-09-09 2013-11-12 Advanced Micro Devices Hybrid prefetch method and apparatus
US9342258B2 (en) 2011-09-01 2016-05-17 Freescale Semiconductor, Inc. Integrated circuit device and method for providing data access control
US11126522B2 (en) * 2013-06-18 2021-09-21 Nxp Usa, Inc. Method and apparatus for offloading functional data from an interconnect component
JP6458682B2 (ja) * 2015-08-24 2019-01-30 富士通株式会社 演算処理装置及び演算処理装置の制御方法

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JPS6448159A (en) * 1987-08-19 1989-02-22 Fujitsu Ltd Data prefetch system
JPH0210450A (ja) * 1988-06-29 1990-01-16 Hitachi Ltd キヤツシユメモリの先行フエツチ制御方式
JPH02275549A (ja) * 1989-04-18 1990-11-09 Fujitsu Ltd 中間バッファプリフェッチ制御方式
US5327540A (en) * 1991-09-18 1994-07-05 Ncr Corporation Method and apparatus for decoding bus master arbitration levels to optimize memory transfers
US6453388B1 (en) * 1992-06-17 2002-09-17 Intel Corporation Computer system having a bus interface unit for prefetching data from system memory
US5566324A (en) 1992-12-24 1996-10-15 Ncr Corporation Computer apparatus including a main memory prefetch cache and method of operation thereof
JP3516963B2 (ja) * 1993-03-12 2004-04-05 株式会社東芝 メモリアクセス制御装置
JPH07129464A (ja) * 1993-11-05 1995-05-19 Hitachi Ltd 情報処理装置
JP3590427B2 (ja) * 1994-08-30 2004-11-17 株式会社ルネサステクノロジ 先行読出機能付命令キャッシュメモリ
JPH08137754A (ja) * 1994-11-10 1996-05-31 Fuji Xerox Co Ltd ディスクキャッシュ装置
US5675749A (en) * 1995-06-02 1997-10-07 Motorola, Inc. Method and apparatus for controlling show cycles in a data processing system
JP2720838B2 (ja) * 1995-06-19 1998-03-04 日本電気株式会社 データ転送装置
US6085291A (en) * 1995-11-06 2000-07-04 International Business Machines Corporation System and method for selectively controlling fetching and prefetching of data to a processor
US5802569A (en) * 1996-04-22 1998-09-01 International Business Machines Corp. Computer system having cache prefetching amount based on CPU request types
US5829028A (en) * 1996-05-06 1998-10-27 Advanced Micro Devices, Inc. Data cache configured to store data in a use-once manner
JPH10187531A (ja) * 1996-12-27 1998-07-21 Nec Corp キャッシュメモリのプリフェッチ方式
JPH10301847A (ja) * 1997-04-30 1998-11-13 Nec Corp データ記憶装置
US6138213A (en) * 1997-06-27 2000-10-24 Advanced Micro Devices, Inc. Cache including a prefetch way for storing prefetch cache lines and configured to move a prefetched cache line to a non-prefetch way upon access to the prefetched cache line
US6012106A (en) * 1997-11-03 2000-01-04 Digital Equipment Corporation Prefetch management for DMA read transactions depending upon past history of actual transfer lengths
US6151662A (en) * 1997-12-02 2000-11-21 Advanced Micro Devices, Inc. Data transaction typing for improved caching and prefetching characteristics
US6202107B1 (en) * 1998-11-19 2001-03-13 Sun Microsystems, Inc. Host controller interface descriptor fetching unit
JP3757117B2 (ja) * 1998-12-18 2006-03-22 富士通株式会社 キャッシュ装置及び制御方法
US6542968B1 (en) * 1999-01-15 2003-04-01 Hewlett-Packard Company System and method for managing data in an I/O cache
JP2001014840A (ja) * 1999-06-24 2001-01-19 Nec Corp 複数ラインバッファ型メモリｌｓｉ
WO2001004760A1 (fr) * 1999-07-07 2001-01-18 Hitachi, Ltd. Controleur de memoire
US6636927B1 (en) * 1999-09-24 2003-10-21 Adaptec, Inc. Bridge device for transferring data using master-specific prefetch sizes
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US6564286B2 (en) * 2001-03-07 2003-05-13 Sony Corporation Non-volatile memory system for instant-on
US6832280B2 (en) * 2001-08-10 2004-12-14 Freescale Semiconductor, Inc. Data processing system having an adaptive priority controller
US6832296B2 (en) * 2002-04-09 2004-12-14 Ip-First, Llc Microprocessor with repeat prefetch instruction

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI607316B (zh) * 2013-03-15 2017-12-01 美商谷歌有限責任公司 高效率輸入輸出操作

Also Published As

Publication number Publication date
EP1623329A1 (en) 2006-02-08
CN1809822A (zh) 2006-07-26
CN100435122C (zh) 2008-11-19
KR20060009307A (ko) 2006-01-31
TW200517856A (en) 2005-06-01
US20040225758A1 (en) 2004-11-11
US6871246B2 (en) 2005-03-22
JP2007500402A (ja) 2007-01-11
WO2004102402A1 (en) 2004-11-25
EP1623329A4 (en) 2008-03-26

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