JP2007500402A - 周辺装置アクセス保護付きデータ処理システム - Google Patents

周辺装置アクセス保護付きデータ処理システム Download PDF

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Publication number
JP2007500402A
JP2007500402A JP2006532425A JP2006532425A JP2007500402A JP 2007500402 A JP2007500402 A JP 2007500402A JP 2006532425 A JP2006532425 A JP 2006532425A JP 2006532425 A JP2006532425 A JP 2006532425A JP 2007500402 A JP2007500402 A JP 2007500402A
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JP
Japan
Prior art keywords
prefetch
access
master
control
interconnect
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Pending
Application number
JP2006532425A
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English (en)
Japanese (ja)
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JP2007500402A5 (https=
Inventor
シー モイヤー、ウィリアム
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NXP USA Inc
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NXP USA Inc
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Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JP2007500402A publication Critical patent/JP2007500402A/ja
Publication of JP2007500402A5 publication Critical patent/JP2007500402A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6026—Prefetching based on access pattern detection, e.g. stride based prefetch
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
JP2006532425A 2003-05-07 2004-04-16 周辺装置アクセス保護付きデータ処理システム Pending JP2007500402A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/431,285 US6871246B2 (en) 2003-05-07 2003-05-07 Prefetch control in a data processing system
PCT/US2004/011874 WO2004102402A1 (en) 2003-05-07 2004-04-16 Data processing system with peripheral access protection

Publications (2)

Publication Number Publication Date
JP2007500402A true JP2007500402A (ja) 2007-01-11
JP2007500402A5 JP2007500402A5 (https=) 2007-06-14

Family

ID=33416427

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006532425A Pending JP2007500402A (ja) 2003-05-07 2004-04-16 周辺装置アクセス保護付きデータ処理システム

Country Status (7)

Country Link
US (1) US6871246B2 (https=)
EP (1) EP1623329A4 (https=)
JP (1) JP2007500402A (https=)
KR (1) KR20060009307A (https=)
CN (1) CN100435122C (https=)
TW (1) TWI345710B (https=)
WO (1) WO2004102402A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012533811A (ja) * 2009-07-20 2012-12-27 フリースケール セミコンダクター インコーポレイテッド プリフェッチ・モジュールを備える信号処理システムおよび集積回路、並びにそのための方法

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* Cited by examiner, † Cited by third party
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US7181556B2 (en) * 2003-12-23 2007-02-20 Arm Limited Transaction request servicing mechanism
US7328312B2 (en) 2005-02-03 2008-02-05 International Business Machines Corporation Method and bus prefetching mechanism for implementing enhanced buffer control
JP2006251923A (ja) * 2005-03-08 2006-09-21 Oki Electric Ind Co Ltd 先読み制御方法
US9304773B2 (en) * 2006-03-21 2016-04-05 Freescale Semiconductor, Inc. Data processor having dynamic control of instruction prefetch buffer depth and method therefor
US8307164B2 (en) 2009-12-15 2012-11-06 International Business Machines Corporation Automatic determination of read-ahead amount
US8583894B2 (en) * 2010-09-09 2013-11-12 Advanced Micro Devices Hybrid prefetch method and apparatus
US9342258B2 (en) 2011-09-01 2016-05-17 Freescale Semiconductor, Inc. Integrated circuit device and method for providing data access control
US9218310B2 (en) * 2013-03-15 2015-12-22 Google Inc. Shared input/output (I/O) unit
US11126522B2 (en) * 2013-06-18 2021-09-21 Nxp Usa, Inc. Method and apparatus for offloading functional data from an interconnect component
JP6458682B2 (ja) * 2015-08-24 2019-01-30 富士通株式会社 演算処理装置及び演算処理装置の制御方法

Citations (12)

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JPS6448159A (en) * 1987-08-19 1989-02-22 Fujitsu Ltd Data prefetch system
JPH0210450A (ja) * 1988-06-29 1990-01-16 Hitachi Ltd キヤツシユメモリの先行フエツチ制御方式
US5327540A (en) * 1991-09-18 1994-07-05 Ncr Corporation Method and apparatus for decoding bus master arbitration levels to optimize memory transfers
JPH07129464A (ja) * 1993-11-05 1995-05-19 Hitachi Ltd 情報処理装置
JPH08137754A (ja) * 1994-11-10 1996-05-31 Fuji Xerox Co Ltd ディスクキャッシュ装置
JPH096704A (ja) * 1995-06-19 1997-01-10 Nec Corp データ転送装置
JPH1055307A (ja) * 1996-04-22 1998-02-24 Internatl Business Mach Corp <Ibm> コンピュータ・システム
JPH10187531A (ja) * 1996-12-27 1998-07-21 Nec Corp キャッシュメモリのプリフェッチ方式
JPH10301847A (ja) * 1997-04-30 1998-11-13 Nec Corp データ記憶装置
JP2000235520A (ja) * 1999-01-15 2000-08-29 Hewlett Packard Co <Hp> キャッシュ・データ管理方法
WO2001004760A1 (fr) * 1999-07-07 2001-01-18 Hitachi, Ltd. Controleur de memoire
US20020052987A1 (en) * 1998-11-19 2002-05-02 Sun Microsystems, Inc. Host controller interface descriptor fetching unit

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JPH02275549A (ja) * 1989-04-18 1990-11-09 Fujitsu Ltd 中間バッファプリフェッチ制御方式
US6453388B1 (en) * 1992-06-17 2002-09-17 Intel Corporation Computer system having a bus interface unit for prefetching data from system memory
US5566324A (en) 1992-12-24 1996-10-15 Ncr Corporation Computer apparatus including a main memory prefetch cache and method of operation thereof
JP3516963B2 (ja) * 1993-03-12 2004-04-05 株式会社東芝 メモリアクセス制御装置
JP3590427B2 (ja) * 1994-08-30 2004-11-17 株式会社ルネサステクノロジ 先行読出機能付命令キャッシュメモリ
US5675749A (en) * 1995-06-02 1997-10-07 Motorola, Inc. Method and apparatus for controlling show cycles in a data processing system
US6085291A (en) * 1995-11-06 2000-07-04 International Business Machines Corporation System and method for selectively controlling fetching and prefetching of data to a processor
US5829028A (en) * 1996-05-06 1998-10-27 Advanced Micro Devices, Inc. Data cache configured to store data in a use-once manner
US6138213A (en) * 1997-06-27 2000-10-24 Advanced Micro Devices, Inc. Cache including a prefetch way for storing prefetch cache lines and configured to move a prefetched cache line to a non-prefetch way upon access to the prefetched cache line
US6012106A (en) * 1997-11-03 2000-01-04 Digital Equipment Corporation Prefetch management for DMA read transactions depending upon past history of actual transfer lengths
US6151662A (en) * 1997-12-02 2000-11-21 Advanced Micro Devices, Inc. Data transaction typing for improved caching and prefetching characteristics
JP3757117B2 (ja) * 1998-12-18 2006-03-22 富士通株式会社 キャッシュ装置及び制御方法
JP2001014840A (ja) * 1999-06-24 2001-01-19 Nec Corp 複数ラインバッファ型メモリｌｓｉ
US6636927B1 (en) * 1999-09-24 2003-10-21 Adaptec, Inc. Bridge device for transferring data using master-specific prefetch sizes
US6560693B1 (en) * 1999-12-10 2003-05-06 International Business Machines Corporation Branch history guided instruction/data prefetching
US6542982B2 (en) * 2000-02-24 2003-04-01 Hitachi, Ltd. Data processer and data processing system
US6564286B2 (en) * 2001-03-07 2003-05-13 Sony Corporation Non-volatile memory system for instant-on
US6832280B2 (en) * 2001-08-10 2004-12-14 Freescale Semiconductor, Inc. Data processing system having an adaptive priority controller
US6832296B2 (en) * 2002-04-09 2004-12-14 Ip-First, Llc Microprocessor with repeat prefetch instruction

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6448159A (en) * 1987-08-19 1989-02-22 Fujitsu Ltd Data prefetch system
JPH0210450A (ja) * 1988-06-29 1990-01-16 Hitachi Ltd キヤツシユメモリの先行フエツチ制御方式
US5327540A (en) * 1991-09-18 1994-07-05 Ncr Corporation Method and apparatus for decoding bus master arbitration levels to optimize memory transfers
JPH07129464A (ja) * 1993-11-05 1995-05-19 Hitachi Ltd 情報処理装置
JPH08137754A (ja) * 1994-11-10 1996-05-31 Fuji Xerox Co Ltd ディスクキャッシュ装置
JPH096704A (ja) * 1995-06-19 1997-01-10 Nec Corp データ転送装置
JPH1055307A (ja) * 1996-04-22 1998-02-24 Internatl Business Mach Corp <Ibm> コンピュータ・システム
JPH10187531A (ja) * 1996-12-27 1998-07-21 Nec Corp キャッシュメモリのプリフェッチ方式
JPH10301847A (ja) * 1997-04-30 1998-11-13 Nec Corp データ記憶装置
US20020052987A1 (en) * 1998-11-19 2002-05-02 Sun Microsystems, Inc. Host controller interface descriptor fetching unit
JP2000235520A (ja) * 1999-01-15 2000-08-29 Hewlett Packard Co <Hp> キャッシュ・データ管理方法
WO2001004760A1 (fr) * 1999-07-07 2001-01-18 Hitachi, Ltd. Controleur de memoire

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012533811A (ja) * 2009-07-20 2012-12-27 フリースケール セミコンダクター インコーポレイテッド プリフェッチ・モジュールを備える信号処理システムおよび集積回路、並びにそのための方法

Also Published As

Publication number Publication date
EP1623329A1 (en) 2006-02-08
CN1809822A (zh) 2006-07-26
CN100435122C (zh) 2008-11-19
KR20060009307A (ko) 2006-01-31
TW200517856A (en) 2005-06-01
US20040225758A1 (en) 2004-11-11
US6871246B2 (en) 2005-03-22
WO2004102402A1 (en) 2004-11-25
EP1623329A4 (en) 2008-03-26
TWI345710B (en) 2011-07-21

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