CN100435122C - 具有外设访问保护的数据处理系统 - Google Patents

具有外设访问保护的数据处理系统 Download PDF

Info

Publication number
CN100435122C
CN100435122C CNB2004800122164A CN200480012216A CN100435122C CN 100435122 C CN100435122 C CN 100435122C CN B2004800122164 A CNB2004800122164 A CN B2004800122164A CN 200480012216 A CN200480012216 A CN 200480012216A CN 100435122 C CN100435122 C CN 100435122C
Authority
CN
China
Prior art keywords
prefetch
master
control
access
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB2004800122164A
Other languages
English (en)
Chinese (zh)
Other versions
CN1809822A (zh
Inventor
威廉姆·C.·莫耶
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of CN1809822A publication Critical patent/CN1809822A/zh
Application granted granted Critical
Publication of CN100435122C publication Critical patent/CN100435122C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6026—Prefetching based on access pattern detection, e.g. stride based prefetch
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
CNB2004800122164A 2003-05-07 2004-04-16 具有外设访问保护的数据处理系统 Expired - Lifetime CN100435122C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/431,285 2003-05-07
US10/431,285 US6871246B2 (en) 2003-05-07 2003-05-07 Prefetch control in a data processing system

Publications (2)

Publication Number Publication Date
CN1809822A CN1809822A (zh) 2006-07-26
CN100435122C true CN100435122C (zh) 2008-11-19

Family

ID=33416427

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004800122164A Expired - Lifetime CN100435122C (zh) 2003-05-07 2004-04-16 具有外设访问保护的数据处理系统

Country Status (7)

Country Link
US (1) US6871246B2 (https=)
EP (1) EP1623329A4 (https=)
JP (1) JP2007500402A (https=)
KR (1) KR20060009307A (https=)
CN (1) CN100435122C (https=)
TW (1) TWI345710B (https=)
WO (1) WO2004102402A1 (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7181556B2 (en) * 2003-12-23 2007-02-20 Arm Limited Transaction request servicing mechanism
US7328312B2 (en) 2005-02-03 2008-02-05 International Business Machines Corporation Method and bus prefetching mechanism for implementing enhanced buffer control
JP2006251923A (ja) * 2005-03-08 2006-09-21 Oki Electric Ind Co Ltd 先読み制御方法
US9304773B2 (en) * 2006-03-21 2016-04-05 Freescale Semiconductor, Inc. Data processor having dynamic control of instruction prefetch buffer depth and method therefor
US9652413B2 (en) 2009-07-20 2017-05-16 Nxp Usa, Inc. Signal processing system and integrated circuit comprising a prefetch module and method therefor
US8307164B2 (en) 2009-12-15 2012-11-06 International Business Machines Corporation Automatic determination of read-ahead amount
US8583894B2 (en) * 2010-09-09 2013-11-12 Advanced Micro Devices Hybrid prefetch method and apparatus
US9342258B2 (en) 2011-09-01 2016-05-17 Freescale Semiconductor, Inc. Integrated circuit device and method for providing data access control
US9218310B2 (en) * 2013-03-15 2015-12-22 Google Inc. Shared input/output (I/O) unit
US11126522B2 (en) * 2013-06-18 2021-09-21 Nxp Usa, Inc. Method and apparatus for offloading functional data from an interconnect component
JP6458682B2 (ja) * 2015-08-24 2019-01-30 富士通株式会社 演算処理装置及び演算処理装置の制御方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000038077A1 (fr) * 1998-12-18 2000-06-29 Fujitsu Limited Antememoire et procede de commande
CN1306246A (zh) * 1999-12-10 2001-08-01 国际商业机器公司 预取由转移历史引导的指令/数据
CN1410893A (zh) * 2002-04-09 2003-04-16 智慧第一公司 具有预取指令的微处理器及预取至其高速缓存的方法

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6448159A (en) * 1987-08-19 1989-02-22 Fujitsu Ltd Data prefetch system
JPH0210450A (ja) * 1988-06-29 1990-01-16 Hitachi Ltd キヤツシユメモリの先行フエツチ制御方式
JPH02275549A (ja) * 1989-04-18 1990-11-09 Fujitsu Ltd 中間バッファプリフェッチ制御方式
US5327540A (en) * 1991-09-18 1994-07-05 Ncr Corporation Method and apparatus for decoding bus master arbitration levels to optimize memory transfers
US6453388B1 (en) * 1992-06-17 2002-09-17 Intel Corporation Computer system having a bus interface unit for prefetching data from system memory
US5566324A (en) 1992-12-24 1996-10-15 Ncr Corporation Computer apparatus including a main memory prefetch cache and method of operation thereof
JP3516963B2 (ja) * 1993-03-12 2004-04-05 株式会社東芝 メモリアクセス制御装置
JPH07129464A (ja) * 1993-11-05 1995-05-19 Hitachi Ltd 情報処理装置
JP3590427B2 (ja) * 1994-08-30 2004-11-17 株式会社ルネサステクノロジ 先行読出機能付命令キャッシュメモリ
JPH08137754A (ja) * 1994-11-10 1996-05-31 Fuji Xerox Co Ltd ディスクキャッシュ装置
US5675749A (en) * 1995-06-02 1997-10-07 Motorola, Inc. Method and apparatus for controlling show cycles in a data processing system
JP2720838B2 (ja) * 1995-06-19 1998-03-04 日本電気株式会社 データ転送装置
US6085291A (en) * 1995-11-06 2000-07-04 International Business Machines Corporation System and method for selectively controlling fetching and prefetching of data to a processor
US5802569A (en) * 1996-04-22 1998-09-01 International Business Machines Corp. Computer system having cache prefetching amount based on CPU request types
US5829028A (en) * 1996-05-06 1998-10-27 Advanced Micro Devices, Inc. Data cache configured to store data in a use-once manner
JPH10187531A (ja) * 1996-12-27 1998-07-21 Nec Corp キャッシュメモリのプリフェッチ方式
JPH10301847A (ja) * 1997-04-30 1998-11-13 Nec Corp データ記憶装置
US6138213A (en) * 1997-06-27 2000-10-24 Advanced Micro Devices, Inc. Cache including a prefetch way for storing prefetch cache lines and configured to move a prefetched cache line to a non-prefetch way upon access to the prefetched cache line
US6012106A (en) * 1997-11-03 2000-01-04 Digital Equipment Corporation Prefetch management for DMA read transactions depending upon past history of actual transfer lengths
US6151662A (en) * 1997-12-02 2000-11-21 Advanced Micro Devices, Inc. Data transaction typing for improved caching and prefetching characteristics
US6202107B1 (en) * 1998-11-19 2001-03-13 Sun Microsystems, Inc. Host controller interface descriptor fetching unit
US6542968B1 (en) * 1999-01-15 2003-04-01 Hewlett-Packard Company System and method for managing data in an I/O cache
JP2001014840A (ja) * 1999-06-24 2001-01-19 Nec Corp 複数ラインバッファ型メモリｌｓｉ
WO2001004760A1 (fr) * 1999-07-07 2001-01-18 Hitachi, Ltd. Controleur de memoire
US6636927B1 (en) * 1999-09-24 2003-10-21 Adaptec, Inc. Bridge device for transferring data using master-specific prefetch sizes
US6542982B2 (en) * 2000-02-24 2003-04-01 Hitachi, Ltd. Data processer and data processing system
US6564286B2 (en) * 2001-03-07 2003-05-13 Sony Corporation Non-volatile memory system for instant-on
US6832280B2 (en) * 2001-08-10 2004-12-14 Freescale Semiconductor, Inc. Data processing system having an adaptive priority controller

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000038077A1 (fr) * 1998-12-18 2000-06-29 Fujitsu Limited Antememoire et procede de commande
CN1306246A (zh) * 1999-12-10 2001-08-01 国际商业机器公司 预取由转移历史引导的指令/数据
CN1410893A (zh) * 2002-04-09 2003-04-16 智慧第一公司 具有预取指令的微处理器及预取至其高速缓存的方法

Also Published As

Publication number Publication date
EP1623329A1 (en) 2006-02-08
CN1809822A (zh) 2006-07-26
KR20060009307A (ko) 2006-01-31
TW200517856A (en) 2005-06-01
US20040225758A1 (en) 2004-11-11
US6871246B2 (en) 2005-03-22
JP2007500402A (ja) 2007-01-11
WO2004102402A1 (en) 2004-11-25
EP1623329A4 (en) 2008-03-26
TWI345710B (en) 2011-07-21

Similar Documents

Publication Publication Date Title
CN100407165C (zh) 数据处理系统中的预取控制
CN100419712C (zh) 用于动态预取缓冲器配置和替换的方法及设备
CN100576811C (zh) 总线装置、总线系统和信息传输方法
US5787475A (en) Controlled prefetching of data requested by a peripheral
US8356143B1 (en) Prefetch mechanism for bus master memory access
CN100435122C (zh) 具有外设访问保护的数据处理系统
CN100492332C (zh) 动态优先级外部事务处理系统
JP2007073052A (ja) 集積回路から外部メモリへのアクセス
JP4652394B2 (ja) マルチバーストプロトコルデバイスコントローラ
US7340542B2 (en) Data processing system with bus access retraction
US6968402B2 (en) System and method for storing chunks of first cache line and second cache line in a buffer in a first and second chunk order
US7130943B2 (en) Data processing system with bus access retraction
TWI324755B (en) Processing modules with multilevel cache architecture
JP2009037639A (ja) ストリーミングｉｄメソッドによるｄｍａｃ発行メカニズム
JP4431492B2 (ja) 複数のコヒーレンシー・グラニュールをサポートするデータ転送ユニット
US7657690B1 (en) Control of PCI memory read behavior using memory read alias and memory command reissue bits
JP2001256169A (ja) データ転送制御システム及び装置
WO2012069874A1 (en) Integrated circuit device, signal processing system and method for prefetching lines of data therefor
US20060129726A1 (en) Methods and apparatus for processing a command

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CP01 Change in the name or title of a patent holder

Address after: Texas in the United States

Patentee after: NXP USA, Inc.

Address before: Texas in the United States

Patentee before: FREESCALE SEMICONDUCTOR, Inc.

CP01 Change in the name or title of a patent holder
CX01 Expiry of patent term

Granted publication date: 20081119

CX01 Expiry of patent term