JP2006309755A5 - - Google Patents

Download PDF

Info

Publication number
JP2006309755A5
JP2006309755A5 JP2006113107A JP2006113107A JP2006309755A5 JP 2006309755 A5 JP2006309755 A5 JP 2006309755A5 JP 2006113107 A JP2006113107 A JP 2006113107A JP 2006113107 A JP2006113107 A JP 2006113107A JP 2006309755 A5 JP2006309755 A5 JP 2006309755A5
Authority
JP
Japan
Prior art keywords
command
tag
slave device
response
slave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006113107A
Other languages
English (en)
Japanese (ja)
Other versions
JP4881052B2 (ja
JP2006309755A (ja
Filing date
Publication date
Priority claimed from US11/106,791 external-priority patent/US7373444B2/en
Application filed filed Critical
Publication of JP2006309755A publication Critical patent/JP2006309755A/ja
Publication of JP2006309755A5 publication Critical patent/JP2006309755A5/ja
Application granted granted Critical
Publication of JP4881052B2 publication Critical patent/JP4881052B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2006113107A 2005-04-15 2006-04-17 タグ情報を使用してコマンドバッファから廃棄されたエントリを除去するシステム及び方法 Expired - Fee Related JP4881052B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/106,791 2005-04-15
US11/106,791 US7373444B2 (en) 2005-04-15 2005-04-15 Systems and methods for manipulating entries in a command buffer using tag information

Publications (3)

Publication Number Publication Date
JP2006309755A JP2006309755A (ja) 2006-11-09
JP2006309755A5 true JP2006309755A5 (https=) 2007-11-29
JP4881052B2 JP4881052B2 (ja) 2012-02-22

Family

ID=37109879

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006113107A Expired - Fee Related JP4881052B2 (ja) 2005-04-15 2006-04-17 タグ情報を使用してコマンドバッファから廃棄されたエントリを除去するシステム及び方法

Country Status (2)

Country Link
US (1) US7373444B2 (https=)
JP (1) JP4881052B2 (https=)

Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100770972B1 (ko) 2006-11-28 2007-10-30 전자부품연구원 단일 신호선을 이용한 복수의 장비간의 비대칭 통신 방법
EP2388707B1 (en) * 2010-05-20 2014-03-26 STMicroelectronics (Grenoble 2) SAS Interconnection method and device, for example for systems-on-chip
JP5664187B2 (ja) * 2010-12-06 2015-02-04 ソニー株式会社 相互接続装置、および、その制御方法
US10157060B2 (en) 2011-12-29 2018-12-18 Intel Corporation Method, device and system for control signaling in a data path module of a data stream processing engine
US20140215148A1 (en) 2013-01-31 2014-07-31 International Business Machines Corporation Limiting the execution of background management operations in a drive array
US8713502B1 (en) 2013-02-26 2014-04-29 International Business Machines Corporation Methods and systems to reduce a number of simulations in a timing analysis
US9092330B2 (en) 2013-03-15 2015-07-28 International Business Machines Corporation Early data delivery prior to error detection completion
US9535778B2 (en) 2013-03-15 2017-01-03 International Business Machines Corporation Reestablishing synchronization in a memory system
US9142272B2 (en) 2013-03-15 2015-09-22 International Business Machines Corporation Dual asynchronous and synchronous memory system
US9146864B2 (en) 2013-03-15 2015-09-29 International Business Machines Corporation Address mapping including generic bits for universal addressing independent of memory type
US9136987B2 (en) 2013-03-15 2015-09-15 International Business Machines Corporation Replay suspension in a memory system
US9037811B2 (en) * 2013-03-15 2015-05-19 International Business Machines Corporation Tagging in memory control unit (MCU)
US9430418B2 (en) 2013-03-15 2016-08-30 International Business Machines Corporation Synchronization and order detection in a memory system
CN103226457B (zh) * 2013-04-28 2016-03-02 惠州市德赛西威汽车电子股份有限公司 一种显示处理器的显示控制方法
US9223542B2 (en) * 2013-05-20 2015-12-29 Advanced Micro Devices, Inc. Variable-sized buffers mapped to hardware registers
US10331583B2 (en) 2013-09-26 2019-06-25 Intel Corporation Executing distributed memory operations using processing elements connected by distributed channels
US10579580B2 (en) 2013-12-18 2020-03-03 Qorvo Us, Inc. Start of sequence detection for one wire bus
US10528502B2 (en) 2013-12-18 2020-01-07 Qorvo Us, Inc. Power management system for a bus interface system
US10282269B2 (en) * 2013-12-18 2019-05-07 Qorvo Us, Inc. Read technique for a bus interface system
US10049026B2 (en) 2013-12-18 2018-08-14 Qorvo Us, Inc. Group write technique for a bus interface system
US10540226B2 (en) 2013-12-18 2020-01-21 Qorvo Us, Inc. Write technique for a bus interface system
US10185683B2 (en) 2013-12-18 2019-01-22 Qorvo Us, Inc. Bus interface system
US9875459B2 (en) * 2015-11-23 2018-01-23 Schlumberger Technology Corporation Wellsite equipment tracking systems and methods
US10579128B2 (en) 2016-03-01 2020-03-03 Qorvo Us, Inc. Switching power supply for subus slaves
US10198384B2 (en) 2016-03-01 2019-02-05 Qorvo Us, Inc. One wire bus to RFFE translation system
US10437772B2 (en) 2016-03-24 2019-10-08 Qorvo Us, Inc. Addressing of slave devices on a single wire communications bus through register map address selection
US10176130B2 (en) 2016-03-30 2019-01-08 Qorvo Us, Inc. Slave device identification on a single wire communications bus
US10558575B2 (en) 2016-12-30 2020-02-11 Intel Corporation Processors, methods, and systems with a configurable spatial accelerator
US10169273B2 (en) * 2017-01-11 2019-01-01 Qualcomm Incorporated Forced compression of single I2C writes
US10558607B2 (en) 2017-02-01 2020-02-11 Qorvo Us, Inc. Bus interface system for power extraction
US10515046B2 (en) 2017-07-01 2019-12-24 Intel Corporation Processors, methods, and systems with a configurable spatial accelerator
US10515049B1 (en) 2017-07-01 2019-12-24 Intel Corporation Memory circuits and methods for distributed memory hazard detection and error recovery
US10496574B2 (en) 2017-09-28 2019-12-03 Intel Corporation Processors, methods, and systems for a memory fence in a configurable spatial accelerator
US11086816B2 (en) 2017-09-28 2021-08-10 Intel Corporation Processors, methods, and systems for debugging a configurable spatial accelerator
US10565134B2 (en) * 2017-12-30 2020-02-18 Intel Corporation Apparatus, methods, and systems for multicast in a configurable spatial accelerator
US10564980B2 (en) 2018-04-03 2020-02-18 Intel Corporation Apparatus, methods, and systems for conditional queues in a configurable spatial accelerator
US11307873B2 (en) 2018-04-03 2022-04-19 Intel Corporation Apparatus, methods, and systems for unstructured data flow in a configurable spatial accelerator with predicate propagation and merging
US10891240B2 (en) 2018-06-30 2021-01-12 Intel Corporation Apparatus, methods, and systems for low latency communication in a configurable spatial accelerator
US11200186B2 (en) 2018-06-30 2021-12-14 Intel Corporation Apparatuses, methods, and systems for operations in a configurable spatial accelerator
US10853073B2 (en) 2018-06-30 2020-12-01 Intel Corporation Apparatuses, methods, and systems for conditional operations in a configurable spatial accelerator
US10983836B2 (en) * 2018-08-13 2021-04-20 International Business Machines Corporation Transaction optimization during periods of peak activity
US10678724B1 (en) 2018-12-29 2020-06-09 Intel Corporation Apparatuses, methods, and systems for in-network storage in a configurable spatial accelerator
US10599601B1 (en) 2019-01-16 2020-03-24 Qorvo Us, Inc. Single-wire bus (SuBUS) slave circuit and related apparatus
US10915471B2 (en) 2019-03-30 2021-02-09 Intel Corporation Apparatuses, methods, and systems for memory interface circuit allocation in a configurable spatial accelerator
US10817291B2 (en) 2019-03-30 2020-10-27 Intel Corporation Apparatuses, methods, and systems for swizzle operations in a configurable spatial accelerator
US11029927B2 (en) 2019-03-30 2021-06-08 Intel Corporation Methods and apparatus to detect and annotate backedges in a dataflow graph
US10965536B2 (en) 2019-03-30 2021-03-30 Intel Corporation Methods and apparatus to insert buffers in a dataflow graph
US11119958B2 (en) 2019-04-18 2021-09-14 Qorvo Us, Inc. Hybrid bus apparatus
US11226924B2 (en) 2019-04-24 2022-01-18 Qorvo Us, Inc. Single-wire bus apparatus supporting slave-initiated operation in a master circuit
US11037050B2 (en) 2019-06-29 2021-06-15 Intel Corporation Apparatuses, methods, and systems for memory interface circuit arbitration in a configurable spatial accelerator
US10983942B1 (en) 2019-12-11 2021-04-20 Qorvo Us, Inc. Multi-master hybrid bus apparatus
US11907713B2 (en) 2019-12-28 2024-02-20 Intel Corporation Apparatuses, methods, and systems for fused operations using sign modification in a processing element of a configurable spatial accelerator
US12086080B2 (en) 2020-09-26 2024-09-10 Intel Corporation Apparatuses, methods, and systems for a configurable accelerator having dataflow execution circuits
US11409677B2 (en) 2020-11-11 2022-08-09 Qorvo Us, Inc. Bus slave circuit and related single-wire bus apparatus
US11489695B2 (en) 2020-11-24 2022-11-01 Qorvo Us, Inc. Full-duplex communications over a single-wire bus
CN112860622B (zh) * 2021-02-08 2022-11-04 山东云海国创云计算装备产业创新中心有限公司 一种处理系统以及一种片上系统
CN115344244A (zh) * 2021-05-14 2022-11-15 瑞昱半导体股份有限公司 处理程序语言函数的装置及方法
US12092689B2 (en) 2021-12-08 2024-09-17 Qorvo Us, Inc. Scan test in a single-wire bus circuit
US11706048B1 (en) 2021-12-16 2023-07-18 Qorvo Us, Inc. Multi-protocol bus circuit
US12182052B2 (en) 2022-01-20 2024-12-31 Qorvo Us, Inc. Slave-initiated communications over a single-wire bus

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04139556A (ja) * 1990-10-01 1992-05-13 Nec Corp リトライ制御方式
JPH05189351A (ja) * 1992-01-13 1993-07-30 Shikoku Nippon Denki Software Kk バス変換装置
JP3401729B2 (ja) * 1993-05-28 2003-04-28 富士通株式会社 スプリットバス制御回路
JPH0728604A (ja) * 1993-07-13 1995-01-31 Hitachi Ltd ディスク装置
JPH0793244A (ja) * 1993-09-21 1995-04-07 Fuji Xerox Co Ltd 外部記憶制御装置
US5537570A (en) * 1993-10-12 1996-07-16 Texas Instruments Incorporated Cache with a tag duplicate fault avoidance system and method
US5784590A (en) * 1994-06-29 1998-07-21 Exponential Technology, Inc. Slave cache having sub-line valid bits updated by a master cache
US5832241A (en) * 1995-02-23 1998-11-03 Intel Corporation Data consistency across a bus transactions that impose ordering constraints
US6112019A (en) * 1995-06-12 2000-08-29 Georgia Tech Research Corp. Distributed instruction queue
JPH09106378A (ja) * 1995-10-12 1997-04-22 Hitachi Ltd インタフェース方法
US5864707A (en) * 1995-12-11 1999-01-26 Advanced Micro Devices, Inc. Superscalar microprocessor configured to predict return addresses from a return stack storage
US5897656A (en) * 1996-09-16 1999-04-27 Corollary, Inc. System and method for maintaining memory coherency in a computer system having multiple system buses
US6356944B1 (en) * 1997-03-31 2002-03-12 Compaq Information Technologies Group, L.P. System and method for increasing write performance in a fibre channel environment
US6240479B1 (en) * 1998-07-31 2001-05-29 Motorola, Inc. Method and apparatus for transferring data on a split bus in a data processing system
US6360308B1 (en) * 1998-09-30 2002-03-19 Lsi Logic Corporation Buffer controller
US6732208B1 (en) * 1999-02-25 2004-05-04 Mips Technologies, Inc. Low latency system bus interface for multi-master processing environments
US6772383B1 (en) * 1999-05-27 2004-08-03 Intel Corporation Combined tag and data ECC for enhanced soft error recovery from cache tag errors
JP2001005744A (ja) * 1999-06-18 2001-01-12 Hitachi Ltd チャネル装置
US6493776B1 (en) * 1999-08-12 2002-12-10 Mips Technologies, Inc. Scalable on-chip system bus
US6490642B1 (en) * 1999-08-12 2002-12-03 Mips Technologies, Inc. Locked read/write on separate address/data bus using write barrier
US6636906B1 (en) * 2000-04-28 2003-10-21 Hewlett-Packard Development Company, L.P. Apparatus and method for ensuring forward progress in coherent I/O systems
US6820165B2 (en) * 2000-08-31 2004-11-16 Hewlett-Packard Development Company, L.P. System and method for increasing the count of outstanding split transactions
US6658520B1 (en) * 2000-09-26 2003-12-02 Intel Corporation Method and system for keeping two independent busses coherent following a direct memory access
US6728790B2 (en) * 2001-10-15 2004-04-27 Advanced Micro Devices, Inc. Tagging and arbitration mechanism in an input/output node of a computer system
JP2003162380A (ja) * 2001-11-27 2003-06-06 Pfu Ltd Ｒａｉｄ装置およびエラーリカバリ方法
JP4307008B2 (ja) * 2002-04-01 2009-08-05 京セラ株式会社 画像形成装置
JP2003323276A (ja) * 2002-05-02 2003-11-14 Canon Inc 情報処理装置および印刷装置およびジョブ処理方法およびコンピュータが読み取り可能な記憶媒体およびプログラム
US7127562B2 (en) * 2003-06-11 2006-10-24 International Business Machines Corporation Ensuring orderly forward progress in granting snoop castout requests
US7203780B2 (en) * 2005-02-22 2007-04-10 Kabushiki Kaisha Toshiba System and method for facilitating communication between devices on a bus using tags
US20060190655A1 (en) * 2005-02-24 2006-08-24 International Business Machines Corporation Apparatus and method for transaction tag mapping between bus domains
US7290074B2 (en) * 2005-04-06 2007-10-30 Kabushiki Kaisha Toshiba Back-off timing mechanism

Similar Documents

Publication Publication Date Title
JP4881052B2 (ja) タグ情報を使用してコマンドバッファから廃棄されたエントリを除去するシステム及び方法
JP2006309755A5 (https=)
US6647453B1 (en) System and method for providing forward progress and avoiding starvation and livelock in a multiprocessor computer system
JP3275051B2 (ja) バスブリッジにおけるトランザクション順序を維持し、遅延応答をサポートする方法及びそのための装置
US6070209A (en) Delivering transactions between data buses in a computer system
US6330630B1 (en) Computer system having improved data transfer across a bus bridge
JP7419261B2 (ja) ストリーミングデータ転送のためのフロー圧縮を用いたデータ処理ネットワーク
CN117009272A (zh) 数据处理
JP2002530744A (ja) 多重レベル接続識別を備えた通信のシステムおよび方法
CN112955876B (zh) 用于在数据处理网络中传输数据的方法和装置
US20140365632A1 (en) Interface apparatus and memory bus system
US5991855A (en) Low latency memory read with concurrent pipe lined snoops
US7203780B2 (en) System and method for facilitating communication between devices on a bus using tags
US8560776B2 (en) Method for expediting return of line exclusivity to a given processor in a symmetric multiprocessing data processing system
US20020184330A1 (en) Shared memory multiprocessor expansion port for multi-node systems
US20100169527A1 (en) Data path master/slave data processing device
US7996614B2 (en) Cache intervention on a separate data bus when on-chip bus has separate read and write data busses
CN119271618B (zh) 一种rdma网卡请求队列的实现方法及系统
US6591325B1 (en) Method and apparatus of out-of-order transaction processing using request side queue pointer and response side queue pointer
KR0153487B1 (ko) 장치간의 통신 수행 방법 및 통신 수행 시스템
JP2004334863A (ja) 順番のある（ｉｎ−ｏｒｄｅｒ）キューをドレインする（ｄｒａｉｎ）システムおよび方法
US7519780B2 (en) System and method for reducing store latency in symmetrical multiprocessor systems
JP2002108836A (ja) プロセッサシステム
EP4022445B1 (en) An apparatus and method for handling ordered transactions
US20060253662A1 (en) Retry cancellation mechanism to enhance system performance