TWI332258B - Controlling flip-chip techniques for concurrent ball bonds in semiconductor devices - Google Patents

Controlling flip-chip techniques for concurrent ball bonds in semiconductor devices Download PDF

Info

Publication number
TWI332258B
TWI332258B TW096111458A TW96111458A TWI332258B TW I332258 B TWI332258 B TW I332258B TW 096111458 A TW096111458 A TW 096111458A TW 96111458 A TW96111458 A TW 96111458A TW I332258 B TWI332258 B TW I332258B
Authority
TW
Taiwan
Prior art keywords
pads
wafer
substrate
ball
spacers
Prior art date
Application number
TW096111458A
Other languages
English (en)
Other versions
TW200802784A (en
Inventor
David N Walter
Duy-Loan T Le
Mark A Gerber
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of TW200802784A publication Critical patent/TW200802784A/zh
Application granted granted Critical
Publication of TWI332258B publication Critical patent/TWI332258B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48647—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8121—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/8503—Reshaping, e.g. forming the ball or the wedge of the wire connector
    • H01L2224/85035—Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball"
    • H01L2224/85045—Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball" using a corona discharge, e.g. electronic flame off [EFO]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06579—TAB carriers; beam leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01031—Gallium [Ga]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01083—Bismuth [Bi]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/201—Temperature ranges
    • H01L2924/20105—Temperature range 150 C=<T<200 C, 423.15 K =< T < 473.15K
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/201—Temperature ranges
    • H01L2924/20106—Temperature range 200 C=<T<250 C, 473.15 K =<T < 523.15K
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/201—Temperature ranges
    • H01L2924/20107—Temperature range 250 C=<T<300 C, 523.15K =<T< 573.15K
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20751—Diameter ranges larger or equal to 10 microns less than 20 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20753—Diameter ranges larger or equal to 30 microns less than 40 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20754—Diameter ranges larger or equal to 40 microns less than 50 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20755—Diameter ranges larger or equal to 50 microns less than 60 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20756—Diameter ranges larger or equal to 60 microns less than 70 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20757—Diameter ranges larger or equal to 70 microns less than 80 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20758—Diameter ranges larger or equal to 80 microns less than 90 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20759—Diameter ranges larger or equal to 90 microns less than 100 microns

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Description

1332258 九、發明說明： 【發明所屬之技術領域】 本發明大體而言係關於半導體裝置及處理之領域，且更 特定言之係關於用於s直地整合之半導體系統之低輪廓封 裝之結構及處理。 【先前技術】 半導體技術使其產品之功能複雜性每18個月增加一倍
(莫耳定律（Moore’s &quot;law”））之長期趨勢具有若干隱含結 果。第一，較高產品複雜性在报大程度上應藉由收縮晶片 組件之特徵大小，同時使封裝尺寸保持恆定（較佳地，甚 至封裝應收縮）而達成。第二，增加之功能複雜性應與產 品可靠性之相當的增長並行。第三，每功能單元之成本應 隨每-代複雜性而降低以使得具有加倍之功能性的產品之 成本將僅微小地增加。 、就半導體封裝中之挑戰而t，主要趨勢為收縮封裝外形 以使得封裝在安裝至電路板上時消耗較小面積及較小高 度’且以最小成本（材料及製造成本兩者）達到此等目標之 努力》近來’向此挑戰清單添加另_要求，即設計封裝以 使件晶片及/或封裝之堆最键兔描丄 箄且變為增加功能密度及減小裝置 厚度之選項之需要。此外，助 r期望堆疊晶片及封裝之成功策 略將縮短創新產品之上市時門 市盼間，该專產品利用具有各種能 力之可用晶片（諸如處理器及々 a &quot;己隐體日日片）’且將無需等待 曰曰片之再設計0 近來的尤其是用於掌上型 無線設備 與對於資料容量及 H9725.doc 1332258 向處理速度之熱切要求組合之應用對用於此等應用之半導 體組件之大小及體積提出新的、嚴格的限制。因此，市場 正繼續推動在二維及三維上收縮半導體裝置且此小型化 努力包括用於半導體裝置及電子系統之封裝策略。 【發明内容】 申請人認識到對於達成在二維及三維上收縮半導體裝置 封裝的連貫、低成本方法之全新概念之需要，該概念包括 關於半導體裝置之裝置堆疊及封裝層疊選項以及倒裝晶片 及導線結合互連之裝配選項。裝置可為豎直整合之半導體 系統之基礎，系統可包括具有功能多樣性之積體電路晶 片及被動’’且件。戶斤得系統應具有極佳電效能、機械穩定性 及較高產品可靠性。此外，系統之製造方法足夠f活以應 用於不同的半導體產品家族及較廣範圍之設計及處理變化 將為一技術優勢。
本發明之一實施例為具有兩個半導體晶片及一可為另一 晶月之基板之半導體裝置。第—半導體晶片具有—大小以 及焊墊位置處的内部第一組及周邊第二組接觸焊墊。將諸 如金之非回焊金屬《變形球體置放於第一及第二組之每一 接觸焊墊上。將至少-額外變形球體置放於第一組焊墊上 從而形成具有-高度之柱狀間隔物。冑第-晶片附著至基 板’該基板具有—晶片附著位置及接近該位置處之第三組 接觸焊墊。低輪廟結合導線跨越於第三組與第二組焊塾之 間八有大小之_第二半導體晶片具有在匹配第—組焊塾 之位置處的第四組接觸焊墊。將第二晶片一 ^ 日日&gt;5 119725.doc 1332258 :’使得第四組焊塾與匹配之第一組焊塾上的間 準，且第-曰H — r , 曰曰月之至少一邊緣懸垂於第二組中之至少一焊 一求體上回焊金屬將間隔物結合至第二晶片，同時 間隔物使第—盘势_ „ '、一 aa片以足夠寬以可將導線跨度置放至 第二組焊墊之間隙隔開。 本發明之另一實施例為用於製造堆疊之半導體裝置之方 法。第一半導體晶圓具有一主動表面，其具有具㈣第一 組及^邊第二組接觸焊塾之裝置；晶圓在其被動表面上接 ，黏耆材料且接著經單—化為具有特定大小之離散的第一 晶片 。 接下來’具有晶片附著位置及接近該位置處之第三組接 觸焊墊之基板接收-附著之第一晶片。在第一組及第二組 ^之每-晶片接觸焊墊上置放並擠塵一金球。對於第一組 ~塾重複球之置放及擠壓以產生且有一 土，、另将疋向度之柱狀間 隔物。結合導線跨越第二盥第=έ煜 /、乐一組斗墊之間的低輪廓以連 接第一晶片與基板。 對於一些實施例，在第一日κ μ 弟曰曰片上以一約等於間隔物高度 之高度沈積-聚合物前駆體材料從而保護第二組焊塾上之 導線結合係有利的。 接下來’提供-第二半導體晶片，其具有在匹配第一焊 塾組之位置處具第四組接觸焊塾之裝置。在將第二晶圓單 一化為具有第二大小之離散第二aH 二 欣乐一 b曰片之刖，可向第四組焊 墊塗覆諸如錫合金之回焊金屬。 將第二晶片置放於該第一晶片上，估铱 l 曰曰月上，使第四組焊墊與匹配 119725.doc -9· 1332258 之第-組焊墊上的間隔物對準以使得該第二晶片之至少一 邊緣懸垂於第二組中之至少— v知墊上之球上。施加熱能以 。焊第四組知墊上之金屬從而將間隔物結合至第二晶片， 使得第一與第二晶片電連接。 '二μ轭例，包括將導線結合囊封於保護化合物中 之額外處理步驟係有利的。另_步驟可包括回焊主體至基 板之附著以提供至外部部分之焊料連接。
在結合隨附圖式及附加申請專利範圍而考慮時，本發明 之特定實施例所表示之技術進步將自對本發明之較佳實施 例的以下描述而變得顯而易見。 【實施方式】
圖1說明統一表示為1〇〇之經裝配之半導體裝置之部分， 其包括藉由所發明之裝配技術之組合而堆疊於基板上之半 導體晶片。第一半導體晶片表示為1〇1 具有包括裝置 及電路之主動表面101a、被動表面101b及周邊101c。第一 晶片ι〇1具有特定大小，但圖1僅展示晶片周邊附近之晶片 刀。第一晶片1 〇丨之主動表面具有定位於晶片之内部部 分中之第—組接觸焊墊1〇2及定位於晶片之周邊部分中之 第一組接觸焊塾1〇3。 如圖1所描繪，第二組接觸焊墊103具有置放於接觸焊墊 上之非回焊金屬之變形球體104。第一組接觸焊墊1〇2具有 置放於接觸焊塾上之m變形球體，以使得該等球體 形成具有特定高度105a之柱狀間隔物1〇5。 如本文中所界定，術語回焊金屬係指在約15〇。匸與32〇£^ 119725.doc 1332258 :間的溫度下炫融之金屬或合金，實例為由錫或各種錫合 金（含有銀、銅、錢及錯）製成之焊料。相比之下術狂非 :焊金屬係指在約航與⑽代之間的溫度下炼融：金 ^或合金’實例為銀、金及銅。較佳非回焊金屬為金或金 合金；或者’其可為銅或銅合金。 晶片101由諸如石夕、鍺化石夕或砷化鎵之半導體材料製 成，對於大多數實施例，較佳材料為石夕。較佳由一或多個
保護膜（諸如氮化m氧切）層覆蓋主動表面用於機械 保護及防潮；W中未展示保護膜。保護膜中之窗暴露晶 片金屬化為焊墊位置處之接觸焊塾（102、103)之部分。在 進階高速裝置中’已將窗之大小減小為大大低於50至 70 μπι2。
θ接觸焊墊較佳由銅製成；或者，其可包括鋁或鋁合金。 焊塾具有可進行導線結合之冶金表面組成；實例為具有較 薄紹層或錄及金層之表面。I緣層可更—般化地為阻焊 劑；當其界定如圖！所示之暴露金屬1〇2及1〇3時，經常將 金屬焊墊稱為阻焊劑界定之金屬焊墊。 圖1之實施例具有基板110，其具有第一表面11〇3及與第 表面相對之表示為11〇b的表面。基板可為另一半導體晶 片。或者，基板具有整合有傳導線及通道ηι之絕緣基底 材料。表面1 l〇a上為適於附著半導體晶片之位置及接近 此位置處的第二组接觸焊墊丨12。在圖丨所說明之組態中， 接觸焊墊112稱作非阻焊劑界定之金屬跡線（金屬線）。較佳 地跡線112為銅，其定位於頂表面11 〇a上❶接觸焊墊112 119725.doc
〜以JO 具有可進行導線結合之冶金表面組態；實例為具有較薄鋁 層或錦及金層之表面。
如圖1所示，使用晶片附著材料（較佳為以聚醯亞胺或環 氧樹脂為主之化合物）層12〇而將晶月1〇1之被動表面i〇b 附者至基板附著位置。結合導線13〇(較佳為幻跨越第三組 接觸焊墊112與第二組接觸辉墊1()3之間的距離以電連接基 板110與第-晶片101。如圖1所示，在較佳結構中，將： 131結合至接觸焊墊112且將針腳132結合至接觸焊墊Μ]上 之變形球體1〇4以形成低輪廓導線結合。 圖1指示具有第二大小之第二半導體晶片140之部分。在 :些產品中’第二大小可大致等於第—晶片igi之大小。 晶片140具有在e配第—組焊塾⑽之位置處之中央第四組 接觸焊墊141。接觸焊墊141較佳由銅或銅合金製成且具有 可進仃焊料附著之冶金表面組態。諸如錫或錫合金之回焊 金屬142處於接觸焊墊ι41上。
在圖1之堆疊裝置100中，將第二晶片140置放於第一晶 片ιοί上，使得第四組接觸焊墊141與匹配之第一組焊墊 102上之間隔物1〇5對準。此外，第二晶片之至少一邊緣懸 垂於第二組中之至少一焊墊上之球上。在圖丨之實施例 中，晶片140之懸垂物在兩個焊墊1〇3之經擠壓球上方拉 伸。 亦將第四組焊墊上之回焊金屬142結合至間隔物ι〇5 ;第 二晶片140因此電連接至第—晶片1()卜歸因於由置放於彼 此頂上之變形球體之數目所判定的間隔物1〇5之高度 119725.doc •12· 105a ’第一晶片1〇1與第二晶片ι4〇以寬度為1〇5&amp;之間隙隔 開°此寬度足夠寬以可容納焊墊1 〇3上之低輪廓導線結 合°選擇間隔物之高度105a且因此間隙之寬度1〇5a以滿足 用以形成低輪廓結合連接之結合技術的空間需要。 車父佳地’形成間隔物之變形球體具有大約相等之大小。 使間隔物大體上與第一晶片1〇1之表面垂直地附著至其接 觸焊塾102且自其接觸焊墊1〇2向晶片ι4〇之匹配焊墊141延 伸亦為較佳的。 如圖1所說明，許多裝置實施例得益於以聚合物材料1 50 填充第一晶片1〇1與第二晶片14〇之間的間隙寬度1〇5&amp; ^此 聚合物底部填充材料用於兩個目的：其保護導線13〇至變 形球體104上之針腳式附著132，且其減少間隔物1〇5及焊 接點接觸焊墊141上之熱機械應力。藉由選擇具有已知流 體機械性能（諸如黏度及毛細流動特性）的以環氧樹脂為主 或以聚醯亞胺為主之前驅體化合物，聚合物15〇可大體上 無空隙地填充間隙寬度l〇5a。 圖1進一步描繪保護接觸焊墊丨12及連接結合導線13〇之 囊封材料160。較佳地，此囊封材料為藉由轉移模製技術 而製造之以環氧樹脂為主之模製化合物。 如圖1所示，裝置100較佳具有附著至基板110之表面 11 Ob(與表面i i 0a相對）之回焊主體丨7〇以提供對外部部分之 連接。較佳地，此等回焊主體包括諸如錫或錫化合物之焊 料。焊料化合物170之回焊溫度較佳低於回焊金屬142之回 焊溫度。 119725.doc 1332258
圖2描繪一實施例，其為統稱為2〇〇、包括與另一裝置 201組合的圖1之半導體裝置1〇〇之電子系統，該裝置2〇1倒 裝裝配至半導體裝置1〇〇上。在此實例中，裝置1〇〇之基板 組態為兩個部分：第一部分為圖丨所描述之基板11〇 ;第二 部分210形成囊封化合物16〇之固持壁。部分21〇具有整合 有傳導線211之絕緣基底材料。部分21〇上為具有適於焊料 附著之冶金表面組態之接觸焊墊212。裝置2〇1在匹配接觸 焊墊212之位置處具有回焊主體2〇2。 在圖2中，裝置100之回焊主體17〇附著至外部部分“❹。 本發明之另一實施例為用於製造半導體裝置之方法。圖 3不意性地描繪其處理流程，且圖4至圖7說明該處理流程 之重要步驟。該方法藉由提供具有主動及被動表面之第一 半導體晶圓而始於步驟301，主動表面包括具有内部第一 組及周邊第二組接觸焊墊之裝置。步驟3〇2概述裝置製造 完成之後的背面研磨、抛光及冑衆清洗之晶圓製備技術。
在步驟303中，將黏著材料附著至被動表面上（例如，以 薄膜方式，或藉由旋塗技術卜在步驟3〇4中，將第一晶圓 早一化為具有特定大小之離散的第一晶片。較佳單一化技 術為鑛切。 钱著提供具有 ....... ’、叫六·另附者133 置及環繞㈣置之第三崎觸焊墊。基板之部分展示於面 7中且表示為701。基板可為另一半導體晶片或可具有整名 有傳導線及通道（在圖7中表示為7G2)之絕緣基底材料；第 三組接觸焊墊表示為703。較佳地，第三組焊塾由銅製点 •19725.d〇c 1332258 且具有可進行導線結合之表面（較佳為金層）。 在步驟3〇5中’使用以環氧樹脂為主或以聚合物為主之 晶片附著材料(圖7中之704)將第一晶片之黏著表面附著至 基板之附著位置上；隨後固化附著聚合物。
在步驟306中’將諸如金或銅之非回焊金屬的球置放於 第—及第二組中之每-接觸焊墊上且對其進行擠壓；圖4 中說明此處理步驟。第一晶片4〇1之部分展示為具有由保 護膜402覆蓋的主動表面4〇lae保護膜4〇2中之窗提供至裝 置金屬化4〇3(金屬化為接觸焊墊）之接取；該等窗因此限^ 了接觸焊墊位置》金屬化4〇3較佳由銅合金製成，其在窗 中具有適於導線結合之表面組態；銅可具有適於金導線結 s之鋁合金表面層或鎳層繼之以頂部金層之堆疊（圖4未展 不此等表面層
將形成於自動導線結合器上之第一無空氣球4〇4壓抵裝 置401之接觸焊墊403且將其稍稍壓平。直徑405可在約15 至1 20 μιη之範圍中。在此實施例中，無空氣球由係富金之 合金’然而藉由具有較小百分比之銅及其他金屬之混合物 而硬化之結合導線製成。在習知自動導線結合器中，將導 線（直徑較佳在約15與90 μηι之間）拉直穿過毛細管406。在 導線之尖端，使用火焰或火花技術而產生無空氣球或球 體。球具有自約1.2至1.6倍於導線直徑之典型直徑。將毛 細管移向金屬焊墊4〇3且將球壓抵金屬焊墊。壓縮力（亦稱 作Ζ力或碾磨力）通常在約與75 g之間。在按壓時，溫度 通常在150°C至270°C之範圍中。將經擠壓之球的經燒灼之 119725.doc -15- 尖端表示為404a ;其自裝置表面40 la面向外。 在處理步驟307中，對於第一組焊墊重複球之置放及擠 壓以產生具有高度503之柱狀間隔物。圖5說明此步驟，其 中藉由自動導線結合技術將具有與第一球大約相等之大小 之第二球502以大體上線性序列壓在第一球（現經擠壓且表 示為5 01)之頂部上’較佳使得中心至中心之線大致垂直於 球之赤道平面。可容許自豎直排列之微小偏差。 可重複球之形成及置放以在第一組接觸焊墊上形成具有 面度503之柱狀間隔物’該高度503係基於所選間隙填充材 料之流體力學及待形成之裝置所需的間隙寬度（當將另一 晶片倒裝至第一晶片上（見下文）且用於容納導線結合之空 間需保留時）^經燒灼尖端5〇2a自附著表面4〇la指向外 部。 重複之置放產生具有大約相同高度之間隔物以使得在裝 配堆豐裝置之後，第一與第二晶片以大體上均勻之距離而 隔開。 描繪於圖7之底部部分中之下一處理步驟3〇8提供裝配於 基板701上之第一晶片401與基板701上之第三組焊墊703之 間的電連接。將球形結合7〇5置放於接觸焊墊7〇3上且將 針腳式結合置放於晶片4〇1之第二組焊墊71〇上的經擠壓之 球711上因此使結合導線720跨越於第二組焊塾71〇與第 三組焊墊703之間。導線72〇與球711在針腳處形成淺角係 較佳的。 對於一些裝置應用需要插入如說明於圖6之底部部分中 119725.doc 1332258 之在第一晶片40 1之主動表面上以約等於間隔物高度之高 度6〇la沈積聚合物前驅體材料601之處理，此作為不一步 驟309在^^合之後’聚合物材料保護第二組焊墊上之針 腳式結合且在多晶片裝配之後將減小焊接點處之熱機械應 力。 在步驟31〇中，提供第二半導體晶圓，其包括在匹配第 組焊墊之位置處之中央第四组接觸焊墊。步驟概述 裝置製造完成之後的背面研磨、拋光及電漿清洗之晶圓製 備技術。 在步驟3 12中，向第四組焊墊塗覆回焊金屬。在步驟η] 中，將第二晶圓單一化為具有大致等於第一晶片大小之大 小的離散之第二晶片。較佳單一化技術為鋸切。 如圖6之頂部部分中所說明，步驟314將第二晶片㈣置 放於第—晶片4(H上且使第四組焊墊611與匹配之第一组谭 墊彻上之間隔物對準；在，中藉由穿過料彻及川之 中〜線來&amp;不此對準。在圖6中’將焊塾川上之回焊金屬 表示為612。在對車夕讲^ 隹對旱之過中，第二晶片之至少一邊緣懸 垂於第二接觸焊墊中之至少-焊墊上之球上。 下一處理步驟315提供第二晶片㈣與第-晶片術之間 的電連接。如圖7之頂加八山 頂。卩部分中所說明，施加熱能以回焊 弟四組焊墊 _ 屬612，金屬潤濕第一組焊墊403上 之間隔物且因此將間隔物結入 β 一 至苐一曰日片。雖然第一與第
二晶片因此而電連拉，/ U 但其藉由間隔物之高度503而隔 開，間隔物足夠寬以可 令扁至弟二組焊墊71 〇之導線跨 I19725.doc -17· 如圖7所示，聚合物材料601在冷卻至環境溫度之後填充 間隙寬度503。在處理步驟316中，對堆疊裝置進行電漿清 洗。其後可將裝置囊封於（較佳地）模製化合物（未展示於圖 7中，但說明於圖丨中）中，以使得藉由囊封材料保護導線 結合及基板之至少一部分。 裝配處理流程可進一步包括將回焊主體附著至基板之與 其第一表面相對之表面以提供至外部部分之連接的步驟。 回焊主體之熔融溫度較佳低於使用於第四組焊墊上之回焊 金屬的熔融溫度。 處理流程藉由符號化及單一化經模製之封裝而以步驟 318結束。 雖然已參考說明性實施例描述本發明，但此描述並不意 欲以限制意義而加以解釋。熟習此項技術者在參考該描述 時將易瞭解對說明性實施例之各種修改及組合以及本發明 之其他貫施例。 舉例而言’該等實施例在半導體裝置及具有接觸焊墊之 任何其他裝置中為有效的，該等裝置需經受在基板或隨後 在印刷電路板上之裝配（包括底部填充裝置與基板之間的 間隙之處理）。在另一實例中，半導體裝置可包括基於 石夕、錯化石夕、砷化鎵及製造中所使用之其他半導體材料的 產品。在另—實例中，本發明之概念對於許多半導體裝置 技術節點有效且不限於特定一者。 因此意欲所主張之本發明涵蓋任何該等修改或實施例。 119725.doc 【圖式簡單說明】 圖1說明具有第—半導體曰 該第一半導體Χ置的不意性橫截面， 午導U具有用於導 塾及具有間隔物之另且接…。至基板之-組接觸焊 相等大小之第-曰片之 知塾’該等間隔物允許大約 剩、片之倒裝裝配，同時控制晶片之間的間 圖2為包括與另一 統的不意性橫截面 置上。 裝置組合的圖1之半導體裝置之電子系 &quot;亥另一裝置經倒裝裝配至該半導體裝 圖3展示製造具有如圖^斤 處理流程步驟之示音性方㈣ h日日片的裝置之特定 裝配之曰曰片之門…I、 處理流程借助於控制所 ^ 日日片之間的間隙而組合了導绩έ士入伽為丨壯壯 J导踝結合與倒裝裝配技 術。 圖4至圖7如下而示专料从约nB 0日γ 〜、也說月間隔物及裝置總成之製造 過程的重要步驟： 圖4示意地展示附菩5 a 才者至bb片接觸烊墊的無空氣球之經擠 壓之球體。 圖5示意地展示由晶片接觸烊墊上之兩個經擠壓之無空 氣球所製造的柱狀間隔物之形成。 圖6示意地展示兩個晶片之對準；一晶片具有一用於導 線結合之接觸焊墊及用於柱狀間隔物之另—接觸焊塾。 圖7示意地展示回焊第二晶片上之焊料以結合至第一晶 片上之間隔物，同時將兩個晶片保持為以間隔物之高度而 隔開之處理步驟之後的堆疊裝置，間隔物之高度足夠寬以 119725.doc -19· 1332258 可容納經導線結合之接觸焊墊的導線跨度。
【主要元件符號說明】 100 半導體裝置/堆疊裝置 101 第一半導體晶片 101a 主動表面 101b 被動表面 101c 周邊 102 接觸焊墊 103 接觸焊墊 104 變形球體 105 間隔物/變形球體 105a 高度/間隙寬度 110 基板 110a 第一表面/頂表面 110b 表面 111 傳導線及通道 112 接觸焊墊 120 晶片附者材料層 130 結合導線 131 球 132 針腳/針腳式附著 140 第二半導體晶片 141 接觸焊墊 142 回焊金屬 119725.doc -20- 1332258
150 聚合物材料 160 囊封材料/囊封化合物 170 回焊主體/焊料化合物 200 電子系統 201 裝置 202 回焊主體 210 第二部分 211 傳導線/接觸焊墊 212 接觸焊墊 220 外部部分 401 第一晶片 401a 主動表面/附著表面 402 保護膜 403 接觸焊墊/金屬焊墊 404a 尖端 405 直徑 406 毛細管 501 第一球 502 第二球 502a 尖端 503 高度/間隙寬度 601 聚合物前驅體材料 601a 南度 610 第二晶片 119725.doc -21 - 1332258 611 焊墊 612 回焊金屬 701 基板 702 傳導線及通道 703 接觸焊墊 704 晶片附者材料 705 球形結合 710 焊墊 711 球 720 結合導線 119725.doc -22-

Claims (1)

1. 1332258 申請專利範圍： 一種半導體裝置，其包含： -具有-大小以及一主動及」被動表面之第_半導體 晶片，該主動表面包括在若干焊塾位置處之内部第 及周邊第二組接觸焊墊； 、·’ 一置放於該第-組及該第二組之該等接觸焊塾 回焊金屬之變形球體； 置放於該等第-組焊墊之該等球體上之至少一 形球體’其形成具有一高度之若干柱狀間隔物； 附著位 一具有一第一表面之基板，該第一表面具有 置及接近該位置處之第三組接觸谭塾； 忒第一晶片之該被動表面附著至該基板附著位置； 低輪廓結合導線跨越於該第三組與該第二組之該等輝 墊之間以電連接該基板與該第一 sy 这帛日曰月’該輪廓係低於該 專間隔物之該高度； 八 第一大小及在匹配該第一組接觸浑墊之若干 位置處的第四組接觸焊墊之第二半導體晶片； 該第-晶片置放於該第—晶片上且該等第四組浮塾與 ^等匹配之第―組焊墊上之該等間隔物對準；及 ^在該等第四組焊墊上之回焊金屬，其結合至該等間 二一違連接該第二晶片與該第一晶片，該第二晶月之至 :緣懸垂於該第二組中之至少-烊墊上之該球體 上。 月托項1之裝置，其中該等變形球體具有大約相等之 119725.doc 二求項1之裝置’其中該非回焊金屬包括金。 士 D月求項1之裝置’复中 _ 曰 ’、中。玄第一日日片具有一大致等於該 曰曰片大小之大小。 5.:;第“項1之裝置’其進-步包括-聚合物材料以填充 6哀第—晶片與該第二晶片之間的間隙。 6·:請求項5之裝置’其中該聚合物材料包括一以—環氧 樹脂及聚醯亞胺化合物為主之前驅體。 、 如請求項1之裝置’其中該基板為一第三半導體晶片。 •:請求項7之裝置，其進-步包括附著至該基板… == 目對之表面的若干回焊主體以提供至若干外部 9·求項1之裝置’其進一步包括對該等第三組焊墊與 °亥等連接結合導線以保護材料形成之一囊封。 10· 一種用於製造-半導體裝置之方法，其包含以下步驟： 提供-具有-大小、一主動及—被曰 μ 〜木曰日 ，該主動表面包括具有内部第―組及周邊第二組接觸 焊墊之若干裝置； /供一具有一第一表面之基板，該第-表面具有一附 者位置及接近該位置處之第三組接觸焊墊； 將該第-晶片之該被動表面附著至該基板之該 置上； 一組 一金球； 組之每—接觸焊墊上置放並擠 壓 119725.doc -2 · 對於該第-組之該等焊塾重複該球之置放及擠壓以產 生具有一高度之若干柱狀間隔物； 使若干低輪廟導線結合跨越於該第二組與該第三么且之 該等焊塾之間以電連接該第—Μ與該基板，該輪廟係 低於該等間隔物之該高度； 提供一第二半導體晶片，其具有—第二大小及在匹配 該第一焊墊組之若干位置處具有第四組接觸焊塾之若干 裝置； τ 向該第四組之該等焊墊，或向該等間隔物，或向 塗覆回焊金屬； 考 將該第：晶片置放於該第—晶片上且使該等第四 ，與該等匹配之第―組焊墊上㈣等間隔物對準，以使 Μ第―晶片之至少—邊緣懸垂於該第二組中之至少一 焊墊上之該球上；及 施加熱能以回焊該金屬從而將該等第四組焊墊結合至 該等第一組焊墊上之兮笙王 該第二晶片。之料心物，電連接該第-晶片與 11. 12. 13. =項：Γ法，其在該使該等導線結合跨越之步驟 :後進—步包括以下步驟：在該第-晶片之該主動表I 材料二尚度之高度沈積-聚合物前驅體 材科，從而保護該等第二組焊墊上之該等結合。體 Μ求項10之方法，其進一步包括將 基板之至少一邮八、 守导踝、=口及該 口Ρ刀以一保護材料囊封之步驟。 如請求項10之方法 , ，八中該基板為一第三半導體晶片。 H9725.doc 14.如請求項1()之方法’其中該 線及若干通道之絕緣主體。 整口有右干傳導 15_Π:項1〇之方法，其中該經㈣之金球為-處於金導 線結合中之無空氣球。 16，：：求項15之方法，其中該等重複之金球置放係自處於 導線結合中之無空氣球而產生，從而使該等經擠塵之 球具有大約相等之夫,s &amp;士人s 之大小且結合至一起以形成一柱狀間隔 物。 :求項16之方法’其中該等重複置放產生具有大約相 同咼度之若干間隔物以使得該第一晶片與該第二晶片以 大體上均勻之距離而隔開。 18.如凊求項1〇之方法，其中該第二組與該第三組之該等焊 墊之間的該等導線經置放以使得該球附著至該第三組之 忒焊墊且該針腳附著至該第二組之該焊墊上的該先前置 放之經擠壓之球。 19·如請求項1〇之方法，其進一步包括以下步驟：將若干回 焊主體附著至該基板之與其第一表面相對之表面以提供 至若干外部部分之連接，該等回焊主體之熔融溫度低於 該等第四組焊墊上所使用之該回焊金屬之熔融溫度。 119725.doc
TW096111458A 2006-03-31 2007-03-30 Controlling flip-chip techniques for concurrent ball bonds in semiconductor devices TWI332258B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US78774206P 2006-03-31 2006-03-31
US11/423,035 US7573137B2 (en) 2006-03-31 2006-06-08 Controlling flip-chip techniques for concurrent ball bonds in semiconductor devices

Publications (2)

Publication Number Publication Date
TW200802784A TW200802784A (en) 2008-01-01
TWI332258B true TWI332258B (en) 2010-10-21

Family

ID=38557597

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096111458A TWI332258B (en) 2006-03-31 2007-03-30 Controlling flip-chip techniques for concurrent ball bonds in semiconductor devices

Country Status (3)

Country Link
US (2) US7573137B2 (zh)
TW (1) TWI332258B (zh)
WO (1) WO2007117931A2 (zh)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8012867B2 (en) * 2006-01-31 2011-09-06 Stats Chippac Ltd Wafer level chip scale package system
US9084377B2 (en) * 2007-03-30 2015-07-14 Stats Chippac Ltd. Integrated circuit package system with mounting features for clearance
TWI335652B (en) * 2007-04-04 2011-01-01 Unimicron Technology Corp Stacked packing module
TW201133745A (en) * 2009-08-27 2011-10-01 Advanpack Solutions Private Ltd Stacked bump interconnection structure and semiconductor package formed using the same
US8084853B2 (en) * 2009-09-25 2011-12-27 Mediatek Inc. Semiconductor flip chip package utilizing wire bonding for net switching
US8372692B2 (en) * 2010-01-27 2013-02-12 Marvell World Trade Ltd. Method of stacking flip-chip on wire-bonded chip
TWI409933B (zh) * 2010-06-15 2013-09-21 Powertech Technology Inc 晶片堆疊封裝結構及其製法
US8697492B2 (en) * 2010-11-02 2014-04-15 Tessera, Inc. No flow underfill
US9842798B2 (en) * 2012-03-23 2017-12-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a PoP device with embedded vertical interconnect units
US9837303B2 (en) 2012-03-23 2017-12-05 STATS ChipPAC Pte. Ltd. Semiconductor method and device of forming a fan-out device with PWB vertical interconnect units
US10049964B2 (en) 2012-03-23 2018-08-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units
US8810024B2 (en) 2012-03-23 2014-08-19 Stats Chippac Ltd. Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units
US9524948B2 (en) 2013-09-30 2016-12-20 Mediatek Inc. Package structure
US9627445B2 (en) * 2013-12-05 2017-04-18 Infineon Technologies Dresden Gmbh Optoelectronic component and a method for manufacturing an optoelectronic component
US10734320B2 (en) 2018-07-30 2020-08-04 Infineon Technologies Austria Ag Power metallization structure for semiconductor devices
US9553001B2 (en) * 2015-04-28 2017-01-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a molding layer for semiconductor package
US10163871B2 (en) * 2015-10-02 2018-12-25 Qualcomm Incorporated Integrated device comprising embedded package on package (PoP) device
DE102016122318A1 (de) 2016-11-21 2018-05-24 Infineon Technologies Ag Anschlussstruktur eines Leistungshalbleiterbauelements
US11127693B2 (en) 2017-08-25 2021-09-21 Infineon Technologies Ag Barrier for power metallization in semiconductor devices
US11088055B2 (en) * 2018-12-14 2021-08-10 Texas Instruments Incorporated Package with dies mounted on opposing surfaces of a leadframe
US11031321B2 (en) * 2019-03-15 2021-06-08 Infineon Technologies Ag Semiconductor device having a die pad with a dam-like configuration

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6255208B1 (en) 1999-01-25 2001-07-03 International Business Machines Corporation Selective wafer-level testing and burn-in
JP2001068621A (ja) * 1999-06-21 2001-03-16 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US6483190B1 (en) 1999-10-20 2002-11-19 Fujitsu Limited Semiconductor chip element, semiconductor chip element mounting structure, semiconductor chip element mounting device and mounting method
JP2001127246A (ja) 1999-10-29 2001-05-11 Fujitsu Ltd 半導体装置
JP2001203318A (ja) 1999-12-17 2001-07-27 Texas Instr Inc <Ti> 複数のフリップチップを備えた半導体アセンブリ
JP4439090B2 (ja) 2000-07-26 2010-03-24 日本テキサス・インスツルメンツ株式会社 半導体装置及びその製造方法
TW465064B (en) 2000-12-22 2001-11-21 Advanced Semiconductor Eng Bonding process and the structure thereof
US6815836B2 (en) 2003-03-24 2004-11-09 Texas Instruments Incorporated Wire bonding for thin semiconductor package
US7242097B2 (en) * 2003-06-30 2007-07-10 Intel Corporation Electromigration barrier layers for solder joints
US7071421B2 (en) * 2003-08-29 2006-07-04 Micron Technology, Inc. Stacked microfeature devices and associated methods
US7112524B2 (en) 2003-09-29 2006-09-26 Phoenix Precision Technology Corporation Substrate for pre-soldering material and fabrication method thereof
JP4427298B2 (ja) 2003-10-28 2010-03-03 富士通株式会社 多段バンプの形成方法
JP4580730B2 (ja) 2003-11-28 2010-11-17 ルネサスエレクトロニクス株式会社 オフセット接合型マルチチップ半導体装置

Also Published As

Publication number Publication date
WO2007117931A3 (en) 2008-04-17
US7776653B2 (en) 2010-08-17
US20070228543A1 (en) 2007-10-04
US7573137B2 (en) 2009-08-11
US20090269883A1 (en) 2009-10-29
TW200802784A (en) 2008-01-01
WO2007117931A2 (en) 2007-10-18

Similar Documents

Publication Publication Date Title
TWI332258B (en) Controlling flip-chip techniques for concurrent ball bonds in semiconductor devices
US7420814B2 (en) Package stack and manufacturing method thereof
TWI331382B (en) Stacked package structure and method for manufacturing the same
US8466552B2 (en) Semiconductor device and method of manufacturing the same
US7906855B1 (en) Stacked semiconductor package and method of making same
US20070216008A1 (en) Low profile semiconductor package-on-package
JP4908750B2 (ja) 半導体装置
TW200901435A (en) Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components
JP4758678B2 (ja) 半導体装置
TW200306652A (en) Ball grid array package with stacked center pad chips and method for manufacturing the same
TW201250885A (en) QFN package and manufacturing process thereof
CN206639796U (zh) 半导体器件
US20140374897A1 (en) Thermal interface material for integrated circuit package and method of making the same
TW550768B (en) Flip-chip on film assembly for ball grid array packages
JP2007511101A (ja) Ｌｏｗ−ｋ誘電体含有半導体デバイスと共に使用される電子パッケージング材料
US20210143126A1 (en) Semiconductor package and method of fabricating the same
TWI234827B (en) Semiconductor device and manufacturing method thereof
CN112038305A (zh) 一种多芯片超薄扇出型封装结构及其封装方法
JP7176048B2 (ja) 半導体ダイと受動熱交換器との間に熱界面接合を形成するための装置及び方法
TW200847357A (en) Integrated circuit package with soldered lid for improved thermal performance
US20230260911A1 (en) Electronic device and manufacturing method thereof
TW202002209A (zh) 半導體裝置及其製造方法
US20070080453A1 (en) Semiconductor chip having a bump with conductive particles and method of manufacturing the same
CN113990815A (zh) 一种硅基微模组塑封结构及其制备方法
US20070216003A1 (en) Semiconductor package with enhancing layer and method for manufacturing the same