TWI331383B - Semiconductor package structure, stiffener and method of making same - Google Patents
Semiconductor package structure, stiffener and method of making same Download PDFInfo
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- TWI331383B TWI331383B TW095129894A TW95129894A TWI331383B TW I331383 B TWI331383 B TW I331383B TW 095129894 A TW095129894 A TW 095129894A TW 95129894 A TW95129894 A TW 95129894A TW I331383 B TWI331383 B TW I331383B
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- reinforcing material
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- 239000004065 semiconductor Substances 0.000 title claims description 28
- 238000004519 manufacturing process Methods 0.000 title description 4
- 239000003351 stiffener Substances 0.000 title description 3
- 239000000758 substrate Substances 0.000 claims description 63
- 239000012779 reinforcing material Substances 0.000 claims description 46
- 229910000679 solder Inorganic materials 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 13
- 230000002787 reinforcement Effects 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 10
- 238000004140 cleaning Methods 0.000 claims description 7
- 239000002904 solvent Substances 0.000 claims description 6
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 4
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 239000000945 filler Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 238000007789 sealing Methods 0.000 claims 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims 1
- UDRRLPGVCZOTQW-UHFFFAOYSA-N bismuth lead Chemical compound [Pb].[Bi] UDRRLPGVCZOTQW-UHFFFAOYSA-N 0.000 claims 1
- 239000004020 conductor Substances 0.000 claims 1
- 238000004806 packaging method and process Methods 0.000 claims 1
- 229910052707 ruthenium Inorganic materials 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 48
- 230000003014 reinforcing effect Effects 0.000 description 8
- 239000000853 adhesive Substances 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 7
- 238000005452 bending Methods 0.000 description 4
- 239000003292 glue Substances 0.000 description 4
- 239000011265 semifinished product Substances 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000005429 filling process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 239000012812 sealant material Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 238000005382 thermal cycling Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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Description
1331383 . 九、發明說明: * 【發明所屬之技術領域】 本發明係有關於一種半導體封裝結構及其製造方 法,特別有關於一種半導體封裝結構之加強材(stiffener) 的改良,使得晶片之底部填膠及清潔製程更有效率。 【先前技術】 在微電子工業中》具有積體電路之晶片通常被固定 φ 在封裝載體上,例如基底、電路板或導線架,其可提供 由晶片至封裝外部的電性連接。在覆晶接合(flip chip mounting)的封裝配置中,晶片具有矩陣式的導電接點, 稱為接合墊(bond pads),其電性連接至基底上相對應的導 電接點,稱為錫球(solder balls)或錫錯凸塊(solder bumps)。將錫錯凸塊與接合墊相對應,並以再回流(reflow) 製程使得晶片與基底間形成銲錫接合而產生電性連接。 覆晶接合後晶片與基底之間會產生間隙。 • 晶片和基底通常由不同的材料組成,其熱膨脹係數 不匹配,因此,受熱時晶片和基底之間會產生不同的尺 寸變化,而在晶片和基底之間的電性連接產生熱應力。 若不補償在熱膨脹方面的差異,將使得晶片性能降低, 並損害銲錫接合或使得封裝失效。當晶片尺寸增加時, 在晶片和基底間熱膨脹係數不匹配的效應將更加顯著, 而且在疊層晶片封裝(stacked die package)中,其熱膨脹 係數不匹配的影響亦大於單一晶片封裝,甚至造成晶片 0503-A31843TWF/Kelly 5 1331383 受損。 為了改善覆晶接合中電性連接的可靠度,通常會用 封膠材質或底部填膠(underfiU)填滿晶片和基底間的間 隙。底部填膠會在熱循環或當晶片與基底有明顯溫度差 異時,藉由降低電性連接受到的應力,以增加封裝的疲 勞,命(fatigue life)並改善電性連接的可靠度。底部填膠 可完^密封該間隙,將電性連接處與周遭環境隔離,並 且可提供封裝體適當的機械強度以對抗衝擊及彎曲。底 部填膠更可提供熱傳導路徑以移除晶片產生的熱,如此 可降低晶片與基底間的溫度差異,因此底部填膠可增加 封裝體的壽命。 為了更進一步提升封裝體的剛性,通常會在封裝體 中加入加強材,因為加強材為高剛性材質,可以讓封裝 體比較不會扭曲變形。 、
在傳統的封裝製程中,先將清潔溶劑注入間隙中以 除去殘留的銲錫助㈣,再將底部填膠注人在晶片與基 :間mt、。然而,其缺點為清潔溶劑會被加強材: 録劑務彳絲有效並徹底地完成,當有銲踢助 隙传會造成接下來的覆晶底部填膠層產生空 隙,=最後封以品的品質及可靠度降低許多。 間的間裝:另一缺點為在底部填膠注入晶片與基底 部填膠塗佈部填膠點膠機會被加強材阻礙,使得底 轉^佈製程耗時又不容易徹底完成。 底 此業界亟需一種可克服上述問題之半導體封裴 0503-A31843TWF/Kelly 結構。 【發明内容】 ㈣日f的目的在於提供—種具有導熱加強材的半導 體封裝結構以及其製造方法。 本發明實施例中提供—種半導體封裝結構,包括一 j,具有-正面及一背面;一半導體晶片固定在該基 氐、正面,導熱加強材固定在該基底的正面並包圍該 晶片,加強材具有第一區及第二區,其中第一區丄 區寬’使得點膠機容易進出晶片與基底間的間隙;一底 部填膠層填充在該間隙中並硬化;以及複數個錫球固定 在基底的背面。 *為了讓本發明之上述目的、特徵、及優點能更明顯 易it,以下配合所附圖式,作詳細說明如下·· 【實施方式】 第1圖為傳統覆晶封裝半成品的剖面圖,具有一加 強材固定在基底上。覆晶封裝10包括一晶片30,其具有 上表面32及下表面34; —組錫鉛凸塊40連接至晶片下 表面34的接觸墊(未圖示);晶片3〇固定在晶片3〇下的 第一基底20上;錫鉛凸塊40也連接至第一基底2〇上表 面的接觸墊(未圖示);底部填膠5〇填充在晶片3〇與第一 基底20間,使得覆晶封裝1〇更堅固,保護晶片3〇避免 彎曲受損;一組錫球60固定至第一基底2()下表面的接 觸墊(未圖示),以及第二基底70的接觸墊(未圖示),第 〇503-A31843TWF/Kelly 7 1331383 • 二基底70可以是印刷電路板或此技藝人士熟知之多層印 刷電路板。 a 覆晶封裝10也可包括散熱片80以及加強材2,以避 免封裝體過度扭曲’散熱片80固定在晶片3〇頂端以消 除晶片30產生的熱,並且可抵銷平衡因為晶片3〇與第 一基底20之間熱膨脹不匹配所產生的應力。加強材2藉 由黏著劑5固定在第一基底2〇與散熱片8〇之間,加強 材2的上視圖如第2圖所示,傳統的覆晶封裝1〇可包括 •導熱膠材(thermal interface material,TIM) 120 設置於晶片 30和散熱片80之間,以轉移晶片3〇產生的熱至散: 80 ° … 接下來介紹本發明之實施例,本發明之實施例如第 3、4及5圖所示。第3圖為本發明之一實施例的覆晶封 裝半成品剖面圖’其中加強材固定在基底上。覆晶封裝 11包括第-基底20;加強材3藉由黏著劑5黏著在第一 基底20的上表面;晶片3〇藉由錫鉛凸塊4〇與第一基底 籲20的上表面接合’並且被包圍在加強材3之内;底部填 膠50填充在晶片30與第一基底2〇間的間隙並硬化;以 及複數個錫球60固定在第一基底2〇的背面。 加強材3較佳為具有大的表面積固定至第一基底2〇 上,其有助於在結構上強化覆晶封裝11,避免扭轉及彎 曲。加強材3的尺寸A多由封裝體的大小決定,並且至 少取決於第一基底20的尺寸及形狀。加強材3包括下方 之第區及上方之第二區,其中第一區較第二區寬,因 〇503-A31843TWF/KelIy 8
I33135J 此在加強材3中產生一凹 宭amh u 4。第4圖為依據本發明之一 實轭例的加強材3上視圖 π 過設計’讓點膠機針頭容易進出可經 間的間隙。在本發明之一實曰:〃第-基底20 度約為50〜m叫中’加強材第一區的寬 篦二區的宮痒的* 冋度約為50〜1500/zm;加強材 :度約為5〇〜11000…高度約為50〜1500 A m,然而’熟悉此技蓺 —或π崎 双人士备可瞭解,加強材3的尺寸 e又计疋為了讓點膠機容易進 ^ g 〇a ^ 著劑5固定在加強材的第二,由黏 加強材3具有-開口以3日_其中的晶片3〇。 3 ㈣尺寸取決於晶片_大小,加強材 #納及包11晶片3G°加強材及開口的尺寸最 佳為讓加強材3固定至第一 大,以降低_及料基底2G絲㈣盡可能地 材料加由剛性材質製成’包括金屬、陶竞或含石夕 其中金屬例如為銅。然而’熟悉此技藝人士當可 声的Hit強材3可由任何材料製成,只要能提供足夠程 =懷’使得覆晶封裝U避免彎曲及扭轉。此外,加 係數與第—基底2〇實質相當的材料製 成’且其導熱性可提供高度的散熱效率。 在製造過程中,加強材3組裝定位之後,晶片%可 穿=強材3固定在第一基底2〇的上表面,之後清潔溶 劑:由凹口 4注射入晶片3〇與第—基底2〇間的間隙, 以>月除殘留在間隙中的銲錫助銲齊卜接下來進行覆晶底 〇503-A31843TWF/Kelly 9 1331383 ..’部填膠製程,在晶片30與第一基底20間的間隙中形成 底部填膠50,在底部填膠製程完成之後,為了進一步提 升覆晶封裴11的剛性,如第5圖所示,可利用接著物6 (^attachment)例如環氧樹脂(ep〇xy)以連接加強材3的第一 區及第二區。在另一實施例中,接著物6可以是散熱片 80上的單一組件,固定在加強材的第一區及第二區之 上’以密封其中的晶片30。 由上述對本發明之覆晶封裝丨丨的描述可瞭解,在銲 •錫助銲劑清潔過程中,可以讓清潔溶劑注人機不會被加 強材3阻礙’因為凹口 4可使清潔溶劑更平順地注入晶 片30與第一基底2〇間的間隙,其優點為讓接下來形成 的底部填膠50實質上沒有空隙產生,因此,所完成的封 裝更$保證其品質及可靠度。此外,加強材3中的凹口 4 可使得在晶片與基底間進行底部填膠的點膠機針頭不會 被加強材阻礙,因此本發明之底部填膠製程比傳統製程 更加快速且更容易完成。 # 〜雖然本發明已揭露較佳實施例如上,然其並非用以 疋本發明,任何熟悉此項技藝者,在不脫離本發明之 精神和範圍内,當可做些許更動與㈣,因此本發明之 保護範圍當視後附之申請專利範圍所界定為準。 °5〇3-A3l843TWF/Kelly 10 1331383 -·【圖式簡單說明】 第1圖為習知的覆晶封裝半成品之剖面圖, 有一加強材固定在基底上。 八τ 〃 第2圖為習知的加強材之上視圖。 第3圖為本發明之一實施例的覆晶封裝半成品之為 面圖’其中具有一加強材固定在基底上。 】 第4圖為本發明之一實施例的加強材之上視圖 第5圖為本發明之一實施例的覆晶封裝半成品 • 面圖’其中具有一接著物連接至加強材。 剖 【主要元件符號說明】 4〜加強材的凹口; 6〜接著物; 20〜第一基底; 32〜晶片之上表面; 40〜錫鉛凸塊; 60〜锡球; 80〜散熱片; 2、3〜加強材; 5〜黏著劑; 10、11〜覆晶封裝; 30〜晶片; 34〜晶片之下表面; • 50〜底部填膠; 70〜第二基底; 120〜導熱膠材。 0503-A31843TWF/Kelly 11
Claims (1)
1331383 修正日期:99.5.26 第95129894號申請專利範圍修正本 十、申請專利範園: 1.一種半導體封裝結構,包含: 一基底,具有一正面及一背面; 一半導體晶片,固定在該基底的正面上; 片 -導熱加強材,固定在該基底的正面上且包圍該晶 其中該加強材具有一第一區及一第二區,該第一區 鄰近該基底’該第二區直接設置於該第—區的上表面之 上’且該第一區較該第二區寬; -底部填膠層,填充在該半導體晶片和 的一間隙中並硬化; -间 複數個錫球,固定在該基底的背面上;以及 一散熱片,固定在該加強材的第二區上,以 半導體晶片,其中在該散熱片與該加強材的第—區之: =間具有一凹口,且該凹口介於該半導體晶 加強材的第二區之間。 、 請侧第1項所述之半導體封裝結構,苴 ^加強材第-區的尺寸能夠讓—點膠機容易進出該間 中請專利範圍帛1項所述之半導體封I結構,呈 中該加強材第一區的寬度約為5〇〜 : 50〜150〇#m。 同度約為 4.如申請專利範圍第1項所述之半 中該加強材第二區的寬度約為5G〜U+^體封裝結構,其 50〜15〇〇"m。 11〇〇〇心高度約為 0503-A31843TWF2/Keliy 12 1331383 第95129894號申請專利範圍修正本 C ^ ^ 修正日期·· 99.5.26 中該半導H利㈣第1項所述之半導體封裝結構,其 蛤體Ba片以鍚鉛凸塊接合至該基底。 6.如申料利範圍第〗項所述之半導體封裝 二:接著物用來連接該加強材的第-區及第:區以提 申請專利範圍第6項所述之半導體封裝結構,其 =者物用環氧樹脂(ep〇xy)來連接該加強材的 及第二區。 8. —種加強材,包含: ^ 、第一區及一第二區,其中該第一區較該第二區 見以便一點膠機容易進出一晶片和一基底之間的一間 隙且其中該第一區鄰近該基底,該第二區直接設置於 該第一區的上表面之上,在該晶片與該加強材的第二區 之間產生一凹口。 9. 如申請專利範圍第8項所述之加強材,更包括一接 著物用來連接該加強材的第一區及第二區。 10· —種半導體的封裝方法,包含: 提供一基底’具有一正面及一背面; 將一導熱加強材固定在該基底的正面上,該加強材 具有一第一區及一第二區,該第一區鄰近該基底的正 面該第一區直接設置於該第一區的上表面之上,且該 第一區較該第二區寬’因此產生一凹口在該加強材中; 將半導體晶片固定在該基底的正面上’並且在該 加強材之内; °5〇3-A31843TWF2/Kelly 13 13313.83 第95129894號申請專利範圍修正本 修正日期:99.5.26 片盥:::加強材的凹口注入-清潔溶劑在該半導體晶 片與該基底之間的間隙中; 形成複數個錫球在該基底的背面上;以及 、.將一散熱片固定在該加強材的第二區上,以封 ,導體日日片’其中該凹口在該散熱片與該加強材的^二 之間,且該凹口介於該半導體晶片與該加強 材的第二區之間。 * Π.如申請專利範圍第1〇項所述之半導體的封裝方 在兮半==由該加強材中的凹口塗佈一底部填膠材料 在a體晶片及該基底之間的間隙中。 =申請專利範圍第10項所述之半導體的封裝方 出該間隙該加強材第—區的尺寸能狗讓—轉機容易進 ^^請專_圍第12項所述之半導體的封農方 声^ k加強材第—區的寬度約為m 度約為 5〇〜1500/am。 π =如申請專利範圍第u項所述之半導體的封褒方 ,、中該加強材第二區的寬度 、 度約為50〜 1500“m。 灣〇#m’兩 法,^*^!?Γ第10項所述之半導體的封裳方 ^導體曰日片以錫鉛凸塊接合至該基底。 法,更利範圍第10項所述之半導體的封震方 第二區二:接著物用來連接該加強材的第-區和 0503-A31843TWF2/KeIK J4 1331383 第95129894號申請專利範圍修正本 修正日期:99.5.26 17.如申請專利範圍第16項所述之半導體的封裝方 法,其中該接著物用環氧樹脂來連接該加強材的第一區 及第二區。 0503-A3I843TWF2/Kelly 15
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US10741468B2 (en) | 2011-11-14 | 2020-08-11 | Micron Technology, Inc. | Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods |
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Also Published As
Publication number | Publication date |
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TW200731482A (en) | 2007-08-16 |
US20070145571A1 (en) | 2007-06-28 |
US8174114B2 (en) | 2012-05-08 |
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