TWI325060B - Device with a circuit for detecting an abnormal substrate - Google Patents

Description

1325060 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor test device for conducting semiconductor component testing, and a substrate having one or more connectors is connected to a corresponding counterpart substrate. The way to operate. t I. I *4? a * we are shaped,

In particular, the present invention relates to a skirt having an abnormality detecting circuit suitable for simultaneously using a semiconductor in which a plurality of DSAs having a plurality of socket boards are combined. And a device in which a plurality of substrates constitute a group and connected to a substrate on the other side, which is configured to input a still signal indicating a combination of the plurality of substrates, and has a uniform inconsistency in detecting the combination of the substrates. A comparison mechanism such as a circuit can easily and surely detect that a combination of different types of substrates can be used to prevent a decrease in connector ratio.

[Prior Art] - Gu: For the semiconductor test device for semiconductor parts test, 13 1325060 19429D-Dpif is mounted on a substrate called a socket board by connecting the semiconductor component to be tested, and connecting the socket board In the manner of the substrate on the main body side of the test apparatus, the specific electrical signal output required for the test is input to the socket board through the motherboard, and the semiconductor component is tested. Here, the conventional semiconductor test apparatus is a socket board on which a semiconductor component is mounted and a motherboard on the main body side of the test apparatus, and is electrically connected by metal wire bonding or the like, and the socket board and the main board form an unloadable body. The composition. In such a semiconductor test apparatus in which the socket board and the main board are connected to each other, it is impossible to unload and replace the socket board at a single age, and it is difficult to test various semiconductor parts that are difficult to cope with. In recent years, 'the development of high-density semiconductor parts has progressed' to develop semiconductor components with different package structures or pin structures. When testing various semiconductor components with different structures, it is necessary to interface the components of the material guide 28 The socket board is changed to a pin structure or a package structure corresponding to each semiconductor component. However, since the semiconductor test apparatus of the above-mentioned type is as described above, the seesaw is in the apparatus for reading the core board (4): it is not possible to attach and detach only the socket board, and if different test apparatuses are performed. It seems that the whole of the main board is recorded, such as recording all the materials to sigh the semi-conductor Wei Yu guide ^ new inspection device time, not only test each semiconductor part to guide people, replace the high price of the second test, because of the (four) test results . Therefore, the recent diversification of the significant (four) body parts, by the replacement test to = 7 1325060 19429D-Dpif all parts are extremely difficult. Therefore, in the case of the applicant of the present invention, in Japanese Patent Application No. 2002-047186, the connector is connected by means of a connector that can be freely attached and detached to each other as a connection structure of a socket board and a motherboard in a semiconductor test apparatus. A semiconductor test apparatus for freely attaching and detaching a socket board to a motherboard is proposed. Figure 8 is an explanatory view conceptually showing the semiconductor test apparatus proposed by the applicant of the present application in Japanese Patent Application No. 2002-047186, (a) before the exploded state, the view '(b) is provided with a plurality of socket boards The bottom view of the dsa. As shown in the drawings, in the semiconductor test apparatus, the DSA 110 and the main board 120 on which the plurality of socket boards 111 are mounted are detachably attached. DSA (Device Specific Adapter) 11A A board in which a plurality of socket boards 111 and connectors U4 are mounted and fixed to the SB (socket board) frame 112, and the unit board is integrated. The DSA 110 is a plurality of socket boards arranged on the SB φ frame 112 as a base, and as shown in FIG. 8(b), the bottom side is exposed on the side of the corresponding motherboard 120. The plurality of connections connecting ^ (not shown) are 114. Then, as shown in FIG. 8(a), by mounting the DSA 10 on the motherboard 20, the connectors 14 on the bottom surface of the DSA are respectively fitted and connected to the connector 121 corresponding to the motherboard side. And the plurality of socket boards on the DSA are electrically connected to the motherboard 120. Then, the DSA 110 is mounted on a motherboard in a complex unit of two groups and four groups in order to simultaneously test the semiconductor parts of the same time. The figure 8 (b) shows two ones and eight The configuration status of the DSA110 of the I9429D-Dpif group. According to such a semiconductor test apparatus, since the DSA 110' loaded with a plurality of socket boards 111 can be detachably connected to the motherboard 120 by the connector 114, it can be mounted on the motherboard 2, The DSA11() of the sound, for example, the test package structure surface's material is the same as the semiconductor section k, the DSA110 can be removed from the motherboard 120 (refer to Fig. 8), and the socket is changed to the socket of the semiconductor component to be tested. Board 1 Other DSA110. Therefore, in the semiconductor test apparatus, the test of different types of semiconductor components can be performed by replacing the DSA on which the socket board is mounted alone, without replacing the entire device including the motherboard as in a conventional device. A low-cost and versatile semiconductor test device is now available. However, the semiconductor test device that can be displayed on the side of the motherboard is as described above. (4) (4) A half of the material of the shirt, there will be a plurality of dsa loaded with the same socket plate on the main board. Since the shape of the DSA and the appearance itself are the same in general, even if the type and structure of the socket board to be mounted are different, there is a case where the unit cannot be distinguished by the unit. Therefore, two or more DSAs having different _ or constructed socket boards may be loaded on the same motherboard in combination with errors. When the DSA carrying different types of socket boards is mounted on the same motherboard, the socket structure of the semiconductor parts and the socket board to be tested may not be suitable. If the semiconductor parts are directly mounted, there will be an IC socket and a socket guide. Physical components such as components (semiconductor parts) or replacement parts for components are subject to physical damage, etc. The DSA error is set to be 1325060 I9429D-Dpif.

Here, it is possible to prevent the use of a combination of misplaced DSAs of such different types of socket boards, for example, it is conceivable to form pins and pin holes in the DSA frame or to form concave and convex shapes, and to make pins and bumps only between the correctly combined DSAs. Shape bite. However, in the method of mounting the unevenness or the fitting structure in the DSA frame as described above, it is necessary to change the fitting structure according to the type of the socket plate, and each time a different type of semiconductor component is tested, it is necessary to redesign and manufacture the DSa frame. The problem. Do not ifG 1 1 ^ / \ 柩媸 肷 肷 肷 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 DS DS DS DS DS DS DS DS DS DS DS DS DS On the other hand, as shown in Fig. 8, the DSA loading and unloading type semiconductor test apparatus is arranged on the frame and a plurality of the plurality of seat plates and connectors are unitized (refer to Fig. 8(b)), and There are several connectors in one DSA, and there are many connections in the corresponding domain _ crying = connecting the DSA to the motherboard, connecting to the socket board and the motherboard

Evening connections may result in poorly fitted or poorly connected conditions. , * Then, when such a connector is connected poorly, the test of the Yifa hoist will be suboptimized, and the efficiency of the squad will be low. +...The reliability of the test device is reduced from the above-mentioned latitude and longitude. For example, if DSa uses the same type of substrate with the correct combination, the substrate is repeatedly loaded and unloaded between the substrates, and the majority is placed, or the 1325060 I9429D-Dpif is good. Developed a new way to effectively prevent the above problems. Therefore, the applicant of the present invention has further elaborated the invention and created the invention of the present invention, which can surely prevent the erroneous installation of the plurality of substrates as described above, and also reliably find the conduction failure between the plurality of connectors.

The present invention has been developed in order to solve the above problems, and is a device in which a plurality of substrate configurations/groups are connected to each other, and an ID signal indicating a combination of the plurality of substrates is input, and is detected. The comparison mechanism such as the matching circuit of the substrate combination can easily and reliably detect the combination of different substrates, and can prevent breakage or failure of the substrate, the socket, or the mounted component due to the erroneous mounting of the substrate. In particular, in order to provide a device with an abnormality detecting circuit, it is suitable for simultaneously using a test device in which a plurality of DSAs having a plurality of socket boards are combined. You have one or two of the goods, and one or more of them: = base::

The signal transmission connector transmits a signal and detects the corresponding connection (four) ^ key circuit 'and easily and surely detects the connection is not protected by the connector to provide - abnormal detection ===, especially 'has Multiple Connections _=Boards [Description of the Invention] As disclosed in claim 1 of the patent application, in order to achieve the above object, 1325060 I9429D-Dpif · » The apparatus with the substrate abnormality detecting circuit of the present invention has a combination of a plurality of substrates At least one set of the substrate group and the device for connecting the other side substrate of the substrate group, and the ID setting substrate is mounted on each of the substrate groups to set a specific ID number assigned to the substrate group And outputting an id signal indicating the ID number; the ID signal input substrate is mounted on the other side substrate corresponding to the substrate group, and each ID signal output from the still-setting substrate is input; and a comparison mechanism is input from the foregoing Π3 signal inputting each ID signal outputted by the substrate, comparing the ID signals of the corresponding base plates; and detecting the abnormal combination of the substrates in the substrate group Composition. According to the apparatus of the present invention having the substrate abnormality detecting circuit, a comparison mechanism such as a matching circuit including a Π3 setting substrate ′ and an ID signal outputted from the erbium setting substrate is used. 'Only the number of the two or more substrates indicating the constituent substrate group is equal to the specific group & the ID number can be input from each substrate, and the matching is determined to be inconsistent. Therefore, it is not necessary to change the configuration or the outer shape of the substrate, that is, φ can determine the combination of the plurality of substrates by the ID number unique to the substrate group, and it is easy and sure to detect the combination of different types of substrates, and it is possible to reliably prevent the erroneous loading. Damage, malfunction, etc. of the substrate, the socket, or the mounted component caused by the etc. By using the ID signal input from the substrate side as described above, it is possible to determine the consistency of the combination by judging whether or not the combination of the substrates is correct, and determining the consistency of the combination on the same day τ on the mounting side. The determination process is more rapid, and the original substrate 12 325060 l9429D^Dpif industry, processing & μ n stomach can be efficiently carried out by placing the substrate on the device, and the specific substrate group can be given the 1D number even if the substrate is increased or decreased. It is possible to realize an abnormality detecting circuit which is easy to use for the use of the melon and expandability. Attached to the second aspect of the present invention, there is provided a substrate having a connector connected to the substrate, and a substrate having a connector, and a daisy chain circuit and a substrate of the other side substrate. The connector input signal is transmitted to the entire link via:: side_ or the above signal, and the connector will sequentially measure the aforementioned riding and pairing signals, and the system checks. "The connection of the connector is abnormal. According to the apparatus of the present invention configured as described above, the daisy chain circuit via one or two r-substrate abnormality detecting circuits is provided, and when the two-tone = 士, all the connectors transmit signals abnormally, etc. At the same time, it can be detected immediately, and the two rooms have poor connection and connection between the connectors, and the connection is not detected. The signal is transmitted to the connector between the boards, and the method of '" When the connection is found to be poorly connected, etc., it is possible to carry out the original operation and processing quickly and efficiently. The connector between the substrates is connected, so that even if the number of blouses is found, the connection is poor or falls off. Wait, but every day. It is still easy and sure to connect poorly and cause malfunctions. Oxygen is now a kind of device that will not be connected by connectors. High reliability such as low business rate 13 1325060 I9429D-Dpif Further, as disclosed in claim 3, the apparatus with a substrate abnormality detecting circuit of the present invention has a plurality of substrates combined with a connector and configured Substrate the substrate side of the device a set of groups, and the connector includes a connector connected to the substrate of the substrates of the other group, and which includes setting the substrate .ID 'are respectively mounted in each of the groups of the substrates yl

The board sets a specific ID number assigned to the substrate group, and rotates an ID signal indicating the D number; the ID signal input substrate is mounted on the other side substrate corresponding to the substrate group, and the input is output from the ID setting substrate. Each of the signals; the comparing means inputs the still signals outputted from the first signal input substrate, and compares the still signals of the respective substrates; and the daisy chain circuit, from the opposite side substrate or the substrate a connector input signal transmits the sequential signals to all the connectors via the respective connections H, and detects the hot output signals; and detects the abnormal combination of the substrates in the substrate group, and simultaneously detects the substrate and the opposite substrate The connection of all connectors is abnormal. According to the substrate abnormality detecting electric device of the present invention having such a configuration, a comparison mechanism such as a circuit for determining the ID number of the substrate group is provided, and a method of detecting a connection failure path of the connector is performed. The substrate can be detected and the connector can be detected. The connector connection between the wire board and the other side substrate can be used in combination with a plurality of substrates, and each substrate has a plurality of devices connected to the side of the square. Will give the ro number and indeed the floor ^ 妾 ^ often ' at the same time can easily find the connection of most connectors; =, provide a versatile, expandable and reliable high reliability. Progress 1325060 • I9429D-Dpif The device having an abnormality detecting circuit as disclosed in claim 4, wherein a plurality of the ID signal setting substrates are mounted on the substrate, and the plurality of ID signal setting substrates are provided by the plurality of ID signal setting substrates. The configuration of the ID number of the substrate is set and output.

According to the apparatus with the substrate abnormality detecting circuit of the present invention configured as described above, the plurality of ID signal setting substrates are provided, and all the numbers set by the plurality of ID signal setting substrates can be configured to form one ID number' and can be configured. The number of the substrates to be used, the type, and the like are freely set to an arbitrary ID number. Therefore, even when the type or the number of the substrates is increased or decreased, the ID number and the like can be more easily added, deleted, or changed, and an abnormality detecting circuit having excellent versatility and expandability can be further provided. A device having an abnormality detecting circuit as disclosed in claim 5, wherein one or more pins of the connector of the substrate and the other substrate are attached to the substrate and the opposite substrate The configuration of the daisy chain circuit is connected by a short circuit.

According to the apparatus of the present invention having the substrate abnormality detecting circuit constructed as described above, the connector is provided by a connector provided between the substrates connected to each other. The daisy chain circuit of the present invention for transmitting signals via all connected devices can be constructed by short-circuiting the pins in the substrate. Therefore, there is no need to add another circuit or mechanism, etc., which can be caused by the daisy-key circuit of the present invention, the connection failure of a plurality of connections (4), the connection abnormality, and the like, without requiring large-scale and complicated bases. It is possible to provide a highly reliable device that can detect the connection failure between the earth-filling boards in advance. ',,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, One or two or more socket boards are composed of dsa. The other side substrate is composed of a motherboard on which the semiconductor test apparatus of the dsa is mounted and connected. Furthermore, the apparatus according to claim 7 is characterized in that the substrate is provided by one or more socket boards having semiconductor components loaded and connected with the test object. The DSA constitutes a "substrate group" in which a plurality of substrates composed of the above-described dsa are combined, and the other side substrate is composed of a main board in which a plurality of DSA semiconductor test devices constituting the substrate group are integrally mounted. According to the apparatus with the substrate abnormality detecting circuit of the present invention thus constituted, the substrate of the present invention is regarded as a 5: 5, and the other side substrate is configured as a host board on which the DSA is mounted, and The substrate group of a plurality of substrates is configured as a DSA group having a plurality of DSAs, and the AI-removable semiconductor semi-conducting device can be regarded as the device of the financial abnormality detecting circuit of the present invention. Therefore, it is possible to easily detect the error 'or the connector is detached or the contact failure, etc., by using the abnormality detecting circuit of the present invention by separately replacing the semiconductor test device of the dsa having the socket board and the test for the various semiconductor components. It can provide a semiconductor test device for the occurrence of a bad installation or installation failure and a test for a reliable limb. L Bay & Mode] 至^第图图' ah illustrates a difficult implementation of the apparatus of the present invention with a substrate different suspension detecting circuit. 1325060 19429D-Dpif · The diagram of the invention is not the invention - the decomposition of the semiconductor test device with the base circuit of the implementation type. The side of the motherboard is removed - the front view

Bottom view. ^DbA is not shown in the drawings, the substrate abnormality detecting circuit of this embodiment is a connector which is mounted on the same surface of the substrate,

The plurality of connectors on the other side of the substrate are: useful for: 复 mounting a plurality of socket boards for semiconductor components. The field is connected to the semiconductor test device of the motherboard 2 of the other side of the mysterious DSA10. Then, this embodiment is provided with an abnormality detecting circuit for detecting that the connector of the DSA1G erroneous HDSA_ motherboard 2() in the semiconductor test apparatus is not connected. (semiconductor test device)

First, a semiconductor test apparatus constituting the apparatus having the substrate abnormality detecting circuit of the present embodiment will be described with reference to Figs. 1 and 2 . As shown in the figure, the semiconductor test apparatus of the present embodiment has substantially the same configuration as the semiconductor test apparatus shown in Fig. 8, and includes a socket board 11 on which a semiconductor component (not shown) to be tested is mounted. The DSA 10 is formed in a detachable manner on the motherboard 2, and a test device capable of corresponding to different types of semiconductor components is formed by merely replacing dsda]0. As shown in Fig. 1, the DSA (Device Specific Adapter) 1 has a plurality of socket boards 11 and a connector 14 17 I9429D-Dpif J ",, 乂® (t〇') on the bottom side of the socket board. Since the plurality of socket boards u and the paired connections & 14iT and the body unit are formed into a substrate, the DSA is usually formed in units of -, unloaded, replaced, etc. The DSA unit of Suihua handles the amount of the dumping amount, for example, about packaging, construction or (4) making different semiconductor parts, preparing to replace the socket board corresponding to the unit 2, * to unload in the city, set the ride in the semiconductor The DSA of the part is tested for various semiconductor parts. Then, the DSA loading and unloading type semiconductor test device is formed in a group of DSAs that can have the same configuration of the socket board in one motherboard. Four sets of equal D s A are used as a set of loads, and the test of the half-those's body can be carried out at the same time. As shown in Fig. 1, this embodiment adopts two DSA10s (DSA). -A10a and DSABlOb) as a group, the two groups of DSA10 The integrated loading and connection of the DSA 10 in the present embodiment is a plurality of socket boards 11 arranged on a frame-shaped SB frame (socket frame) 12 serving as a base substrate, and In the frame space of the sb frame 12, a connector 14 is provided which is connected to each of the socket boards 11. Each of the socket boards 11 is provided with a component mounting portion which is electrically connected to a semiconductor component to be tested. The substrate of the (socket portion) is configured to have one semiconductor component mounted on each of the socket plates 11. Then, the plurality of socket plates 11 are respectively mounted and fixed on the frame portion of the frame 86. The SB frame 12 is made of metal. The frame member configured as described above has a complex space (see Fig. 2(b)). As shown in Fig. 2, this embodiment has one row of 8 18 I9429D-Dpif 'total 16 space regions. Then, as As shown in Fig. 2(b), the inner air of the SB is housed with a connector connected to the socket board 11]. ^, as in "back: Fig. 2, the DSA10 of the present embodiment The SB box]2 has a space area of 2 lines and 1 line, and has 2 points in each of the total space areas. The insertion of money]1 means that the connection should be 32 in total. However, the number of the socket board 11 connected to the gram 14 and the frame 12 are not particularly limited. The way to find the connector Η is as described above. And the connecting core is disposed on the bottom side of each of the plug wires, and the corresponding plug 1 on the teacher 12, (4) is on the same plane on the side of the plug wire, and corresponds to the side of the motherboard 2 () Connection (4) (refer to Fig. 1) simultaneously has all the connectors attached and detached. Therefore, when the connection on the DSAU side is 14 and the connector 21 on the side of the motherboard 20 is not fully fitted and connected, the connector is formed. The connection is poor, and the connection failure of the connector is detected by the germination circuit 4 后 which will be described later. As shown in Fig. 1, each of the socket boards mounted on the frame 12 has a rectangular shape in which the base plates of the socket boards are notched, and the frame portion of the frame 12 is exposed from the notched portion. The exposed portion is formed with a positioning hole 15 that is inserted into the positioning pin 22 that is protruded from the side of the main board 20. The DSA 10 is positioned and fixed at a specific position on the motherboard 2 in such a manner that the positioning hole 5 is inserted into the positioning pin 22. Here, in the present embodiment, the positioning holes 15 (and the positioning pins 22) are formed at two places on the left and right in the longitudinal direction of the SB frame 12 (refer to FIG. 2), but as long as the DSA 10 is positioned at a predetermined position, the setting position can be set at any position. The pin 22 is located in the positioning hole 15' and the number is not particularly limited. 1325060 I9429D-Dpif Further, as shown in Fig. 2, the SB frame 12 is in a region of the plurality of connectors 14 which does not interfere with the connector arrangement surface. The ID number of the DSA 10 is set, and the ro setting substrate 13 indicating the Π3 signal of the ID number is provided. The details of the ID setting substrate 13 will be described later.

Then, 'the DSA10 series consisting of the above configuration is combined with two DSA-A10a and DSA-B] Ob loaded with the same configuration of the socket plate 当作 as a group, and the two priests are still loaded one by one. On the motherboard 2〇. That is, the present embodiment corresponds to the type of the DSA1〇 and the socket board of the two sets, for example, set to "DSA-A and B", "DSA_C and D" or "DSA_E".

And F"...', in combination with two DSAs 10 loaded with the same configuration of the socket board. Therefore, at this time, for example, the combination of "still eight-eight and still eight-seven" or "DSA_B and DSA-D" will cause different types of socket boards to be loaded on the motherboard 2, for the combination of DSA10 abnormal. Then, by the ID setting substrate 13 described later, the circuit 30 is double-measured to determine the inconsistency of the combination of the s Xuan D S A10.

As shown in Fig. 1, the motherboard 2 is attached to a substrate mounted on the semiconductor test apparatus = body side, and as described above, a plurality of connectors 2 corresponding to the DSA 10 side of the plurality of socket boards n are provided. (See the day g] map). The DS (4) is connected to the motherboard 2G through the connection port, and the predetermined electrical signals required for the test are outputted to the hidden side through the motherboard 20 to perform the test of the semiconductor components on the socket boards 11. Then, the present embodiment is attached to the contact pin substrate 23 which is in contact with the upper surface of the motherboard 2 without interfering with the plurality of connectors 21, and the substrate for the Dsa_^id setting substrate. The __substrate 23 is finely described as follows with the ID setting substrate 13 on the side of the 20 1325060 19429D-Dpif DSA10. In the present embodiment, the portion shown as the motherboard 2 is generally included in the main body of the semiconductor test device, including the SPCF, the metal plate, the working characteristic substrate, the common substrate, and the like. As will be described later, in the present embodiment, the abnormality detecting circuit is mounted on the common substrate 20a in the motherboard 2A. Therefore, the "main board" of the present embodiment is detachably connected to the unitized <DSA1" to indicate the other side substrate of the present invention. Further, although the detailed description is omitted, the configuration and function of the semiconductor test apparatus of the present embodiment are the same as those of the existing semiconductor test apparatus except for the above-described DSA1 & Lu motherboard. "ID setting substrate" Next, the id setting substrate 13 of the present embodiment will be described with reference to Figs. 3 and 4 . Fig. 3 is a cross-sectional front view showing a principal part of the ID setting substrate 13 and the contact pin substrate 23 of the present embodiment. Fig. 4 is a block diagram conceptually showing the relationship between the ID setting substrate 13 and the 1) matching circuit 30 of the present embodiment. φ The ID setting substrate 13 shown in the drawings is provided with an ID number indicating a combination of each DSA 10 (DSA-A and B, DSA-C, and D..), and the ID number is indicated by an output. The substrate of the ID signal is mounted on the side of the connector of the DSA10. The ID setting substrate 13 is disposed in a region where the connector arrangement surface of the SB frame 12 does not interfere with the plurality of connectors 14. As shown in Fig. 2, this embodiment is in each DSA 10 (l〇a, L〇b) Eight ID setting substrates]3 are provided. 21 1325060 19429D-Dpif Then, the contact pin substrate 23 serving as the substrate for the ro signal input is mounted on the side of the motherboard 2 facing the setting substrate 13. As shown in Fig. 1, the έ 接触 contact pin substrate 23 corresponds to each of the X) setting substrates 3, and corresponds to each of the two DSAlOa and l〇b, respectively, for a total of 6 contacts. Similarly to the ID setting substrate 3, the pin substrate 23 is disposed in a region that does not interfere with the plurality of connectors 21 of the motherboard. Therefore, when the DSA 10 is mounted on the motherboard 20, correspondingly; [the ID signal output pad 13a of the D setting substrate 13 and the contact pin 23a of the contact pin substrate 23 are in contact with each other, as will be described later, after loading the DSA 10 At the same time, the 'K can be signaled' is automatically output to the id-in circuit 30. As shown in Fig. 3, each of the ID setting substrates 13 is disposed on a surface facing the main board 20 side of the DSA 10 by a fixing mechanism such as a bolt, and has two pairs of ID signal output pads on the surface of the fixed substrate. 13a. A pair of ID signals The output fresh pad 13a is connected to the pair of ID number setting pads 13c on the inner surface side (DSA10 side) of the substrate through the through holes 13b. Each ID number setting pad 13c is connected to the GND pad 13e via the jumper 13d. The GND pad 13e is transmitted through a conductor pattern (not shown), and is grounded, for example, to a bolt for fixing the ID setting substrate 13. Then, the ID number setting pad 13c can be set to GND or OPEN depending on whether or not the jumper wire 13d is connected to the GND pad 13e. Specifically, when the ID number setting pad 13c is set to GND (connected to the GND pad 13e), the ID signal output pad 3a is outputted to the signal of the ID-inducing circuit 30 described later, and the input side is grounded. LOW (〇). On the other hand, when the ID number setting pad 13c is set to OPEN (non-22 19429D-Dpif, at the GND pad 13e), the signal from the still signal output pad]% is output to the still circuit 30, by the ID The power supply voltage vcc of the circuit 3 is formed to HIGH(]) (refer to FIG. 5). In the ID setting substrate 13 of the present embodiment, the tfi number output from the still signal output pad 13a connected to the numbering pad 13 is switched to the tfi number according to the presence or absence of the connection % wiring 13d. LOW ( 〇) /HIGH (]). However, by setting an arbitrary L 〇 W (°) / HIGH (1) signal to the ID = fixed substrate 3, the still signal indicating the desired 1 number can be input to the ROS circuit 3 (refer to 4 picture). Here, as shown in Fig. 2, in the present embodiment, eight Π) setting substrates 13 are disposed in each of dsaIO ( ] 〇a and 〇b), and each ID setting substrate 13 has two ID signal outputs. Solder pad i3a. Therefore, the ID number of the ID setting substrate 13 can be set to be a 16-bit signal in a group of DSAIOs (10a, 10b). However, in the present embodiment, the 16-bit signal is included. The 14-bit signal of the upper (or lower) is assigned as the 1:) signal indicating the ID number. For example, the ID number indicating the combination of "DSA-A and B" is regarded as "00000000000001", and the ro number indicating "DSA-C and 〇" is regarded as "00000000000010", etc., and can be arbitrarily within the range of the Μ bit Give the ID number. Then, as shown in Fig. 4, the 14-bit ID signal is output from each DSAlOa, 10b, and is passed through the contact pin substrate 23 on the motherboard 20 side to the ID-inducing circuit 30. Then, the number of bits of the ID signal indicating the ID number of the DSA 10, and 23 1325060 19429D-Dpif are not limited to the 14-bit case in the present embodiment, and can be arbitrarily set corresponding to the type of the DSA 10 11 can be changed according to the number of required bits:) The number of setting substrates 13 or the number of output pads. For example, when the semiconductor test device of the DSA 10 is used, the number of IDs becomes one, so that the signal of '0 bits' can be given 1024 IDs. Therefore, in the case of the ID setting substrate 3 of the present embodiment, the ID setting substrate having the number of outputs of "2" is sufficient as long as each of the DSAs is installed in each of the DSAs. On the other hand, when 10,000 kinds of DSA10 semiconductor test devices can be used, the ID number must also be one. As in the present embodiment, the ID of 16384 modes can be assigned by using the 4-bit signal method. Numbering. As described above, the id setting substrate 13 of the present embodiment can be arbitrarily set as the ID signal by assigning the number of allocations, the number of output bits, or the number of bits that can be used as the ID signal. Then, the setting of the id number of the board 13 for the setting of the Ro is preferably performed before the assembly of the DSAIO, and after setting the type of the socket board 1 mounted on the DSA 10, the setting is the same in the corresponding two groups. The ID number setting substrate 13 is mounted on a predetermined location of the DSA 10. In addition, the 1:) number of the setting is usually not changed afterwards, and the DSA10 is incorrectly installed due to an inadvertent ID change. Therefore, as shown in this embodiment, it is expected to use a bolt or the like. The setting substrate 13 is fixed to the DSA 10 side and mounted so as not to be detachable. (ID-to-Circuit Circuit) Next, the ip-matching circuit 30 of this embodiment will be described with reference to FIG. Fig. 5 is a detailed circuit diagram showing the ID of the present embodiment. As shown in the figure, the ID-inducing circuit 30 of the present embodiment detects a set of 24 1325060 I9429D-Dpif fSAlO (1〇a, 1〇b) which is a non-conforming circuit' as a comparison I. Signal ratio agency. In this embodiment, each of the input and the ribs is still «the 14-bit id signal input by the substrate 13 is used. Specifically, as shown in FIG. 5, the ID-inducing circuit 30 is composed of 14 XOR circuits and hgN0R circuits and one octave; ^1) circuit which are inserted into each 14-bit signal. Each of the 14-bit signals input from the ID setting substrate 13 of each DSAlOa and i〇b is compared with the corresponding bit, and the HIGH (1) signal is output only when all the bits match, and the other cases are output. L〇w (〇) signal. Therefore, when the combination of the DSA 10 mounted on the motherboard 2 is detected and the different types of DSA 10 are combined, since the abnormal signal (L〇w (〇) signal) can be output, the corresponding abnormality can be performed. deal with. In the present embodiment, as will be described later, the locking mechanism of the DSA 10 is locked on the side of the main board 2, and the display cannot be locked. Then, in the present embodiment, the ID-inducing circuit 30 is mounted on the common substrate 2〇a on the side of the motherboard 2 (refer to FIG. 4 and FIG. 7), and when the still signal is not detected, As will be described later, the common substrate 2A is treated as a rID signal. °~ Xing Moreover, the comparison mechanism for comparing the ID signals can also adopt the configuration other than the ID of the present invention. That is, the comparator can use any circuit or device as long as it can detect that a different type of DSA is combined by comparing the ID signals. (Daisy Chain Circuit) ^ Next, the daisy chain circuit 4 of the present embodiment will be described with reference to FIG. Figure 6 is a conceptual representation of the daisy chain circuit of the embodiment of the present invention. 25 ^^5060 19429D-Dpif έ 明 明 如 如 , 雏菊 雏菊 雏菊 雏菊 雏菊 雏菊 雏菊 daisy On the side of the _ side, the connector 14 on the D (10) side (the sixth picture is used to sequentially connect the signal transmission domain board 2G and the job data.), and the circuit for detecting the presence or absence of the output signal is detected. , 2, 14 ' Road _ will be the motherboard 20 side of the connector 21 two _ = ^

If the corresponding sales are shouted __, the order = ^ and the transmission line is formed. Therefore, as shown in Fig. 6, the implementation is wrong by the connection of the connector 21 on the motherboard 20 side and the connection on the 1 side. ^ — A pin short circuit, and all connectors are connected in series.

First, the two pins of each connector 21 (the male pin in Fig. 6) are assigned to the daisy chain on the side of the motherboard 2, and one is regarded as the wheel entry side and the other is regarded as the output side. Then, the daisy chain output pin of one of the connectors 21 is connected to the adjacent connector 21 through the short-circuit line, and the daisy chain input pin of the other connector 21 is connected. Moreover, the two pins of each connector, 4 (the female pin in Fig. 6) are also assigned to the daisy chain, one is regarded as the input side, the other is regarded as the output side, and the connector is In the description 4, the input side and the wheel exit side are connected by the short-circuit line 14a. Then, the daisy key pin in each of the connectors 21 and 14 can be used with an empty pin or the like which is not used in each connector, and can also be used exclusively for the daisy chain. According to the daisy chain circuit 40, the input side and the output side of the daisy key circuit 40 are turned on only when all the connectors corresponding to the side of the motherboard 2 and the DSA 10 side are normally connected, and when any connector has a connection failure , the shape of the 26 丄J厶19429D-Dpif into the daisy 鍅 snow smash into the m / key circuit 40. Therefore, 'in the way of the daisy chain circuit 40: the way of crying 2 1 pressure' and the connection of the connector, when all the s s touch bad, the normal signal (high (i) signal), ^ output The signal can be detected whether the connector corresponding to the motherboard 20 side and the SA10 side is all mounted on the motherboard 20 side, and the connector connection between the motherboard 20 side and the DsAi side is abnormal. Then, the output signal from the daisy chain circuit 4 is applied (f is shown in Fig. 7), and as will be described later, the same signal is used to determine whether there is an abnormality in the common substrate. It is handled as an abnormality in Daisy Chain. Then, in the present embodiment, the daisy-chain circuit 4 is configured to distribute the two pins of the connector on the main board paste and the DSA G side to the daisy-chain, but it is not particularly limited to two pins. In other words, the daisy chain circuit 4 can form a transmission line by sequentially connecting all the connectors on the main board 20 side and the D S A10 side in series, and the number of pins or the connection method used is not particularly flawed. Therefore, for example, when the DSA 10 and the motherboard 20 are provided with a coaxial connector, the SIG line can be distributed on the input side of the daisy chain and the GND line can be distributed on the output side so that the SIG line and the GND line of the coaxial connection can be short-circuited. , into circuit 40. In addition, this embodiment performs the round-in and output of the daisy-chain circuit 4A on the side of the motherboard 20, but the input and output signals to the daisy chain circuit can also be performed on the DSA10 side. % (common substrate) 27 1325060 I9429D-Dpif Next, the common substrate 2A of the present embodiment will be described with reference to Fig. 7. Fig. 7 is a block diagram conceptually showing a common substrate 20a in the semiconductor test apparatus with the substrate abnormality detecting circuit of the present embodiment. As shown in FIG. 7, the common substrate 2A of the present embodiment is mounted on the substrate on the side of the motherboard 20, and has an output signal input from the daisy chain circuit 4, and is input to the ID setting substrate 13 at the same time. The π) coincidence circuit 30 of the transmitted ID signal. then. As shown in Fig. 7, the common substrate 2〇& has an H@AND circuit for inputting the output signals of the daisy chain circuit 40 and the ID-inducing circuit 30, and the input

The daisy chain abnormal signal input unit 34 of the output signal of the daisy chain circuit 40 and the ID number abnormal signal input unit 35 of the output signal of the input ID circuit 3 are input. The AND circuit 33 outputs a 5 (No. 2) signal indicating that there is no second line only when the input from the daisy chain circuit 40 and the ROS circuit 30 is HIGH (1), that is, a normal signal. ). With this circuit, the output signal is detected, and the DD of the DSA 10 is not detected, and the DSA] and the main branch: the connection of the king of the board 20 is poorly connected, and "no abnormality" is performed.

The control embodiment outputs "no abnormality" from the AND circuit 33, and controls the locking mechanism of the DSAi lock on the side of the motherboard 2 to be locked (LOCK). On the other hand, when the daisy chain abnormal signal input unit 34 or the ID number abnormality input unit 35 is in the signal (10) (7) of the input, and the # abnormal signal, the signal indicating that there is a sensation is not displayed. Therefore, it is detected that the connection between aDSA]0 and the main smear=〇 思 connection state is poor, or the 1D of the DSA10 has an inconsistent monthly value of $1, although the "Daisy Chain has an abnormality" or "the ID number is abnormal" 28 ^25060 19429D- Dpif is processed. In this embodiment, the locking mechanism of the DSA1 lock on the side of the motherboard 20 is controlled to be in an unlockable state (niEE@) by the "abnormal" signal, and the equivalent of "Daisy (3) is abnormal). Or the "1 is a number of LEDs" such as LEDs, and an abnormality will be notified to the outside of the device. (Anomaly Detection Operation) Next, an abnormality detection operation in the semiconductor test apparatus with the substrate abnormality detecting circuit of the present embodiment configured as described above will be described. - First, two sets of DSAs 10 are prepared, mounted on the pre-wired position of the motherboard 2, and fitted, connected to the connector 21 on the motherboard 10 side and the connected state 14 of each DSA 10. ID of each DSA10 when the DSA10 is loaded on the motherboard 2. Further, the signal output substrate 13a of the substrate 13 is brought into contact with the contact pin 23a of the contact pin substrate 23 on the side of the corresponding main board 20, and an id signal indicating the ID number of the DSA 10 is output. The output ID signal is rotated into the coincidence circuit 30 of the common substrate 2〇a via the contact pin 23a, and the ID signal of the DSA 10 is compared and detected to be consistent. The result is an AND circuit input to the common substrate 2〇a. 33 and ID number abnormal signal input unit 35. Moreover, when the DSA 10 is mounted on the motherboard 20 and the connectors of the DSA 10 and the motherboard 20 are connected to turn on the daisy chain circuit 40, the daisy chain signal is output, and the AND circuit 33 of the common substrate 2A is turned on and The daisy chain abnormal signal input unit 34. Then, in the AND circuit 33 of the common substrate 20a, when the signal input from each circuit is HIGH (1), that is, the normal signal, a signal indicating "no abnormality" (HIGH (1) signal) is output. 29 1325060 I9429D-Dpif Therefore, there is no inconsistency between the two groups of the motherboards 20 mounted on the motherboard 20, and all the connectors of the DSA 10 and the motherboard 20 are normally connected, and there is an abnormal state. The locking mechanism of the DSA]0 on the side of the motherboard 20 will take care of (LQCK) DSA1G. (4) Tests on semiconductor parts using DSA10 and motherboard 2 in a hybrid state. On the other hand, when the daisy chain abnormality signal input unit 34 or the number abnormal signal input unit 35 inputs LOW (0) ', that is, the abnormal signal, the dSA 〇 and the arbitrary connection of the motherboard 20 (4) have a connection not (four) shape. And the combination of the DSA 10 loaded on the host board 20 has an abnormality, and the output indicates that there is an "abnormal" signal. Therefore, 'the processing is equivalent to "Daisy Chai_Exception" or "ID number is abnormal". That is, 'the locking mechanism that locks the DSA 10 on the side of the motherboard 20 is controlled to be not in the locked state (FREE), and the LED corresponding to the abnormality of the r Daisy Chain or the "ID number is abnormal" is turned on, An exception notification device will occur. Hey. Therefore, in this state, the semiconductor test apparatus cannot be used, and the semiconductor test is not performed in a state where the dysfunctional D S A10 is directly mounted on the motherboard 2 ’ or the partial connector is poorly connected. As described above, the apparatus having the substrate abnormality detecting circuit according to the present embodiment includes the substrate 13 for the setting which indicates the combination of the DSAs 10, and the consistency of the signals outputted from the substrate 13 for still setting. Still, the circuit 3G is given, and the predetermined ID number is given, and only if the (four) job numbers are consistently inconsistent, it can be determined whether the two sets of DSA1 are the predetermined combination. Therefore, the unique 30 19429D-Dpif ID number is given to each DSA 10 without changing the configuration or shape of the DSA 10, and it is possible to discriminate whether the DSA 10 combination is appropriate or not, and to easily and surely detect the 1DSA10 error. It is possible to reliably prevent breakage, malfunction, and the like of the socket, the mounted component, and the like caused by the erroneous mounting of the DSA 10. 'Ding only Y is the tenth, "Ai U detect the ID tfl number found" and determine whether the combination of the DSA10 is correct, so it can be judged that the combination is appropriate while loading the DSA 〇 on the side of the motherboard 20 Whether or not, the determination process can be performed quickly and can be performed efficiently and efficiently. In addition, this embodiment is based on the input of a signal from the side of the DSA1 and is set to 5 female Δ 1 Γ» 4 people. When π mm .. , 轼 π 俄 极 恻 可 可 可 可 可 可 可 可 可 可 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Moreover, since the combination of the DSA and the specific DSA1 can be given to the ro number, if the number or the number of the test is increased or decreased, the generality and the expansion of the abnormality can be realized by adding or deleting the (4) correspondence. And motherboard 2. There is a bad connection between the connectors and the connector: even if the road is connected to the temple, it can be detected immediately. 4. Check: connect 2 :: connector, Judging whether there is;; board, half Qing ◦ Luo Xun 'can be achieved - the species will not be connected. Now the connection is poor or the work is poor or the operation efficiency is low, etc. = the connection is caused by the connection type with the ID In particular, the soft circuit 30 and the daisy chain circuit 4〇's square 19429D-Dpif type can positively detect the combination abnormality of the DSA10, and can detect the connection between the DSA10 and the motherboard 20. Therefore, the semiconductor test device in which a plurality of DSAs are combined and each DSA 10 has a plurality of connectors 14 is given a 1] 3 number and a combination of DSA 10 is reliably detected. In many connection states, the connection is poor, and a semiconductor test device with high reliability and high expandability is provided. The device with the substrate abnormality detecting circuit of the present invention is exemplified by a preferred embodiment. Explain However, the apparatus having the substrate abnormality detecting circuit of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. For example, the above-described embodiment is only for setting the substrate. It is used to set and output the ID number of a group of DSAs, but it can also be used as a number setting mechanism for setting and outputting any number used for other purposes. That is, the above-mentioned embodiment is setting and outputting the substrate for ID setting. The 2-bit signal is used as the 1st signal indicating the number of the 1-bit signal. For example, if the ID setting substrate is set to be configurable and the 6-bit signal is output, the 2-bit signal is used. The element can be used as the π) signal of the present invention, and the remaining 4 bit parts can be allocated as other signals. Therefore, for example, it can be input as an object to be used, and an arbitrary serial number, user number or management can be set. A numbering mechanism such as a number, and the semiconductor test device shown in the above embodiment is a group that performs DSA detection by means of an ID matching circuit and a daisy chain circuit. In addition to the abnormality, the detection of the connector connection failure 19429D-Dpif between the DSA and the motherboard is also performed, but of course, only one of them can be provided. In the above, in the known state, it is determined that the ID is consistent. Whether or not the substrate group is: and 3 is limited to 2 grazing-groups, and it is considered to be the case 'but it is not possible. Similarly, it is required to be: two - wide after 1 Detecting a connection with a bad connection and crying for a long time ^ The daisy chain circuit check is only between the connected substrates; t: set = kiss... /, each connector can be used. 'The above-mentioned Besch type is a semiconductor test. The splicing of the connector and the connector of the motherboard are taken as an example to illustrate the base of the present invention: the plug-and-pull test circuit, but the use of the present invention is not limited to the cast test device having the cover plate. ^The substrate is attached with the substrate abnormality detecting circuit. The main board is connected to the other side of the board. 2^, the combination of more than one is connected to the other side of the substrate device with the corresponding connector. A substrate or a device can be used. [Industrial Applicability] W [In the present invention, a device having a substrate abnormality detecting circuit, a device connected to a plurality of substrates, and a device connected to the other substrate, t is shown to indicate a combination of the plurality of substrates. In the method of the Liao) signal, it is possible to easily and surely detect the case where a different type of substrate is used in combination by using a comparison mechanism such as a matching circuit of the combination of the h/th and the 5 hai substrate. Therefore, y is protected against damage, malfunction, and the like of the substrate, the socket, or the loaded component caused by the erroneous mounting of the substrate, and is particularly suitable for simultaneously using a semiconductor test device in which a plurality of DSAs having a plurality of socket boards are combined. 1325060 19429D-Dpif For the purpose of inventing a device for detecting a substrate abnormality detecting circuit, a substrate having one or more connectors is connected to a corresponding one or more connectors (four), which are provided by Connected, all connected to H and transmitted signals to detect the output of the signal, the off-network key circuit can easily and surely detect the poor connection or disconnection of the connector of the dm. Therefore, it is possible to prevent the operation of the connector due to poor connection of the connector or the semiconductor test device having the motherboard and the socket board which are connected to the plurality of connectors at the same time. [Embodiment] Fig. 1 is an exploded perspective view showing a semiconductor test apparatus with a substrate abnormality detecting circuit according to an embodiment of the present invention. Fig. 2 is a view showing a semiconductor test apparatus with a substrate abnormality detecting circuit according to an embodiment of the present invention, wherein (a) is a DSA shown in (a) before the DSA state is removed from the motherboard side. Bottom view. Fig. 3 is a cross-sectional front view showing a principal part of an ID setting substrate and a contact pin substrate in a semiconductor test apparatus with a substrate abnormality detecting circuit according to an embodiment of the present invention. Fig. 4 is a block diagram conceptually showing an ID setting substrate and an ID-inducing circuit in a semiconductor test apparatus with a substrate abnormality detecting circuit according to an embodiment of the present invention. Fig. 5 is a detailed circuit diagram showing an ID-inducing circuit in a semiconductor test apparatus with a substrate abnormality detecting circuit according to an embodiment of the present invention. Fig. 6 is a view conceptually showing a daisy chain circuit in a semiconductor test apparatus with a substrate abnormality detecting circuit according to an embodiment of the present invention. 34 1325060 I9429D-Dpif diagram. Fig. 7 is a block diagram conceptually showing a common substrate in a semiconductor test apparatus with a substrate abnormality detecting circuit according to an embodiment of the present invention. Figure 8 is a diagram conceptually showing the semiconductor test apparatus proposed by the applicant in Japanese Patent Application No. 2002-047186, (a) before the DSA state is removed from the motherboard side, and (b) is ( a) The bottom view of the DSA shown. Φ [Main component symbol description] 10, 110 DSA (component designation adapter)

10a DSA-A

10b DSA-B 11, 111 socket board 12, 112 SB frame 13 ID setting board 13a ID signal output pad 13b via hole 13c ID number setting pad 13d jumper 13e GND pad 14, 21, 114, 121 connection 4a, 21a short-circuit line 15 positioning hole 20, 120 main board 35 1325060 19429D-Dpif 20a common substrate 22 locating pin 23 contact pin substrate 23a contact pin 30 ID circuit 33 AND circuit 34 daisy chain abnormal signal input unit 35 ID number abnormal signal input unit

40 daisy chain circuit

36

Claims (1)

19429D-Dpif X. Patent application scope: 1. A component designation adapter (DSA), including: a socket board frame; a plurality of socket boards mounted on the socket board frame; and a plurality of connectors, and a plurality of sockets Each of the boards is connected and mounted on a socket board as described above; wherein 'the aforementioned DSA is detachable for a motherboard of a semiconductor test apparatus. 2. The component-designated adapter of claim 1, wherein each of the plurality of socket boards has a notch shape in a square corner, and the socket board frame is shaped from the gap when the plurality of socket boards are mounted The exposed portion has a positioning hole for inserting a positioning pin protruding from the side of the main board. 3. A component designation adapter (DSA) comprising: a plurality of socket boards 'loading and connecting semiconductor components to be tested; and a plurality of connectors; wherein 'the combination of a plurality of DSAs is connected to the other side substrate The component specifying adapter further includes an ID setting substrate for assigning a specific id number to the combination of the plurality of DSAs, and outputting an ID signal indicating the ID number and detecting other DSAs among the plurality of DSAs. Whether the ID signals are identical to each other; each of the plurality of ID setting substrates includes: an ID setting substrate mother board; 1325060 !9429D-Dpif a pair of ID signal output pads, which are provided in the aforementioned ID setting substrate mother board a surface of the other side substrate; a pair of ID number setting pads connected to the pair of ID signal output pads and disposed inside the ID setting substrate mother board; and a GND pad for grounding; the plurality of IDs Each of the setting substrates is set according to whether the jumper is connected to the aforementioned ID number and the aforementioned GND pad, and the ID will be used Number setting pads or GND is set to OPEN, HIGH or LOW and the output signal. 4. The component specifying adapter according to claim 3, wherein the substrate for setting the ID is fixed by a plug, and the GND pad is grounded to the bolt. 38