TWI292484B - Device with a circuit for detecting an abnormal substrate - Google Patents
Device with a circuit for detecting an abnormal substrate Download PDFInfo
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- TWI292484B TWI292484B TW094143705A TW94143705A TWI292484B TW I292484 B TWI292484 B TW I292484B TW 094143705 A TW094143705 A TW 094143705A TW 94143705 A TW94143705 A TW 94143705A TW I292484 B TWI292484 B TW I292484B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
- G01R31/2808—Holding, conveying or contacting devices, e.g. test adapters, edge connectors, extender boards
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
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- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
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Description
129娜 九、發明說明： [發明所屬之技術領域】 本發明係關於一種如用以進行半導體零件試驗之半 導體試驗裝置般，具備一個或二個以上連接器之芙 連接在對應之對方侧基板的方式而動作之裝置。土 尤其，本發明係關於一種具備異常檢測電路之裝置， 適於同時使用組合有複數具備複數插座板之DSA的半、導體 試驗裝置，其巾，複數基板構成—㈣連接 ^裝^其係以輸人表示該—組基板之组合的仍訊號:方 式，猎由具備檢測該基板組合的一致不—致令— 了=易且_刪組合使用僵:基板 t載令件导破知、故障等。 ’本發明係關於—種具備異常檢測電路之裝置， 適於具備同時連接有複 ：= 衣置 導體試驗裝置，ι中，n 之主杬板和插座板的半 的裝置，II由具備經由連接的之對方侧基板 出該訊號之輪出結果的 ^傳廷訊號且檢測 容易且石崔實地檢測出=chain)電路之方式，而 亦可防患因連接器之、車：接為之連接不良或脫落等， 率低落等。 不良所造成的動作不良或作業效 【先前技術】 一般:而言， 進行半物料試驗之半導賴驗裝置， 6 129纖 將當作試驗對象之半導體零件裝載於稱為插座板之 i之美^將義座板連接在試驗褒置本體側之稱為主機 輸《入】S板透=機;，驗所需之特定電性訊號 主插座板，而進仃半導體零件之試驗。 之插Γ之半導麟料置，絲輪料體零件 等_板’藉由金屬線或銲錫 可分之:成機板形成不能裳卸之-體不 之習知之以在 板和主機板連接成—體不可分 而產生=對應多樣化之各種半導體零 近年來’隨著半導體零件 =的問禮。 展，開發有多數封裝體構造或銷 ㈣度化之進 而試驗各種構造不同之半_@ t问之半導體零件， 二導體零件之銷: 了上述，裝置本二之^ 種若進“ 試驗裝置。 、/、置換已3主機板之全體 如此必須置換全體裝置之以 於導入新的额裝置須耗費時間==置，由 且必須依照各半導體零件來導 矿間長期化， 因此導致增加試驗成核㈣f源科=償^驗裝置， 近多樣化進展顯著之半導體零 ^ =此’關於最 千軋由置換試驗裝置來對 l29mi 應所有之零件係極為困難之事。 因此，本案申請人精心研究之後，在曰本特願 2002-047186號中，藉由採用可互相地自由裝卸而連接之連 接器，作為半導體試驗裝置中的插座板和主機板等之連接 構造，而提出一種使插座板可相對於主機板自由裝卸、置 換之半導體試驗裝置。 第8圖為為概念性地表示本案申請人在該曰本特願 2002-047186號中提出之半導體試驗裝置的說明圖，⑷ 響為分解狀態之前視圖，（b)為具備複數插座板之DSA底視 圖。如該等圖式所示，在該半導體試驗裝置中，裝載有複 數插座板111之DSA110和主機板120係以可自由裝卸方式 構成。 DSA( Device Specific Adapter:元件指定轉接器）11〇 係複數個插座板111及連接器丨14裝載、固定於§8(插座板） 框112，且一體單元化之插座板之基板。 5亥D S A110係複數個插座板111排列在當作基極之s b ❿框112上，同時如第8圖（b)所示，在底面側露出有嵌合在 所對應之主機板120側之連接器（省略圖示）的複數個連接 态Π4。然後，如第8圖（a)所示，藉由將該DSA11〇裝載 在主機板120上，DSA底面之各連接器114分別嵌合、連接 在主機板側對應之連接器121，且DSA上之複數座板ιη 係黾性連接在主機板120。然後，DSA11〇為了同時地試驗 多數半導體零件，相同構成之DSA係以2個一組、4個一組 之複數單位而裝載於一個主機板上，第8圖（b)表示2個一 129 娜, 組之DSA110之配設狀態。 根據如此之半導體試驗裝置’由於裝载有複數個插座 板111之DSA110,可藉由連接器Π4而以可自由裝卸方式連 接在主機板120，因此可在主機板12〇裝卸、置換任意之 DSA110 ’例如試驗封裝體構造或銷構造不同之半導體焚件 時，可從主機板120取下DSA110 (參照第8圖（a) ^令且 變更成裝載對應於試驗對象之半導體零件之插座板U1的 其他DSA110。 因而，在該半導體試驗裝置中，以僅單獨置換裝載有 插座板之DSA的方式，可對應不同種類半導體零件之試 驗，而不須如習知裝置般置換包含主機板之全體裝置等， 1實現一種低成本且泛用性佳之半導體試驗裝置。 然而，可在主機板側裝卸DSA之半導體試驗裝置係如 上所述，由於同時地試驗多數半導體零件，因此會有在主 枝板上裝載複數個裝載有相同種類之插座板的DSA之情 形。由於一般而言DSA之外形、外觀本身相同，故即使裝 載之插座板種類、構造不同時，亦有無法以DSA單位加以 區別之情形。因此，具備不同種類或構造之插座板的二個 以上之DSA，可能會組合錯誤而裴載於相同主機板上。 裝載有不同種類之插座板的DSA裝載於相同主機板 上時’當作試驗對象之半導體零件和插座板之插座構造會 不適合’若如此直接搭載半導體零件的話，會有1C插座、 插座導件、元件（半導體零件）或元件置換用之置換件等 產生物理性破損等之慮。因而，如此之DSA錯誤裝設有必 129¾¾ 要 加以防範。 此處，防止使用組合錯誤之裝載有如此不同種類之插 座板的DSA之機構，例如可考慮在DSA框體形成銷和銷孔 或形成凹凸形狀，僅在正碟組合之DSA間，使銷和凹凸形 狀咬合。但是，如此在DSA框體裝設凹凸或嵌合構造之方 法，必須依照各插座板種類而變更嵌合構造，且每次試驗 不同種類之半導體零件時，會產生必須重新設計、製造〇;§八 框體之問題。 而且，如此在DSA框體裝設嵌合構造或凹凸，或安裝 銷時，DSA框體之厚度會變薄，而有強度性變弱之問題。 另一方面，如第8圖所示，DSA裝卸型之半導體試驗 裝置係於框體上排列一定數量之複數個插座板及連=二= 予以單元化（參照第8圖（b))，且在一個DSA二3 固連接器，而在對應之主機板側亦具備多數個連接器。 ^將DSA裝卸在主機板時，連接_座板和 多數連接器會產生嵌合不良或連接不良之情形。間的 ^然後，產生如此之連接器連接不良等時，無 吊的試驗，作章六令'八亞/μ , …、 仃正 低之慮。 惡化，同時有試驗裂置之可靠性降 在必上ί經緯’如DSA裝卸側之半導體試驗裝置， t :、組口热誤之相同種類基板（DSA)之带置弋 在基板間反覆裝卸、嵌合多數連接哭 =置，或 板之錯誤裝設、錯誤使料或連㈣之連接不良Γίίΐ 129¾賊 良等情形，而期待開發出一種得以有效地防止上述問題之 新方法。因此，本案申請人進一步精心研究之後，劍作 出本案發明，可確實地防止如上述之複數基板之錯誤装設 等，同時亦得以確實地發現複數連接器間之導通不良等。 本發明係為了解決以上之課題而研發者，其係複數個 基板構成一組而連接在對方侧基板之裝置，以輸入表乔該 -組基板之組合卿訊號之方式，藉由具備檢測出該基板 組合的一致不一致之一致電路等比較機構，可容易且確實 地檢測出組合使用不同基板之情形，並可防範因基板之錯 誤裝設所造成的基板、插座或搭载元件等破損、故障。尤 其，^提供一種附有異常檢測電路之裝置為目的，其適用 二、、同時使用組合有被數個具備複數插座板之Dsa的半導體 試驗裝置。 柯鴨具備—個或二她上連接ϋ之基板連 壯^具備對應之-個或二個以上之連接器的對方側基板之 具備經由連接的全部連接器傳送訊號且檢測出 =就之輪出絲之_鏈轉，而Μ且確實地 連接不良或脫落等，並且可防範因連接器 以提供所造成的動作不良或作業效率低落等，尤其， 備同時連拯異¥檢測電路之裝置為目的，其適用於具 驗裳置。彳复數個連接β之主機板和插座板的半導體試 [發明内容】 為了達成上述目的，如申請專利範圍第㈣所揭示， 1292)4^^ 本發明之㈣基板異常檢測電路之裝置，係具有組合有複 數基板而構成的至少-組之基板群，以及連接絲板群: 對^侧^之裝置’且其具備：ID設定用基板，分別裝設 在刖述基㈣之各基板，設定賦予該基板群之特定1〇編 號，同時輸出表示細編號之10訊號；仍訊號輸入基板， 裝設在對應於㈣基板群m彳基板，且輸人從前述仍 設定用基板輸出之細訊號；以及比較機構，.㈣述 id訊號輸人基板輸出之細訊號，比較所對應之前述各基 板之ID訊號；且其係檢_述基板群巾祕板 之構成。 …吊 根據如此之構成之本發明_有基板異常檢路 =衣置’以具備ID設定用基板，和用以檢測從該仍設定用 訊號的一致性之一致電路等比較機構之方 1 μ賦卞表tf構成基板群之二個以上的基板符合特定组 a jID編號，而可從各基板輸入該Πλ編號，且比較、判定 致不—致。因此，不須變更基板之構成或外形等，即 J =由基板群固有之πχ編號判別複數基板之組合，容 確只地撿測出組合不同種類基板之情形，而可確 因錯誤裝料錢縣、插座或 之 故障等。 〈礙才貝、 且，藉由如此從基板側輪入1〇訊號的方式，而以判定 基板之組合是否正確的方式，可在將該基板裝载於裝設側 的同Β守，判斷該組合之一致性，而可進行更迅速的判定處 理，且有效率地進行將基板裝載於裝置而進行之本來的= 12 129 购 fl 業、處理。 板且，由於可賦予仍編號而特定基板群，即使增減基 應，，^數1時，仍可藉由附加、刪除iD編號而容易地對 w現一種泛用性、擴張性佳之異常檢測電路。 附有里Γ方面，如申請專利範圍第2項所揭示，本發明之 具備連二檢測電路之裝置係具有具備連接器之基板，以及 置，且龙i亥基板之各連接器的連接器之對方側基板之裝 基板之：：=離菊鍵電路’其係從前述對方侧基板或前述 訊號傳逆到iit'輸入訊號’經由對應之各連接器將順序 測前述==，並檢測有無輸出訊號，且其係檢 成。 ？方侧基板之全部連接器之連接異常的構 壯罢據如此構成之本發明的附有美柘© $ &、， 衣置，以具備經由一個或二個以卜有基板兴吞松測電路之 之雛菊鏈電路的式告 之王部連接器傳送訊號 異常等時，可立=二有連接不良、連接 f接的連接器間而檢測出連接不二，訊號傳送到如此 板間的連接器之同時，判定式’可在連接基 發現連接不良等， 、…、μ不良情形，而可迅速地 而進財來之作業y處=效率地進行連接基板間之連接器 地^同時連接多數連接器時，仍可以曰卜 叫現連接不良或脫落等 〗仍了奋易且確實 連接不良而造成的動作不良ϋ種不會因連接器之 的裝置。 a作業政率低落等之可靠性高 Ι29^Μί 基板專利範圍第3項所揭示，本發明之附有 數其/欢一电路之裝置，係具有組合有具備連接器之複 群：Ϊ:構成的至少一組之基板群，以及具備連接該基板 1 口土板之連接器的連接器之對方側基板之裝置，且立 設定用基板，分別裝設在前述各基板群之各基 予該基板群之特定ID編號，同時輸出表示該仍 群’IDm號輪入基板，裝設在對應於前述基板 穿，卜私侧基板，輪入從前述iD設定用基板輸出之各ID訊 穿=械構輻入從4述iD訊號輸入基板輸出之各ID訊 4: 讀應之，述各基板之ID訊號；以及雛菊鏈電路， 有^山口 ^接器將順序訊號傳送到全部連結器，並檢測 且檢測前述基板群中的基板之組合異常: 常。丁取測則述基板及對方側基板之全部連接器之連接異 根據^此構成之本發明的附有基板異常檢測電路之 二:猎由具備判定賦予基板群之ID編號的—致性之 电路等比較機構，以及檢測連接 路的方式，確實地娜板上===鍵電 ::板;;對方侧一 :側之iii板且各基板具備複數個連接器而連接在對 转视二τ谷易地％現夕數連接器之連接不良，進—牛 k供一種泛用性、擴張性佳之可靠性高的裳置。進步 14 129视i 然後’尤其如申請專利範圍弟4項所私不之附有兴常 檢測電路之裝置，其中，在前述基板裝設有複數個前述ID 訊號設定用基板，且藉由該複數個ID訊號設定用基板，而 ό又疋、輸出該基板之一^固ID編號之構成。 根據如此構成之本發明的附有基板異常檢測電路之129 Nine, invention description: [Technical Field of the Invention] The present invention relates to a semiconductor test device for conducting semiconductor component testing, in which one or more connectors are connected to the corresponding opposite substrate. The device that operates in a way. In particular, the present invention relates to a device having an abnormality detecting circuit, which is suitable for simultaneously using a semi-conductor test device in which a plurality of DSAs having a plurality of socket boards are combined, and a plurality of substrates are formed, and (four) are connected to each other. The input signal indicates the still signal of the combination of the substrate: the mode, the hunting has the consistency of detecting the combination of the substrate - the order is - the easy and the combination is used: the substrate t carries the command to break the knowledge, fault, etc. . The present invention relates to a device having an abnormality detecting circuit, and is adapted to be provided with a device for simultaneously connecting a half of the main conductor plate and the socket plate of the composite conductor test device, i, n, and II. The other side of the substrate out of the signal of the round of the results of the signal and easy to detect and Shi Cui real detection = chain) circuit, but also prevent the cause of the connector, the car: connected to the poor connection Or fall off, etc., the rate is low. Poor operation or work efficiency caused by failure [Prior technology] In general: For the semi-conductive inspection device for semi-material testing, 6 129 fiber will be used as the semiconductor component of the test object. The tester board is connected to the main body side of the test fixture, which is called the main unit input "input" S board pass through the machine; the specific electrical signal main socket board required for the test is taken, and the semiconductor component is tested. The semi-guided material placement, the wire wheel material parts, etc. can be divided by metal wire or solder: the formation of the machine plate cannot be unloaded - the body is not known to be connected to the board and the motherboard - Inseparable to produce = Various semiconductors corresponding to diversification in recent years 'With the semiconductor parts = gift. Exhibition, development of a majority of package structure or pin (four) degree and then test a variety of different structures _@ t ask the semiconductor parts, the sale of the two-conductor parts: the above, the device of this two into the "test device. , /, replacement of all three motherboards, so it is necessary to replace the entire device to introduce a new amount of equipment to take time == set, and must be in accordance with each semiconductor parts to lead the long-term lead, resulting in increased test nucleation (4) f source section = reimbursement device, near diversification of significant semiconductors = ^ This is extremely difficult for the most thousand rolling by the replacement test device for all parts of l29mi. Therefore, after careful study by the applicant of this case In the Japanese Patent Application No. 2002-047186, a connector that can be freely attached and detached to each other is used as a connection structure of a socket board and a motherboard in a semiconductor test apparatus, and a socket board is provided to be relatively A semiconductor test apparatus for free loading, unloading, and replacement of a motherboard. Fig. 8 is a conceptual view of a semiconductor guided by the applicant in Japanese Patent Application No. 2002-047186. (4) is a front view of the exploded state, and (b) is a bottom view of the DSA having a plurality of socket boards. As shown in the drawings, the semiconductor test apparatus is loaded with a DSA 110 of a plurality of socket boards 111. The motherboard 120 is detachably mounted. The DSA (Device Specific Adapter) 11 is mounted on a plurality of socket boards 111 and connectors 14 and fixed to the § 8 (socket board) frame 112. And a unitized socket board substrate. 5Hai DS A110 is a plurality of socket boards 111 arranged on the sb frame 112 as a base, and as shown in Fig. 8(b), the bottom side is exposed. a plurality of connection states Π4 of connectors (not shown) on the corresponding motherboard 120 side. Then, as shown in FIG. 8(a), by loading the DSA 11A on the motherboard 120, the DSA The connectors 114 on the bottom surface are respectively fitted and connected to the corresponding connector 121 on the motherboard side, and the plurality of seat plates on the DSA are connected to the motherboard 120. Then, the DSA 11 is used to test most semiconductor components at the same time. The same composition of the DSA system is 2 one 4 sets of multiple units are mounted on one motherboard, and Figure 8(b) shows the configuration of two 129 dinars, the DSA110 of the group. According to the semiconductor test device, there are multiple The DSA 110 of the socket board 111 can be detachably connected to the motherboard 120 by the connector , 4, so that any DSA 110 can be detached and replaced in the motherboard 12 ', for example, a semiconductor package with different test package structure or pin structure In the case of the device, the DSA 110 can be removed from the motherboard 120 (refer to Fig. 8 (a) and changed to another DSA 110 in which the socket board U1 corresponding to the semiconductor component of the test object is mounted. Therefore, in the semiconductor test apparatus, the test of different types of semiconductor components can be performed by replacing only the DSA on which the socket board is mounted, and it is not necessary to replace all the devices including the motherboard as in the conventional device. A low-cost and versatile semiconductor test device. However, the semiconductor test apparatus in which the DSA can be mounted on the main board side is as described above, and since a plurality of semiconductor parts are simultaneously tested, a plurality of DSAs loaded with the same type of socket boards are mounted on the main board. Since the shape of the DSA and the appearance itself are generally the same, even if the type and structure of the socket board to be loaded are different, there is a case where the DSA unit cannot be distinguished. Therefore, two or more DSAs with different types or configurations of socket boards may be combined and placed on the same motherboard. When a DSA loaded with a different type of socket board is mounted on the same motherboard, the socket structure of the semiconductor component and the socket board to be tested may not be suitable. 'If the semiconductor component is directly mounted, there will be a 1C socket, a socket guide, A component (semiconductor part) or a replacement for component replacement may cause physical damage or the like. Therefore, such a DSA error must be guarded against the necessary 1293⁄43. Here, to prevent the use of a combination of wrong DSA mechanisms loaded with such different types of socket boards, for example, it is conceivable to form pins and pin holes or form concave and convex shapes in the DSA frame, and only between the DSA of the positive disc combination, the pin and The concave and convex shape is bitten. However, in the method of installing the unevenness or the fitting structure in the DSA casing, it is necessary to change the fitting structure in accordance with the type of each socket plate, and it is necessary to redesign and manufacture the flaws each time a different type of semiconductor component is tested; Eight-frame problem. Further, when the DSA housing is provided with the fitting structure or the unevenness or the mounting pin, the thickness of the DSA housing is reduced, and the strength is weak. On the other hand, as shown in Fig. 8, the DSA loading and unloading type semiconductor test apparatus is arranged such that a certain number of socket boards are arranged on the frame and connected = two = unitized (refer to Fig. 8 (b)), and In a DSA two 3 solid connector, there are also many connectors on the corresponding motherboard side. ^When the DSA is loaded and unloaded on the motherboard, the connection_seat and most of the connectors may cause poor fitting or poor connection. ^ Then, when such a connector is connected poorly, etc., there is no hanging test, and the chapter six orders '八亚/μ, ..., 仃 are low. Deterioration, at the same time, the reliability of the test rupture is reduced. The latitude and longitude 'such as the DSA loading and unloading side of the semiconductor test device, t:, the group of the same kind of substrate (DSA) is placed between the substrates, Most of the fittings are connected to the crying, or the wrong installation of the board, the wrong material or the connection of the (4) is poor, and it is expected to develop a new method to effectively prevent the above problems. Therefore, after further careful study by the applicant of the present invention, the invention of the present invention can surely prevent the erroneous mounting of the plurality of substrates as described above, and at the same time, it is possible to reliably detect the conduction failure between the plurality of connectors. The present invention has been made in order to solve the above problems, and is a device in which a plurality of substrates are formed in a group and connected to a substrate on the other side, and the combination of the input signals of the group and the substrate is detected. A comparison mechanism such as a matching circuit in which the substrate combinations are inconsistent can easily and reliably detect a combination of different substrates, and can prevent breakage or failure of the substrate, the socket, or the mounted component due to the erroneous mounting of the substrate. In particular, it is intended to provide a device with an abnormality detecting circuit, which is applicable to a semiconductor test device in which a plurality of Dsas having a plurality of socket boards are combined. Ke duck has one or two of the substrates on which she is connected. The other side of the substrate with the corresponding one or more connectors transmits signals through all connected connectors and detects = rotates The wire is twisted, and the connection is unsatisfactory or detached, and it is possible to prevent the malfunction caused by the connector from being supplied or the work efficiency is low, and the like, in particular, the device for detecting the circuit at the same time It is suitable for use in the test.半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体A substrate group of at least one set of a plurality of substrates, and a device for connecting the wire groups: a device for the side of the device, and an ID setting substrate, which are respectively mounted on each of the substrates of the description (4), and are provided with a setting The specific number of the substrate group is outputted at the same time, and the signal indicating the fine number is outputted at the same time; the signal input substrate is mounted on the substrate corresponding to the (4) substrate group m彳 substrate, and the input signal is output from the substrate for the setting; Comparing means, (4) describing the fine signal of the output of the id signal input substrate, and comparing the ID signals of the corresponding substrates; and the structure of the substrate group. According to the present invention, the present invention has a substrate abnormality detection path = a clothing setting unit, and a comparison setting mechanism such as a matching circuit for detecting the consistency of the signal for still setting. The two or more substrates constituting the substrate group of the t table tf conform to the specific group a jID number, and the Πλ number can be input from each substrate, and the comparison and the determination are not performed. Therefore, it is not necessary to change the configuration or the shape of the substrate, that is, J = the combination of the plurality of substrates is determined by the π χ number inherent to the substrate group, and it is possible to accurately measure only the combination of different types of substrates, and it is possible to accurately charge the materials. County, outlet or fault, etc. In order to determine whether or not the combination of the substrates is correct, the substrate can be mounted on the mounting side, and the board can be judged to be With the consistency of the combination, it is possible to perform a more rapid determination process, and efficiently perform the original processing and processing of loading the substrate on the device. In addition, since the specific substrate group can be assigned to the number, even if the base is increased or decreased, the number of 1 can be easily detected by adding or deleting the iD number. Circuit. In addition, as disclosed in claim 2, the device having the second detection circuit of the present invention has a substrate with a connector, and a connector of each connector of the device. The substrate on the other side of the substrate::= from the daisy-key circuit 'from the other side of the substrate or the signal is reversed to the iit 'input signal' through the corresponding connectors will sequentially measure the above ==, and detect the presence or absence of output Signal, and its system is checked. ? The connection of all the connectors of the square side substrate is abnormal. The invention is constructed as follows. The present invention is attached to the US 柘© $ &, clothing, to have a circuit through one or two of the substrate When the daisy chain circuit tells the king that the connector transmits a signal abnormality, etc., it can be connected to the connector between the connectors connected to the f connection, and the signal is transmitted to the connector between the boards. At the same time, the judgment formula 'can find a connection failure in the connection base, etc., and the μ is in a bad situation, and the operation can be quickly performed y = the connector between the connection substrates is efficiently performed. When the device is used, it can still be called the current connection is not good or falls off, etc. It is still a device that does not cause malfunction due to poor connection and is not connected properly. a reliability of low operating rate, etc., is high. 29^Μί The substrate of the present invention, which is attached to the third aspect of the invention, has a plurality of devices with a connector: a composite group having a connector: a substrate group of at least one of the groups, and a device having a counterpart substrate of a connector for connecting the connector of the substrate 1 and the ground plate, and the substrate for each of the substrates is mounted on each of the substrate groups The specific ID number is simultaneously outputted to indicate that the still group 'IDm number is mounted on the substrate, and is mounted on the substrate corresponding to the substrate, and the private side substrate is inserted into each of the IDs of the iD setting substrate. Input ID signals from the input of the iD signal input substrate 4: read the ID signal of each substrate; and the daisy chain circuit, the ^ Yamaguchi connector will transmit the sequence signal to all the connectors, and detect and detect The combination of the substrates in the aforementioned substrate group is abnormal: often. The connection of all the connectors of the substrate and the other substrate is different according to the present invention. The substrate abnormality detecting circuit of the present invention is configured to: the circuit having the ID number of the substrate group for determining the substrate group. The comparison mechanism, and the way to detect the connection road, is surely on the board === key electricity:: board;; the other side: one side of the iii board and each substrate has a plurality of connectors connected to the pair of two τ谷易地% of the current number of connectors is poorly connected, and the ox-k is for a versatile, highly expandable and highly reliable skirt. Progress 14 129 see i then 'in particular, as in the case of the patent application, the fourth device is not equipped with a device for the detection circuit, in which a plurality of substrates for setting the ID signal are mounted on the substrate, and by the plural The ID signal setting substrate is configured to output the ID number of one of the substrates. According to the present invention, the substrate abnormality detecting circuit is attached
裝置，具備複數個ID訊號設定用基板，可藉由該複數個ID 訊號設定用基板所設定之全部編號而構成一個ID編號，並 可對應所使用之基板數量、種類等，而自由地設定任意之 工〇編號。因此，即使增減基板種類或數量時，仍可更容易 地進行附加、刪除、變更Π3編號等，而進一步可提供一種 泛用性、擴張性佳之異常檢測電路。 ^另一方面，如申請專利範圍第5項所揭示之附有異常 檢，電路之裝置，其中，前述基板及對方侧基板之連接器 =個或二個以上之銷，係在該基板及對方侧基板内藉由 、旦方式連接前述雛菊鏈電路之構成。 裝晋/構成之本發明_有基板異常檢測電路之 接器路之方式，而可構成經以 檢測複數個連接器之連接不71本發明之雜菊鏈電路， 板或裝置等大型化、;：異常等’而不須將基 載，的連接不良之可靠,種可預先發現裝 然後’如申請專利_項所二有異常檢測 12The device includes a plurality of ID signal setting substrates, and all of the numbers set by the plurality of ID signal setting substrates can be used to form one ID number, and can be freely set in accordance with the number and type of substrates used. The number of the work. Therefore, even when the type or the number of the substrates is increased or decreased, it is possible to more easily add, delete, or change the Π3 number, and the like, and further provide an abnormality detecting circuit which is excellent in general versatility and expandability. On the other hand, as disclosed in claim 5, the apparatus for detecting an abnormality, the circuit, wherein the connector of the substrate and the other side substrate = one or more pins are attached to the substrate and the other party The daisy chain circuit is connected to the side substrate by a denier method. The present invention has the form of a substrate abnormality detecting circuit connector, and can be configured to detect the connection of a plurality of connectors. The hybrid daisy chain circuit of the present invention, a board or a device, and the like; : abnormal etc. 'do not need to base the load, the connection is not reliable, the species can be pre-discovered and then 'as patent application _ item two have abnormal detection 12
^路之衣置’其中，前述基板係由具有裝載、連接有當作 ^驗對象之半導體零件的一個或二個以上之插座板的DSA 7構成，前述對方側基板係由裝載、連接有前述DSA之半 導體試驗裝置之主機板所構成。 ^ 再者，如申請專利範圍第7項所揭示之附有異常檢測 二=之裝置，其中，前述基板係由具有裝載、連接有當作 對象之半導體零件的一個或二個以上之插座板的DSA $構成’前述基板群係組合有複數個由前述DSA所構成之 ，前述對方侧基板係由一體裝載、連接有構成前述基 反群之複數個DSA之半導體試驗裝置的主機板所構成。 ^根據如此構成之本發明的附有基板異常檢測電路之 衣置，係將本發明之基板當作DSA，將對方側基板當作裝 載有DSA之主機板之構成，並且，以將具備複數個基板之 基板=當作具備複數個DSA之DSA群而構成之方式，可將 =SA衣卸型之半導體試驗裝置當作本發明之附有異常檢測 私路之衣置。因此’在藉由單獨置換具備插座板之DSa的 方式，可對應各種不同半導體零件之試驗的半導體試驗裝 置中，使用本發明之異常檢測電路即可容易且確實地檢測 出DSA之錯誤，或連接器脫落或接觸不良等，而可提供一 種可預先防範錯誤裝設或裝設*良之發生，且進行可靠性 尚的半導體零件之試驗的半導體試驗裝置。 【實施方式】 以下芬照第1圖至第7圖，同時說明本發明之附有基板 異常檢測電路之裝置之較佳實施型態。 16 129觀 第1圖表不本發明之一實施型態之附有基板異常檢測 Ϊ路的半導體試驗裝置之分解斜棚。第2酿示本實施型 悲之附有基板異常檢測電路之半導體試驗裝置，⑷為從 主機板侧取下DSA狀態之前視圖，（b)為u)所示之 之底視圖。 , ㈣等®式所示，本實施型態之附有基板異常檢測電 路，係將I设在基板相同面上之複數個連接器，連接在對 •應之對方側基板的衩數個連接器之裝置，且構成一種具備 排列有用以格載半導體零件之複數插座板1 1的〇§入1〇，和 當作連接該DSA10之對方侧的主機板2〇之半導體試驗裝 置。然後，本貫施型悲係具備用以檢測該半導體試驗裝置 中的DSA10錯誤或DSA10與主機板2〇之連接器連接不良之 異常檢測電路者。 (半導體試驗裝置） 首先，參照第1圖及第2圖，說明構成本實施型態之附 有基板異常檢測電路之裝置的半導體試驗裝置。如該圖所 _ 示，本實施型態之半導體試驗裝置係和第8圖所示之半導體 試驗裝置形成大致同樣之構成，具備裝載有當作試驗對象 之半導體零件（省略圖示）之插座板11的DSA10，係以可 自由裝卸方式構成在主機板20，且以僅單獨置換DSDA10 之方式，形成一種亦可對應不同種類之半導體零件之試驗 的試驗裝置。 如第 1圖所示，DSA (Device Specific Adapter) 1〇具 備複數個插座板11，同時在插座板底面側配設有連接器14[The clothing of the road] wherein the substrate is composed of a DSA 7 having one or two or more socket plates on which semiconductor components to be inspected are mounted, and the other substrate is loaded and connected. The motherboard of the semiconductor test device of DSA is composed. ^ Further, as disclosed in claim 7, wherein the substrate is provided by one or more socket boards having semiconductor components loaded and connected thereto as objects. The DSA$ constitutes a plurality of the substrate groups combined with the DSA, and the other side substrate is composed of a main board in which a plurality of DSA semiconductor test devices constituting the base group are integrally mounted. According to the clothing with the substrate abnormality detecting circuit of the present invention thus constituted, the substrate of the present invention is regarded as a DSA, and the other substrate is configured as a motherboard on which a DSA is mounted, and a plurality of boards are provided. The substrate of the substrate is configured as a DSA group having a plurality of DSAs, and the semiconductor test device of the SA-dismounting type can be used as the clothing of the present invention with the abnormality detection private road. Therefore, it is possible to easily and surely detect a DSA error or connect by using the abnormality detecting circuit of the present invention in a semiconductor test apparatus capable of testing various semiconductor components by separately replacing the DSa having the socket board. The device can be detached or has poor contact, and the like, and a semiconductor test device capable of preventing the occurrence of erroneous mounting or mounting, and testing the reliability of the semiconductor component can be provided. [Embodiment] Hereinafter, a preferred embodiment of the apparatus for attaching a substrate abnormality detecting circuit of the present invention will be described with reference to Figs. 1 to 7 . 16 129. The first graph is not an embodiment of the present invention. The substrate is abnormally detected. The semiconductor test device of the circuit is decomposed. In the second embodiment, a semiconductor test apparatus including a substrate abnormality detecting circuit is provided, (4) is a front view in which the DSA state is removed from the main board side, and (b) is a bottom view shown as u). (4), etc., in the present embodiment, the substrate abnormality detecting circuit is provided with a plurality of connectors on the same surface of the substrate, and a plurality of connectors connected to the opposite substrate of the corresponding substrate. The device comprises a semiconductor test device having a plurality of socket boards 11 for arranging the semiconductor components and a semiconductor board for connecting the other side of the DSA 10. Then, the present embodiment has an abnormality detecting circuit for detecting a DSA10 error in the semiconductor test apparatus or a connector connection failure between the DSA 10 and the motherboard 2A. (Semiconductor Test Apparatus) First, a semiconductor test apparatus constituting the apparatus having the substrate abnormality detecting circuit of the present embodiment will be described with reference to Figs. 1 and 2 . As shown in the figure, the semiconductor test apparatus of the present embodiment has substantially the same configuration as the semiconductor test apparatus shown in Fig. 8, and includes a socket board on which a semiconductor component (not shown) to be tested is mounted. The DSA 10 of 11 is formed in a detachable manner on the motherboard 20, and a test apparatus which can also test different types of semiconductor components by forming the DSDA 10 alone. As shown in Figure 1, the DSA (Device Specific Adapter) 1 has a plurality of socket boards 11 and a connector 14 on the bottom side of the socket board.
129 娜, 鹿:弟i圖⑴）：由於該等複數個插座板11和所對 接裔14係—體早70化成—枚基板狀者，因此通常形 成將細A當作-單位來製造、裝卸、置換等。如此以單 = ^DSA單位處理複數個插座板之方式，例如關於封裝 版構k或銷構造不同的半導體零件，準備以 單位對應之插絲，而以在主機板裝卸、置 體零件之説的方式，進行各種不同的複數^體零$ 試驗。 然後，如此之DSA裝卸型半導體試驗裝置，係形成可 在一個主機板將具備相同構成之插座板的DSA，以9個一 組、4個一組等複數個D S A當作—組裝載使用，俾可同時實 施多數半導體零件之試驗。如第〗圖所示，本實 聊議（DSA_偷及DS侧b)#作—組， 組之DSA10形成一體裝載、連接在主機板2〇上。具體而言， 本實施型態之DSA 10係複數個插座板π排列在當作基極基 板之框形SB框（插座板框）12上，同時在SB框12之框空間 内’形成配设有對應各插座板11而連接之連接器14。 各插座板11分別由具備裝載有當作試驗對象之半導 體零件而電性連接之元件裝載連接部飞插座部）的基板所 構成，在各插座板11分別裝載一個半導體零件。然後，該 複數個插座板11係分別裝載、固定在兕框12之框體部分 上。 SB框12係由金屬寺所構成之框構件，具備複數空間 (參照第2圖（b))，如第2圖所示，本實施型態具備1行8 18 l29min 個’合计16個空間區域。然後，如第2圖.（b)所示，該SB 框12之各空間内分別收容有連接在插座板丨丨之連接器丨々。 此處，如第1圖、第2圖所示，本實施型態之]〇§人1〇係§技框 12具備2行之1行8個的空間區域，在合計16個空間區域分 別具備各2個插座板u及對應之連接器14，合計32個。但 疋，插座板11、連接器14之數量及sb框12之空間數量等， 並非特別受限定者。 '129 Na, Deer: Di's figure (1)): Since the plurality of socket boards 11 and the 14-series of the docking body are formed into a substrate, the thin A is usually manufactured as a unit, and is loaded and unloaded. , replacement, etc. In this way, a plurality of socket boards are processed in a single = ^DSA unit, for example, a semiconductor component having a different package structure or a pin structure is prepared, and a wire corresponding to the unit is prepared, and the component is mounted and unloaded in the main board. The way to perform a variety of different complex ^ zero zero trials. Then, in such a DSA loading and unloading type semiconductor test apparatus, a DSA having a socket board having the same configuration can be formed on one motherboard, and a plurality of DSAs, such as 9 groups and 4 groups, can be used as a group load. Testing of most semiconductor parts can be performed simultaneously. As shown in the figure, the actual discussion (DSA_ stealing DS side b) #作—group, the DSA10 of the group is integrated and connected to the motherboard 2〇. Specifically, the DSA 10 of the present embodiment has a plurality of socket boards π arranged on a frame-shaped SB frame (socket frame) 12 serving as a base substrate, and is formed in the frame space of the SB frame 12 There are connectors 14 connected to the respective socket boards 11. Each of the socket plates 11 is constituted by a substrate having a component mounting socket portion (which is provided with a component mounted on the semiconductor component to be tested and electrically connected), and each of the socket plates 11 is mounted with one semiconductor component. Then, the plurality of socket boards 11 are respectively loaded and fixed on the frame portion of the frame 12. The SB frame 12 is a frame member made of a metal temple and has a complex space (see FIG. 2(b)). As shown in FIG. 2, this embodiment has 1 row, 8 18 l29 min, and a total of 16 spatial regions. . Then, as shown in Fig. 2(b), each of the spaces of the SB frame 12 houses a connector 连接 connected to the socket board. Here, as shown in FIG. 1 and FIG. 2, the present embodiment has a spatial region of two rows and one row, and has a total of 16 spatial regions. A total of 32 socket boards u and corresponding connectors 14 are provided. However, the number of the socket boards 11, the number of connectors 14, and the number of spaces of the sb frame 12 are not particularly limited. '
如以上所述，以將連接器14收容在SB框12之方式，而 將連接器14配設在各插絲此底面侧，將各連接器㈣ ，在SB框12上所對應之插絲n，同時在插絲底面側固 定在相同平面上，而在主機板2〇侧對應之連接器Μ (袁昭 口第1圖）同時裝卸有全部連接器。因而，該DSA1_之連^ 和主機板20侧之連接器21未全部正常地嵌合、連接 胃械連錢之連接不良，1藉由後述之㈣鍵電路 40檢測出有無該連接器之連接不良。 把圖所示，裝載於_12上之各插座板將各插座 ΐϋ角隅形成缺口形狀，且從該缺σ部分露出纽框 2之框脰#分，該卿gl2之露出部分形成有插人突設在主 的定麵5 °以在㈣細5插入定 方式’將DSA1吹位且固定在主機⑽之特定位 方、SB们2長度方向之左右二處所（參照第如，但 :;Γ =預定位置’可在任何位置裝設定位銷22及定 位孔15 ’且该數量亦不特別受限定， <.S：. 19 129娜丨 再者，如第2圖所示，該SB框12在不妨礙連接器配設 面之複數各連接器14之區域，設定有DSA10之ID編號，且 配設有輸出表示該1D編號之Π)訊號的ID設定用基板13。該 ID設定用基板13之詳細將後述。 然後，由如以上構成所構成之DSA10係組合裝載有相 同構造之插座板11的二枚DSA-A10a和DSA-B10b當作一 組，該二枚一組之DSA10係一體裝載於主機板2〇。亦即， 本實施型態係對應二枚一組之DSA10、插座板11之種類， 例如，設定成「DSA-A及B」、「DSA-C及D」或「DSA-E 及F」…，而組合使用裝載有相同構造之插座板丨丨的二枚 DSA10。因而，此時，例如組合「DSA-A和DSA-C」或「DSA-B 和DSA-D」’會使不同種類之插座板u裝載於主機板2〇 上’對DSA10之組合而言為異常。 然後，透過後述之ID設定用基板^而以仍一致電路30 檢測出該DSA10的組合之一致不一致。 如第1圖所示，主機板2〇係於裝設在半導體試驗裝置 ^本體侧的基板，如上所述，具備對應於將複數插座板u 單兀化之DSA10侧的複數個連接器21 (參照第1圖）。藉由 透過連接器而將DSA10連接在該主機板2〇之方式 ，而透過 主機板20將試驗所需之預定電性訊號輸出入至DSA侧，以 進行各插座板11上之半導體零件之試驗。 和、然後’本實施型態係於該主機板20上面之不妨礙複數 ^連接态21之區域，配設和DSAl〇侧之ID設定用基板13接 *的接觸銷用基板23。該接觸銷用基板23之詳細將和 20 129娜 DSA10側之ID没定用基板13一起後述。 又，本實施型態中當作主機板20所示之部分，一般除 了裝設在半導顏驗裝置之本虹駐機板之外，係包含 SPCF、金屬板、工作特性基板、公用基板等，且如後述， 在本貫施型,％中，異常檢測電路係裝設在主機板内之公 用基板20a。®而，本實施型態所謂之「主機板」，係以可 自由裝卸方錢接在單元化之Dsaiq，表林發明之對方 側基板。而且，雖然省略詳細說明，但除了上述〇从1〇及 主機板20之外，裝設在本實施型態之半導體試驗裝置之構 成、功;3b，係形成與既存之半導體試驗裝置同樣者。 「ID設定用基板」 接著’芩照第3圖及第4圖，說明本實施型態之11}設定 用基板13。第3圖為概念性地表示本實施型態之仍設定用 基板13和接觸銷用基板23之主要部分剖面前視圖。第4圖為 概念性地表示本實施型態之11}設定用基板13和1〇一致電 路30之關係之方塊圖。 該等圖式所示之ID設定用基板13，係設定有表示各 DSA10 (DSA-A及B、DSA-C及D...)之組合的ID編號，且 利用輸出表示該ID編號之id訊號的基板，裝設在DSA10之 連接器配設面侧。 該iD設定用基板13係配設在SB框12之連接器配設面 之不妨礙複數個各連接器14的區域，如第2圖所示，本實施 型態在各DSA10 ( i〇a、i〇b)分別配設有8個1〇設定用基板 12924¾ 然後，在該ID設定用基板13相對向之主機板20侧，裝 設有當作ID訊號輸入用基板之接觸銷用基板23。如第1圖 所示，該接觸銷用基板23在對應於各ID設定用基板13之位 置，分別將對應於二枚DSAlOa、10b之各8個，合計16個接 觸銷用基板23，與ID設定用基板13同樣地，配設在不妨礙 主機板之包數個各連接益21的區域。因此，當]3SA10裝載 • 於主機板2〇上時，對應之ID設定用基板13之ID訊號輸出焊 ， 墊13a和接觸銷用基板23之接觸銷23a相接觸，如後所述， 鲁在裝載DSA10之同時，可將ID訊號自動地輸出到id—致電 路30。 如第3圖所示，各ID設定用基板13以螺栓等固定機構 配設在與DSA10之主機板20侧相對向之面，且在固定之基 板表面具備2個一對之ID訊號輸出銲墊13 a。一對之ID訊號 輸出銲墊13a係分別透過通孔13b而連接在基板内面側 (DSA10側）之2個一對的ID編號設定銲墊13c。 各ID編號設定銲墊13c係透過跨接線13d而分別連接 ⑩在GND銲墊13e。GND銲墊13e係透過未圖示之導體圖案， 接地在例如固定ID設定用基板13之螺栓等。然後，依據是 否將跨接線13d連接在該GND銲墊13e，而可將ID編號設定 銲墊13c設定成GND或OPEN。 具體而言，ID編號設定銲墊13c設定成GND (連接在 GND銲墊13e)時，從訊號輸出銲墊13a輸出到後述ID — 致電路30之訊號，由於將輸入侧予以接地而形成L〇w (〇)。另一方面，ID編號設定銲墊13c設定成OPEN (非 22 129mi 連接在GND銲墊13e)時，從ID訊號輸出銲墊na輸出到仍 一致電路30之訊號，藉由ID —致電路30之電源電壓Vcc而 形成HIGH (1)(參照第5圖）。 如此，本實施型態之ID設定用基板13，係依據有無連 接跨接線13d，而可將從連接在ID編號設定錚墊i3c之ID訊 號輸出銲墊13a輸出的訊號，切換成LOW ( 0) /HIGH ( 1)。 然後’藉由將任意之LOW (0) /HIGH (1)訊號設定在該 ID設定用基板13的方式，可將表示所希望的ίχ)編號之仍訊 號輸入至ID —致電路30 (參照第4圖）。 此處，如第2圖所示，本實施型態在各dsaIO (l〇a、 l〇b)分別配设8個ID設定用基板π，各ID設定用基板13具 備2個Π)訊號輸出銲墊13a。因此，可設定在π)設定用基板 13之ID編號，係可在一組DSA10 ( l〇a、l〇b)分配成16位 元之訊號，但在本實施型態中，將該16位元訊號中的上位 (或下位）之14位元訊號，分配成當作表示】D編號之仍訊 號。 例如，將表示「DSA-A及B」之組合的Π)編號當作 「00000000000001」，將表示「DSA_C&D」的仍編號當 作「00000000000010」等，可在14位元範圍内任意地賦予 ID編號。 然後，如第4圖所示，從各DSAlOa、10b輸出該14位 元之ID矾號，透過主機板2〇側之接觸銷用基板23而輸入至 ID —致電路30。 然後，表示該DSA10之ID編號的ID訊號之位元數，並As described above, in order to accommodate the connector 14 in the SB frame 12, the connector 14 is disposed on the bottom surface side of each of the wires, and the connectors (four) and the corresponding wires on the SB frame 12 are connected. At the same time, the bottom surface of the wire is fixed on the same plane, and the connector Μ (Yuan Zhaokou first figure) corresponding to the side of the motherboard 2 is simultaneously loaded and unloaded with all the connectors. Therefore, the connection between the DSA1_ and the connector 21 on the motherboard 20 side is not normally fitted, and the connection between the gas and the device is poor, and the connection of the connector is detected by the (four) key circuit 40 which will be described later. bad. As shown in the figure, each socket board mounted on the _12 forms a notch shape in each socket corner, and the frame 脰# of the button frame 2 is exposed from the σ portion, and the exposed portion of the gl2 is formed with a plug-in The protrusion is set at 5 ° on the main surface to insert the DSA1 in the (4) fine 5 insertion mode and fixed to the specific position of the host (10) and the left and right of the SB 2 (refer to the first, but: ; = predetermined position 'The position pin 22 and the positioning hole 15' can be installed at any position and the number is not particularly limited, <.S:. 19 129 Naga, as shown in Fig. 2, the SB frame In the area where the plurality of connectors 14 of the connector arrangement surface are not obstructed, the ID number of the DSA 10 is set, and the ID setting substrate 13 for outputting the signal indicating the 1D number is provided. The details of the ID setting substrate 13 will be described later. Then, the DSA 10 series constituted by the above configuration is combined with two DSA-A10a and DSA-B10b loaded with the socket board 11 of the same configuration as a group, and the two sets of DSA 10 are integrally mounted on the motherboard 2 . That is, the present embodiment corresponds to the type of the DSA 10 and the socket board 11 of the two groups, for example, set to "DSA-A and B", "DSA-C and D" or "DSA-E and F"... In combination, two DSAs 10 loaded with the same configuration of the socket plate are used in combination. Therefore, at this time, for example, combining "DSA-A and DSA-C" or "DSA-B and DSA-D" will cause different types of socket boards u to be loaded on the motherboard 2' for the combination of the DSA10. abnormal. Then, the matching of the combinations of the DSAs 10 is detected by the still matching circuit 30 through the ID setting substrate described later. As shown in Fig. 1, the motherboard 2 is attached to a substrate mounted on the main body of the semiconductor test apparatus, and as described above, a plurality of connectors 21 corresponding to the DSA 10 side of the plurality of socket boards u are provided ( Refer to Figure 1). By connecting the DSA 10 to the motherboard through the connector, the predetermined electrical signals required for the test are output to the DSA side through the motherboard 20 to test the semiconductor components on the socket boards 11. . In the present embodiment, the contact pin substrate 23 connected to the ID setting substrate 13 on the DSAl side is disposed in a region on the main board 20 that does not interfere with the plurality of connection states 21. The details of the contact pin substrate 23 will be described later together with the ID determinate substrate 13 on the 20A 129 DSA10 side. In addition, in the embodiment, the portion shown as the motherboard 20 is generally provided with SPCF, a metal plate, a working characteristic substrate, a common substrate, etc., in addition to the main board of the semiconductor device. As will be described later, in the present embodiment, %, the abnormality detecting circuit is mounted on the common substrate 20a in the motherboard. In the present embodiment, the so-called "main board" is attached to the unitized Dsaiq, which is the other side of the invention. Further, although the detailed description is omitted, the configuration and work of the semiconductor test apparatus of the present embodiment, except for the above-described cymbal and the motherboard 20, are the same as those of the existing semiconductor test apparatus. "ID setting substrate" Next, the substrate 11 for setting 11 of the present embodiment will be described with reference to Figs. 3 and 4 . Fig. 3 is a front cross-sectional front view showing a main portion of the substrate 13 and the contact pin substrate 23 of the present embodiment. Fig. 4 is a block diagram conceptually showing the relationship between the 11} setting substrate 13 and the 1" matching circuit 30 of the present embodiment. The ID setting substrate 13 shown in the drawings has an ID number indicating a combination of each DSA 10 (DSA-A and B, DSA-C, and D...), and an id indicating the ID number by an output. The signal board is mounted on the connector side of the DSA10. The iD setting substrate 13 is disposed in a region where the connector arrangement surface of the SB frame 12 does not interfere with the plurality of connectors 14. As shown in Fig. 2, the present embodiment is in each DSA 10 (i〇a, In the case of the ID setting substrate 13 facing the main board 20, the contact pin substrate 23 serving as the ID signal input substrate is mounted. As shown in Fig. 1, the contact pin substrate 23 corresponds to each of the ID setting substrates 13, and corresponds to each of two DSAlOa and 10b, and a total of 16 contact pin substrates 23 and IDs. Similarly, the setting substrate 13 is disposed in an area that does not interfere with the number of connection benefits 21 of the package of the motherboard. Therefore, when the 3SA10 is mounted on the motherboard 2, the ID signal output welding of the corresponding ID setting substrate 13 is contacted, and the pad 13a is in contact with the contact pin 23a of the contact pin substrate 23, as will be described later. The ID signal can be automatically output to the id-in circuit 30 while the DSA 10 is being loaded. As shown in Fig. 3, each of the ID setting substrates 13 is disposed on a surface facing the main board 20 side of the DSA 10 by a fixing mechanism such as a bolt, and has two pairs of ID signal output pads on the surface of the fixed substrate. 13 a. A pair of ID signal output pads 13a are connected to the pair of ID number setting pads 13c on the inner surface side (DSA10 side) of the substrate through the through holes 13b. Each of the ID number setting pads 13c is connected to the GND pad 13e via the jumper 13d. The GND pad 13e is transmitted through a conductor pattern (not shown), and is grounded, for example, to a bolt for fixing the ID setting substrate 13. Then, the ID number setting pad 13c can be set to GND or OPEN depending on whether or not the jumper wire 13d is connected to the GND pad 13e. Specifically, when the ID number setting pad 13c is set to GND (connected to the GND pad 13e), the signal output pad 13a is outputted to the signal of the ID-inducing circuit 30, which is described later, and the input side is grounded to form L〇. w (〇). On the other hand, when the ID number setting pad 13c is set to OPEN (non-22 129mi is connected to the GND pad 13e), the signal is output from the ID signal output pad na to the signal still in the same circuit 30, by the ID-inducing circuit 30 The power supply voltage Vcc forms HIGH (1) (refer to Fig. 5). As described above, the ID setting substrate 13 of the present embodiment can switch the signal output from the ID signal output pad 13a connected to the ID number setting pad i3c to LOW (0) depending on the presence or absence of the connection jumper 13d. /HIGH (1). Then, by setting an arbitrary LOW (0) / HIGH (1) signal to the ID setting substrate 13, a still signal indicating the desired number can be input to the ID-inducing circuit 30 (refer to 4 picture). Here, as shown in Fig. 2, in the present embodiment, eight ID setting substrates π are disposed in each of dsaIO (10a, l〇b), and each ID setting substrate 13 has two 讯) signal outputs. Solder pad 13a. Therefore, the ID number of the π) setting substrate 13 can be set, and a signal of 16 bits can be allocated to a group of DSAs 10 (1〇a, l〇b), but in the present embodiment, the 16-bit is used. The 14-bit signal of the upper (or lower) digit in the yuan signal is assigned as the still signal indicating the D number. For example, the Π) number indicating the combination of "DSA-A and B" is regarded as "00000000000001", and the still number indicating "DSA_C&D" is regarded as "00000000000010", etc., and can be arbitrarily given within the range of 14 bits. ID number. Then, as shown in Fig. 4, the 14-bit ID number is output from each DSAlOa, 10b, and is input to the ID-inducing circuit 30 through the contact pin substrate 23 on the side of the motherboard 2. Then, the number of bits of the ID signal indicating the ID number of the DSA 10, and
23 1292规 非限定於本實施型態中的14位元之情形者，可對應dSAIO 之種類而任意地設定，且亦可對應所需之位元數而變更工D 設定用基板13之數量或輸出銲墊數量。例如使用1〇〇〇種 DSA10之半導體試驗裝置時，由於ID編號變成1000個，因 此若採用10位元之訊號，可賦予1〇24個ID。因而，此時若 是如本實施型態之ID設定用基板13般，輸出數為「2」之ID 5又疋用基板’則只要在各DSA裝設各5個即足夠。相對於 _ 此，可使用10000種DSA10之半導體試驗裝置時，id編號 亦必須為10000個，如本實施型態，以採用14位元訊號之方 式’可賦予16384種方式之ID編號。如此，本實施型態之π) 设定用基板13係將配設數、輸出位元數或可使用之位元數 中的多少位元分配作為ID訊號，而可任意設定者。 然後’對該ID設定用基板13之ID編號設定，係最好於 組裝DSA10前進行，在設定裝載於DSA10之插座板11的種 類後，以對應之2個一組而將設定有相同仍編號之仍設定 用基板13女裝在DSA10之預定處所。而且，一次設定之id Φ 編號，通常其後不須變更，且由於不小心之ID變更亦有造 成DSA10錯誤裝設等之情形，因此如本實施型態所示，期 待使用螺栓等將ID設定用基板13固定在DSA10侧，且安裝 成不能裝卸之方式。 (ID —致電路） 接著，參照第5圖說明本實施型態之10 一致電路3〇。 第5圖表示本實施型態之π) —致電路3〇之詳細電路圖。 如該圖所示，本實施型態之ID—致電路3〇係檢測一組 24 129¾¾ DSA10 (l〇a、㈣的一致不一致之電路，當作比較1〇訊 號之比較機構。本實施型態係輸入從DSAi〇a、⑽之各1〇 設定用基板13輸人之各14位元ID訊號。具體而言，如第5 圖所不’ ID-致電路3〇係由輸入各14位元仍訊號之⑷固 XOR電路和7個N0R電路及_AND電路所構成，將從各 .DSAlGa、1Gb^ID設定用基板丨增人之各1顿元之仍訊 號，以對應之位元加以比較，僅在全部位元一致時，輸出 鲁HIGH⑴訊號’其他情形則輪出LOW (〇)訊號。因此， f檢測出裂載於主機板2〇上之DSA1〇之組合一致，且組合 ，『同種類之DSA10時，由於可輸出異常訊號（L〇w (〇) 訊號).、，因此可進行對應發生異常之處理。本實施型態係 =述，將於主機板2_貞圆A1G之翻機構控制成不 能鎖固狀態’同時進行表示ID編號不-致之顯示。 然後，本實施型態係將該ID一致電路3〇裝設在主機板 2〇侧j公用基板術（參照第4圖、第7圖），檢測_訊號 ^ 致日守，如後所述，在公用基板2〇a當作「id訊號有異 W常」進行處理。 /、23 1292 is not limited to the 14-bit case in the present embodiment, and can be arbitrarily set according to the type of dSAIO, and the number of the D-setting substrate 13 can be changed corresponding to the required number of bits or The number of output pads. For example, when one semiconductor test device of the DSA 10 is used, since the ID number becomes 1000, if a 10-bit signal is used, 1 to 24 IDs can be assigned. Therefore, in the case of the ID setting substrate 13 of the present embodiment, it is sufficient that the number of the IDs 5 and the number of the substrates used in the DSA are set to five in each DSA. In contrast, when 10,000 kinds of DSA10 semiconductor test devices can be used, the id number must also be 10,000. As in the present embodiment, the ID number of 16384 modes can be assigned by using the 14-bit signal method. In this way, the π) setting substrate 13 of the present embodiment can assign any number of bits, the number of output bits, or the number of usable bits as an ID signal, and can be arbitrarily set. Then, the ID number setting of the ID setting substrate 13 is preferably performed before the DSA 10 is assembled. After the type of the socket board 11 mounted on the DSA 10 is set, the same number is set in the corresponding two groups. The substrate 13 is still set to be a predetermined place in the DSA 10. In addition, the id Φ number that is set once is usually not changed afterwards, and the DSA10 is incorrectly installed due to an accidental ID change. Therefore, as shown in this embodiment, it is expected to set the ID using a bolt or the like. The substrate 13 is fixed to the DSA 10 side and mounted so as not to be detachable. (ID-to-Circuit Circuit) Next, a 10-match circuit 3A of this embodiment will be described with reference to FIG. Fig. 5 is a detailed circuit diagram showing the π)-transistor circuit 3 of the present embodiment. As shown in the figure, the ID-inducing circuit 3 of the present embodiment detects a set of 24 1293⁄43⁄4 DSA10 (l〇a, (4) consistent inconsistent circuits, as a comparison mechanism for comparing 1 〇 signals. This embodiment mode Each of the 14-bit ID signals input from the setting substrate 13 of each of DSAi〇a and (10) is input. Specifically, as shown in FIG. 5, the ID-to-circuit 3 is input by each 14-bit element. The signal (4) solid XOR circuit and the seven NOR circuits and the _AND circuit are formed, and the still signals of each 1 ton of each of the .DSAlGa and 1Gb^ID setting substrates are added, and the corresponding bits are compared. Only when all the bits are the same, the output of the HIGH (1) signal is 'others' LOW (〇) signal. Therefore, f detects the combination of the DSA1〇 split on the motherboard 2〇, and the combination, In the case of the DSA10 type, since the abnormal signal (L〇w (〇) signal) can be output, the corresponding abnormality processing can be performed. This embodiment is described as follows, and will be turned over on the motherboard 2_贞A1G The mechanism is controlled to be unable to lock the state 'at the same time, indicating that the ID number is not displayed. Then, this embodiment mode The ID matching circuit 3 is mounted on the main board 2 side j common substrate (refer to FIG. 4, FIG. 7), and the detection signal is sent to the keeper, as will be described later, on the common substrate 2〇a The "id signal is different" is processed.
At而且，用以比較1D訊號之比較機構亦可採用本實施型 不之ID —致電路30以外之構成。亦即，比較機構只^ 可4由比較ID汛號之方式而檢測出組合有不同種類之 DSA，則可採用任何電路或裝置等。 、 (雛菊鏈電路） μ 2接著，參照第6圖說明本實施型態之離菊鏈電路卯。 第6圖為概念性地表示本發明實施型態之離菊鏈電路4〇之 25 129 鳩 i 舌兄明圖。 如該圖所示，雛菊鏈電路40係一種從主機板2〇側的一 個連接器21(第6圖左端之連接器21)輸入訊號，經由所對 應之DSA10側之連接器14 (第6圖左端之連接器14)，佐順 序將訊號傳送到主機板20和DSA10之全部連接哭21、μ、 而檢測出有無輸出訊號之電路。具體而言，由於雛菊=带 路40係將主機板20侧之連接器21及DSA10侧之連接哭14 = 別對應之銷分配成雛菊鏈用，依順序串聯連接全部、卓刀 f，而形成傳送線路者，因此如第6圖所示，本實二= 错由使主機板20側之連接器21 &DS A丨〇侧之連 = 二個銷短路之方式，而串聯連接全部連接器。^ 口 首先，在主機板2〇側將各連接器2〗之 為公创销）分⑯#am 鋼C弟6圖中 一刀酉u成雛莉鏈用，將一個當作輸入侧，將另 個當作輸出侧。然後，在鄰^側舲另一 而这棬一古夕、电从 丧0連接益21間透過短路線21a 接叩71 & 接斋21的雛菊鏈用輸出銷’與另一方之、車 接21的離赫用*人 力刀之連 14之2個銷（第6圖=# ^且’ DSA1Q側亦將各連接器 當作輸入側，將^固；S分配成離菊鏈用’將-個 短路、^物㈣域，且在麵細4内以 器中不使用之、14中的雛菊鏈用銷可利用各連接 根據如此之亦可於離菊鍵設置專用之銷。 側和DSA10侧所對庫:之=路40 ’僅在正常地連接主機板2〇 仙之輸入側和輪出：之工部；接器時，會導通離菊鏈電路 旬在任意連接器有連接不良時，均形 26At the same time, the comparison means for comparing the 1D signals can also be constructed other than the ID of the present embodiment. That is, the comparison mechanism can detect any combination of different types of DSAs by comparing the ID nicknames, and any circuit or device can be used. (Daisy Chain Circuit) μ 2 Next, the daisy-chain circuit 本 of this embodiment will be described with reference to FIG. Fig. 6 is a diagram conceptually showing the daisy chain circuit of the embodiment of the present invention. As shown in the figure, the daisy chain circuit 40 is a type of connector 21 (connector 21 at the left end of FIG. 6) from the side of the motherboard 2, via the corresponding connector 14 on the DSA 10 side (Fig. 6). The connector 14) at the left end sequentially transmits a signal to the circuit connecting the motherboard 20 and the DSA 10 to cry 21, and to detect the presence or absence of an output signal. Specifically, the daisy=belt 40 system is used to connect the connector 21 on the motherboard 20 side and the connection on the DSA 10 side to the daisy chain, and to connect all of the pins in sequence, and to form a transfer. As shown in Fig. 6, the actual two = wrong is caused by short-circuiting the connector 21 & DS A side of the motherboard 20 side = the two pins are short-circuited, and all the connectors are connected in series. ^ First, on the side of the motherboard 2, each connector 2 is a public sales pin) 16#am steel C brother 6 picture in a knife 酉u into a young chain, one as the input side, will be another As the output side. Then, on the side of the neighboring side, the other side, the old one, the electricity from the mourning 0 connection benefit 21 through the short-circuit line 21a to connect 71 & the daisy chain of the fasting 21 with the output pin 'to the other side, the car 21 of the use of * human labor knife with 14 of the 2 pin (6th figure = # ^ and ' DSA1Q side also regards each connector as the input side, will be solid; S is assigned to the daisy chain with 'will A short circuit, a (four) field, and a daisy chain pin that is not used in the face 4, the 14 daisy chain pin can be used to make a dedicated pin according to the setting of the daisy key. Side and DSA10 side The corresponding library: the = road 40 'only in the normal connection of the motherboard 2 〇 仙 input side and turn out: the work department; when the connector, will be turned off the daisy chain circuit when any connector has poor connection, Homogeneous 26
129獅 絲法導通_鏈電路4G。因而，以在該_ 加電壓之方式，與連接器之連接同時地，當全= 連接以有接觸不良時會輪出正常訊號（扭冊⑴ 以監視有無該輸出訊號，藉此可檢 ;’ DSA1〇側輯狀連㈣是衫部正常地連接。因1側！: 將DSAK)裝载於主機板2G側而連接連接器彼此時 田士 檢測出主機板20侧和DSA10侧間的連接器連接異常。°」守 然後，來自該雛菊鏈電路4〇之輪出訊號係輸入 基板20a (參照第7圖），且如後述，判斷仍訊號之— -致的同時亦判斷在公用基板2Ga是否有異常，異 「Daisy Chain有異常」進行處理。 田 然後，本實施型態中，1隹菊鏈電路40係將主機板2〇側 及DSA10側之各連接器的各2個銷分配成雛菊鏈用，但其並 非特別限定於2個銷。亦即，雛菊鏈電路4〇只要以依串聯 連接主機板20側和DSA10側之全部連接器的方式可形成^ 送線路，則使用之銷數量或連接方法並沒有特別限定。因 而，例如DSA10和主機板20具備同軸連接器時，以使同軸 連接裔之SIG線和GND線短路之方式，亦可將SIG線分配在 離菊鏈之輸入側，將GND線分配在輸出侧，而構成雛菊鏈 電路40。 而且，本實施型態係於主機板20側進行雛菊鏈電路4〇 之輸入和輸出，但亦可在DSA10側進行對雛菊鏈電路4〇之 輸出入訊號。 (公用基板） 27129 lion wire method conduction _ chain circuit 4G. Therefore, at the same time as the connection with the connector in the manner of the voltage, the normal signal is turned off when the full connection is made to have a bad contact (the twisting (1) is used to monitor the presence or absence of the output signal, thereby detecting; DSA1 〇 辑 辑 四 四 四 四 四 四 四 四 四 四 DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS abnormal. Then, the wheel-out signal from the daisy chain circuit 4 is input to the substrate 20a (refer to FIG. 7), and as will be described later, it is judged whether or not the common substrate 2Ga is abnormal, The "Daisy Chain has an exception" is processed. In the present embodiment, the daisy-chain circuit 40 is used to distribute the two pins of the connector on the side of the main board 2 and the side of the DSA 10 into a daisy chain, but it is not particularly limited to two pins. In other words, the number of pins used or the connection method is not particularly limited as long as the daisy chain circuit 4 can form a transmission line by connecting all the connectors on the side of the main board 20 and the side of the DSA 10 in series. Therefore, for example, when the DSA 10 and the motherboard 20 are provided with a coaxial connector, the SIG line can be distributed on the input side of the daisy chain and the GND line can be distributed on the output side so that the SIG line and the GND line of the coaxial connection are short-circuited. And the daisy chain circuit 40 is formed. Further, in the present embodiment, the input and output of the daisy chain circuit 4 are performed on the side of the motherboard 20, but the input and output signals to the daisy chain circuit 4 can be performed on the DSA 10 side. (common substrate) 27
UnMn 接著，參照第7圖說明本實施型態之公用基板2〇a。第 7圖為概念性地表示本實施型態之附有基板異常檢測電路 之半導體試驗裝置中的公用基板2〇a之方塊圖。 如第7圖所示，本實施型態之公用基板施係裳設在主 機板20侧之基板，具備輸人從_鏈電路4Q傳來的輸出訊 號，同日守輸入從ID設定用基板13傳來的仍訊號之仍一致電 路30。然後。如第7圖所示，公用基板施具備輸入難菊鐘 電路街口ID-致電路30之輸出訊號賴固八肋電路33、輸 入雛菊鏈電雜之輸出訊號_菊鏈異常域輪入部34及 知入ID-致電路3〇之輸出訊號的仍編號異常訊號輸入部 o r ° AND電路33僅在從雛菊鏈電路40和ID —致電路30輸 入^號為HIGH⑴，亦即正常訊刺，會輸出表示「沒 U」之几號（HIGH ( 1 )訊號）。藉由該電路 之輸出訊號，檢測DSA1(^ID沒有不—致，且腸1〇和主 機=20之全部連接器是否連接不良，㈣行「沒有異常」 之。本貫施型態係從該AND電路33輸出「沒有異常」 =日=’將在主機板2〇側鎖固Μαι〇之鎖固機構控 固狀態（LOCK)。 另方面，雛菊鏈異常訊號輪入部34或ID編號異常訊 ίΪΐ部35在輪入之訊號為謂（〇)，亦即異常訊號時， :剧表示有異常」之訊號。藉此 ，檢測出DSA10和主 ^ 任意連接时連接不良，或DSA1G之ID有不-致 、月开乂而虽作「DaisyChain有異常」或「id編號有異常」 ； 28 129概UnMn Next, the common substrate 2A of the present embodiment will be described with reference to Fig. 7. Fig. 7 is a block diagram conceptually showing a common substrate 2A in the semiconductor test apparatus with the substrate abnormality detecting circuit of the present embodiment. As shown in FIG. 7, the common substrate of the present embodiment is applied to the substrate on the side of the motherboard 20, and has an output signal transmitted from the _chain circuit 4Q, and the same input from the ID setting substrate 13 is transmitted. The incoming signal is still consistent with circuit 30. then. As shown in FIG. 7 , the common substrate is provided with an output signal of the input daisy-chain circuit gate ID-inducing circuit 30, the input signal of the daisy chain, and the output signal of the daisy-chain electric field _ daisy-chain abnormal domain wheel-in portion 34 and The numbered abnormal signal input unit or ° AND circuit 33 of the input signal of the ID-inducing circuit 3〇 is only input from the daisy chain circuit 40 and the ID-inducing circuit 30 to the HIGH (1), that is, the normal signal is output. Indicates the number of "no U" (HIGH (1) signal). By means of the output signal of the circuit, the DSA1 is detected (the ^ID is not uncorrupted, and all the connectors of the intestine 1〇 and the host=20 are poorly connected, and (4) the line is "no abnormality". The present embodiment is from the The AND circuit 33 outputs "no abnormality" = day = 'the lock mechanism fixing state (LOCK) will be locked on the side of the motherboard 2 side. On the other hand, the daisy chain abnormal signal wheeling portion 34 or the ID number abnormal signal When the signal of the rounding is "(), that is, the abnormal signal, the drama indicates that there is an abnormal signal. By this, it is detected that the connection between the DSA10 and the main ^ is bad, or the ID of the DSA1G is not - As a result, "DaisyChain has an abnormality" or "The id number is abnormal"; 28 129
理。本實施型態係藉由該「有異常」訊號，而將在 “、反20側鎖固DSA1〇之鎖固機構控制成不能鎖固狀態 FREE)，同時使相當於「Daisy Chain有異常」或「ID 編ΐ有異常」之LED等亮燈，而將發生異常通知裝置外部。 (兴常檢測動作） . 接著，說明關於由如以上構成的本實施型態之附有基 板兴常檢測電路之半導體試驗裝置中的異常檢測動作。 φ 首先，準備2枚一組的0义410，裝載於主機板20之預 定位置，並嵌合、連接主機板10側之連接器21和各DSA10 之連接态14。將DSA10裝載於主機板2〇時，各dsai〇之id 6又疋用基板13的ID訊號輸出基板13a，會接觸在對應之主機 板20側之接觸銷用基板23的接觸銷23a，並輸出表示該 DSA10之ID編號的ID訊號。 人 幸月 1出之ID訊號經由接觸鎖23a而輪入至公用其板2 之ID —致電路3〇，並比較2牧DSA10之ID訊號而檢測出一& 致不一致’其結果為輸入至公用基板2〇a之AND電路33及 φ ID編號異常訊號輸入部35。 而且，當將DSA10裝載於主機板20，並連接Dsa〗〇# 主機板20之各連接器而導通離菊鏈電路4〇時，輸出離菊鍵 訊號，且輸入至公用基板20a之AND電路33及雛菊鍵里常 訊號輸入部34。 、 然後，在公用基板20a之AND電路33中，從各電路幸今 入之訊5虎為HIGH (1 )’亦即正常訊號時，輸出表示「、、」 有異常」之訊號（HIGH ( 1)訊號）。 29 I29^4Mi 因此，裝載於主機板2〇之2枚一組的DSA10之ID沒有 不一致，且DSA10和主機扳20之全部連接器正常地連接， 而成為「沒有異常」狀態，在主機板2〇侧鎖固DSA1〇之鎖 固機構會鎖固（LOCK) DSA10。因而，在該狀態下可進 行使用DSA10和主機板2〇之半導體零件之試驗。 另一方面，在雛菊鏈異常訊號輸入部34或Π)編號異常 訊號輸入部35輸入LOW (0)，亦即異常訊號時，DSA1〇 和主機板20之任意連接器有連接不良情形，且裝載於主機 板20之DSA10之組合有異常，而輸出表示「有異常」之訊 號。因此，進行相當於「Daisy Chain有異常」或「ID編號 有兴常」之處理。 亦即，將在主機板20侧鎖固DSA10之鎖固機構控制成 =能鎖固狀態（FREE)，同時使相當於「Daisy Chain有異 系丄或「仍編號有異常」之LED等亮燈，而將發生異常通 知衣置外部。因而，在該狀態下無法使用半導體試驗裝置， 而不胃在組合錯誤之DSA10直接裝設於主機板2〇的狀態下 進仃半導體試驗，或在部分連接器連接不良的狀態下進行 試驗。 2以上說明，根據本實施型態之附有基板異常檢測電 衣置，藉由具備表示DSA10之組合的id設定用基板 和檢測從ID設定用基板13輸出之辽>訊號的一致性之id 致兔路30，而賦予預定之id編號，僅判定該1〇編號之一 致，即可判疋2枚一組之DSA10是否為預定之組合。 因此，以不變更DSA10之構成或外形等，而將固有之 30 129娜 ID編5虎賦予在各D S A10之方式’可判別D S A10組合之適當 與否，並容易且確實地檢測出1DSA10之錯誤，而可癌實地 防止因DSA10之錯誤裝設等所造成的插座、搭載元件等之 破損、故障等。 此外，本實施型態由於輸入從DSA10側傳來的id訊 , 唬，而判定該^^人10之組合是否正確，因此在將DSA10裝 載於主機板20侧之同時可判斷該組合之適當與否，而可迅 籲祕進行判植理，並可有效率地進行半導體試驗裝置本 來的試驗作業或處理等。 即使增減量7 = 號而容易地對二亦可稭由附加、冊獅編 檢測電路。〜貝見—種泛用性、擴張性佳之異常 部連ί器;經由DSA10和主機板2〇之全 參 又，葬σ "吊寺，仍可立刻檢測出。 40，以檢測連接不良1^^到全部連接器間的離菊鏈電路 2〇間的連接器之同時:二^可在連接DSA]〇和主機板 因此，即使且供目士 Μ、、ϋ亥不良、不協調。 之半導體試驗裝置，仍可2連接器之DSA10和主機板2〇 落等，而可實現1不會^ 2實地發現連接不良或脫 作不良或作業效率低落等益之連接不良所造成的動 本實施型態細具^D—致高賴驗裝置。尤其， 电路30和雛菊鏈電路4〇的方 129¾¾^ 式，可確實地檢測出DSA10之組合異冑，同時可檢測出關 於DSA10和主機板20間的連接器連接不良。 因此，在組合使用複數個DSA10且各DSA10具備複數 個連接器Μ之半導顏驗K置巾，會賦雅職且確實地 杈測出DSA10之組合異常，同時亦可容易地發現多數連接 器之連接不良，而可提供一種泛用性、擴張性更佳之可靠 性高的半導體試驗裝置。 以上關於本發明之附有基板異常檢測電路之裝置，係 以較佳實施型態為例加以說明，但本發明之附有基板異常 檢測電路之裝置，不僅限定於上述實施型態者，當然亦可 在本發明之範圍内實施各種變更。 例如，上述實施型態雖係將ID設定用基板僅使用於設 定、輸出一組DSA之ID編號，但亦可將其作為設定、輸出 使用於其他用途之任意編號之編號設定機構來使用。亦 即’上述貫施型態係ID設定用基板設定、輸出2位元訊號， 同時將該2位元訊號全部當作表示ID編號之id訊號來使 用’但例如若將ID設定用基板設定成可設定、輸出6位元 訊號之構成，則2位元可當作本發明之ID訊號來使用，而 可將剩餘之4位元部分分配為其他訊號用。因此，例如可當 作依照使用對象而輸入、設定任意序列編號、使用者編號 或管理編號等之編號機構。 而且，上述實施型態所示之半導體試驗裝置，係以具 備iD —致電路和雛菊鏈電路的方式，在進行檢測DSA之組 合異常之同時，亦進行DSA、主機板間的連接器連接不良 32Reason. In this embodiment, the "with abnormality" signal is used to control the locking mechanism of the DSA1〇 in the reverse 20 side to be in an unlockable state FREE, and at the same time, the equivalent of "Daisy Chain is abnormal" or The LED such as "ID is edited abnormally" lights up, and an abnormality is notified to the outside of the device. (Random detection operation) Next, an abnormality detecting operation in the semiconductor test apparatus with the substrate development detecting circuit of the present embodiment configured as described above will be described. φ First, two sets of 0 sense 410 are prepared, mounted on a predetermined position of the motherboard 20, and fitted and connected to the connector 21 on the motherboard 10 side and the connected state 14 of each DSA 10. When the DSA 10 is mounted on the motherboard 2, the id 6 of each dsai 疋 uses the ID signal output substrate 13a of the substrate 13 to contact the contact pin 23a of the contact pin substrate 23 on the side of the corresponding motherboard 20, and outputs An ID signal indicating the ID number of the DSA 10. The ID signal from the lucky one is rotated to the common ID of the board 2 via the contact lock 23a, and the ID signal of the DSA10 is compared and the ID of the DSA10 is compared to detect an inconsistency. The result is input to The AND circuit 33 of the common substrate 2A and the φ ID number abnormal signal input unit 35. Moreover, when the DSA 10 is mounted on the motherboard 20 and connected to each connector of the Dsa 〇# motherboard 20 to turn on the daisy chain circuit 4, the output is separated from the daisy key signal and input to the AND circuit 33 of the common substrate 20a. And the daisy key frequent signal input unit 34. Then, in the AND circuit 33 of the common substrate 20a, when the 5th tiger is HIGH (1)', that is, the normal signal, the signal indicating ",," is abnormal" (HIGH (1) ) signal). 29 I29^4Mi Therefore, the IDs of the DSA10s of the two groups mounted on the motherboard 2 are not inconsistent, and all the connectors of the DSA10 and the host 20 are normally connected, and become "no abnormal" state on the motherboard 2 The locking mechanism of the side locking DSA1〇 locks (LOCK) the DSA10. Therefore, the test of the semiconductor parts using the DSA 10 and the motherboard 2 can be performed in this state. On the other hand, when the daisy chain abnormality signal input unit 34 or the 编号) number abnormal signal input unit 35 inputs LOW (0), that is, the abnormal signal, the DSA1 〇 and any connector of the motherboard 20 have a poor connection condition and are loaded. The combination of the DSA 10 on the motherboard 20 has an abnormality, and the output indicates a signal that "there is an abnormality". Therefore, the processing corresponding to "Daisy Chain has an abnormality" or "ID number is normal" is performed. That is, the locking mechanism that locks the DSA 10 on the side of the motherboard 20 is controlled to be in a lockable state (FREE), and at the same time, the LED corresponding to the "Daisy Chain is different" or "still numbered abnormal" is turned on. , and an exception will be notified to the outside of the clothing. Therefore, in this state, the semiconductor test apparatus cannot be used, and the semiconductor test is not performed in a state in which the DSA 10 having the wrong combination is directly mounted on the motherboard 2, or the test is performed in a state in which the partial connector is poorly connected. In the above description, the substrate abnormality detecting electric clothing is provided, and the id of the id setting substrate including the combination of the DSA 10 and the identities of the signals output from the ID setting substrate 13 are detected. To the rabbit road 30, and given the predetermined id number, it is determined whether the two sets of DSAs 10 are the predetermined combination. Therefore, it is possible to discriminate whether the DS A10 combination is appropriate or not, and to easily and surely detect the 1DSA10, by changing the composition or shape of the DSA 10, and giving the unique 30 129 Na ID code to each DS A10. In the case of an error, it is possible to prevent damage or malfunction of the socket or the mounted component caused by the erroneous installation of the DSA 10 or the like. In addition, in this embodiment, since the id message transmitted from the DSA 10 side is input, and it is determined whether the combination of the ^10 is correct, the DSA 10 can be loaded on the side of the motherboard 20 while judging the appropriateness of the combination. No, it can be quickly and arbitrarily judged, and the original test operation or processing of the semiconductor test apparatus can be performed efficiently. Even if the amount of increase or decrease is 7 =, it is easy to use the attached circuit. ~ Bei Jian - a kind of generality, excellent expansion of the abnormality of the ί 器; through the DSA10 and the motherboard 2 〇 全 又 , 葬 葬 葬 葬 葬 葬 葬 葬 吊 吊 吊 吊 吊 吊 吊 吊 吊 吊 吊 吊 吊 吊 吊 吊 吊 吊 吊 吊 吊 吊40, to detect the connection failure 1 ^ ^ to the connector between the daisy chain circuit 2 全部 between all the connectors: two ^ can be connected to the DSA] 主机 and the motherboard so that even for the gentry, ϋ Poor and uncoordinated. The semiconductor test device can still be used for the DSA10 of the 2 connector and the motherboard 2, etc., and can realize the problem that the connection failure caused by poor connection or poor work efficiency or low operating efficiency can be found in the field. Implementation of the type of fine ^ D - high inspection device. In particular, the circuit 30 and the daisy chain circuit 4 〇 293 , , , , 可 可 可 可 可 。 。 。 。 DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS DS Therefore, when a plurality of DSAs 10 are combined and each DSA 10 has a plurality of connectors, the semi-conducting sensation K-type towel will be used to accurately detect the abnormality of the combination of the DSA 10, and it is also easy to find a plurality of connectors. The connection is poor, and a semiconductor test device with high reliability and high expandability is provided. The apparatus having the substrate abnormality detecting circuit of the present invention is described by way of a preferred embodiment. However, the apparatus with the substrate abnormality detecting circuit of the present invention is not limited to the above embodiment, and of course Various changes can be made within the scope of the invention. For example, in the above-described embodiment, the ID setting substrate is used only for setting and outputting the ID number of a group of DSAs, but it may be used as a number setting means for setting and outputting an arbitrary number for other uses. In other words, the above-described ID system setting substrate is set and a 2-bit signal is output, and the 2-bit signal is used as the ID signal indicating the ID number. However, for example, the ID setting substrate is set to The composition of the 6-bit signal can be set and output, and the 2 bits can be used as the ID signal of the present invention, and the remaining 4 bit portions can be allocated for other signals. Therefore, for example, it can be used as a numbering mechanism for inputting and setting an arbitrary serial number, a user number, or a management number in accordance with the object of use. Further, in the semiconductor test apparatus shown in the above embodiment, the combination of the DSA and the daisy-chain circuit is used to detect the abnormality of the combination of the DSA, and the connector connection between the DSA and the motherboard is also poor.
I29Z4H 之測，但其當然亦可僅具備其中一者。 又，在上述實施型態中，判定在10 一致電路組人 當與否的基板群，雖然採用2牧—組之DSA為例，但二= 限定於2枚一組者，只要是2牧以上，組、犧Γίί 然也可以。同樣地，在上述實施型態中，、田 咖連接不良之連接器數量，亦奴為複數連接器 只要在連接的基板間至少具傷各―個連接器即可。〜、 再者，上述實施型態雖係採用半導體試驗裝置 座板和主機板之連接隸卸為例，來說明本發明知田 常檢測電路，但使財發明之異常檢測電路之#切: 限於具備DSA和主機板之半導體試驗裳置。亦_，、= 之附有基板異常檢測電路之裝置只要是組合二個以 板而，接於對方側基板，或具備—個或二個以上連= =藉由連接在具備對應之連接器的對方側基板而^之 衣置，任何基板或裝置均可適用。 一 [產業利用性] 壯罢如=亡說明，根據本發明之附有基板異常撿測電路之 衣、’=衩數基板構成一組而連接在對方側基板之裝置 中，以輸入表示該一組基板之組合的仍訊號之方 二 二備^ ^及基板之組合的一致不一致之一致電路等比較機 ，可谷易且確實地檢測組合使用不同種類基板的。 ^此I防範因基板之錯誤裝設所造成的基板、插座 個 障等’尤其適用於同時使用組合有複數 ’、叙數插座板之DSA之半導體試驗裝置。 j292^. 具備一個或::::::附有基板異常檢測電路之裝置， 或二個以上連接=彳器:繼接在具備對應之-個 連接的全部連接器而“由具備經由 雛菊鏈電路，而可衮ί : ί編訊號輪出結果之 接不良或脫4 了幾測叫 成的動作不良或作業改;:;因之連接不良所造 接有複數個連接心其適用於具備同時連 【實施方式】。之主機板和插座板的半導體試驗裝置。 電路ΐ y—實㈣g之附有基板異常檢測 二卞今版忒驗裝置之分解斜視圖。 之編，、(b)為 板異^圖^概念性地表示本發明之一實施型態之附有基 接觸销二半導體試驗裝置中的定用基板和 ”之主要部分剖面前視圖。 柘田H圖為概念性地表示本發明之一實施型態之附有基 導體試驗裝置一定用基板和 檢- 、、半‘體试驗裝置中的雛菊鏈電路之說明 Ι2924^Ήίι 圖。 第7圖為概念性地表示本發明之一實施型態之附有基 板異常檢測電路的半導體試驗裝置中的公用基板之方塊 圖。 第8圖為概念性地表示本案申請人在日本特願 2002-047186號中提出之半導體試驗裝置之說明圖，（a) 為從主機板側取下DSA狀態之前視圖，（b)為（a)所示 之DSA之底視圖。 【主要元件符號說明】 10、110 DSA (元件指定轉接器）I29Z4H is measured, but of course it can only have one of them. Further, in the above-described embodiment, it is determined that the substrate group of the 10-consistent circuit group is a group or not, and the DSA of the 2-grass group is taken as an example, but the second is limited to two groups, as long as it is 2 or more , group, sacrifice Γ ί 然 can also. Similarly, in the above embodiment, the number of connectors that are poorly connected to the field is also a plurality of connectors, as long as at least one connector is damaged between the connected substrates. Further, although the above-described embodiment is an example in which the connection between the semiconductor test device base plate and the main board is used as an example to explain the known field detection circuit of the present invention, Semiconductor test stand with DSA and motherboard. Also, the device with the substrate abnormality detecting circuit of _, and = is connected to the other side substrate as long as the two boards are combined, or one or two or more are connected == by being connected to the corresponding connector The substrate of the other side can be placed, and any substrate or device can be applied. [Industrial Applicability] The use of the substrate abnormality measuring circuit according to the present invention, the '= number of substrates constitutes a group and is connected to the other side of the substrate, and the input indicates the one. The comparator of the combination of the combination of the substrate and the combination of the substrate and the matching circuit of the combination of the substrates can be used to detect and use different types of substrates in combination. ^This I protects the substrate, the socket barrier, etc. caused by the erroneous mounting of the substrate. It is especially suitable for the simultaneous use of a semiconductor test device in which a DSA of a plurality of 'sector socket boards is combined. J292^. One or :::::: device with substrate anomaly detection circuit, or more than two connections = 彳: relaying all connectors with corresponding connections - "by having a chain of daisy Circuit, but 衮ί : ί 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号 信号Even the semiconductor test device of the main board and the socket board of the [Embodiment] circuit ΐ y-real (four) g with the substrate abnormality detection II. The exploded view of the current inspection device. The edit, (b) is the board FIG. 2 is a cross-sectional front view showing a principal part of a base contact pin semiconductor test apparatus according to an embodiment of the present invention. The Putian H diagram is a diagram conceptually showing the substrate of the base conductor test apparatus and the daisy chain circuit in the half-body test apparatus, which is an embodiment of the present invention, Ι2924^Ήίι. Fig. 7 is a block diagram conceptually showing a common substrate in a semiconductor test apparatus with a substrate abnormality detecting circuit according to an embodiment of the present invention. Fig. 8 is an explanatory view conceptually showing a semiconductor test apparatus proposed by the applicant of the present application in Japanese Patent Application No. 2002-047186, wherein (a) is a front view of the DSA state removed from the motherboard side, and (b) is (a) ) The bottom view of the DSA shown. [Main component symbol description] 10, 110 DSA (component designation adapter)
10a DSA-A10a DSA-A
10b DSA-B η、in 插座板 12 、 112 SB框架 13 ID設定用基板 13a ID訊號輸出銲墊 13b 通孑L 13c ID編號設定銲墊 13d 跨接線 13e GND銲墊 14 > 21 ^ 114、121連接器 14a、21a短路線 15 定位孔 20、120 主機板 35 Ι292ι44§〇Ιίπ 20a 公用基板 22 定位銷 23 接觸銷用基板 23a 接觸銷 30 ID —致電路 33 AND電路 34 雛菊鏈異常訊號輸入部 35 ID編號異常訊號輸入部10b DSA-B η, in socket board 12, 112 SB frame 13 ID setting substrate 13a ID signal output pad 13b 孑 L 13c ID number setting pad 13d jumper 13e GND pad 14 > 21 ^ 114, 121 Connector 14a, 21a Short-circuit line 15 Positioning hole 20, 120 Mother board 35 Ι 292 ι 44 § 〇Ι 20 20 公用 common substrate 22 Locating pin 23 Contact pin substrate 23a Contact pin 30 ID 电路 circuit 33 AND circuit 34 Daisy chain abnormal signal input portion 35 ID number abnormal signal input unit
40 離菊鏈電路40 daisy chain circuit
3636
Claims (1)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002056570A JP3790175B2 (en) | 2002-03-01 | 2002-03-01 | Device with substrate abnormality detection circuit |
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| Publication Number | Publication Date |
|---|---|
| TW200634322A TW200634322A (en) | 2006-10-01 |
| TWI292484B true TWI292484B (en) | 2008-01-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| TW092104151A TWI277757B (en) | 2002-03-01 | 2003-02-27 | Device with a circuit for detecting an abnormal substrate |
| TW094143705A TWI292484B (en) | 2002-03-01 | 2003-02-27 | Device with a circuit for detecting an abnormal substrate |
| TW096116860A TWI325060B (en) | 2002-03-01 | 2003-02-27 | Device with a circuit for detecting an abnormal substrate |
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| TW092104151A TWI277757B (en) | 2002-03-01 | 2003-02-27 | Device with a circuit for detecting an abnormal substrate |
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| TW096116860A TWI325060B (en) | 2002-03-01 | 2003-02-27 | Device with a circuit for detecting an abnormal substrate |
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| JP (1) | JP3790175B2 (en) |
| KR (3) | KR100966686B1 (en) |
| CN (2) | CN1811479A (en) |
| DE (1) | DE10392347T5 (en) |
| MY (1) | MY134319A (en) |
| TW (3) | TWI277757B (en) |
| WO (1) | WO2003075026A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100395718C (en) * | 2004-03-13 | 2008-06-18 | 鸿富锦精密工业（深圳）有限公司 | Motherboard function test board |
| KR100897349B1 (en) | 2007-06-12 | 2009-05-15 | 주식회사 유니테스트 | Tester for testing semiconductor device |
| CN101551427B (en) * | 2008-03-31 | 2012-04-04 | 无锡松下冷机有限公司 | Substrate detecting method |
| TWI385773B (en) * | 2008-05-21 | 2013-02-11 | Lefram Technology Corp | Lead frame carrier and method of manufacturing the same |
| CN102445635B (en) * | 2010-10-11 | 2014-12-03 | 中国电信股份有限公司 | Quick tester for wire jumper |
| US8878182B2 (en) * | 2011-10-12 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Probe pad design for 3DIC package yield analysis |
| KR101316785B1 (en) | 2013-07-31 | 2013-10-10 | 테스토피아 주식회사 | Apparatus for changing socket board using vertical type cylinder |
| CN103440567A (en) * | 2013-08-28 | 2013-12-11 | 杭州华三通信技术有限公司 | Method and device for differentiating devices sold to different markets |
| KR102377694B1 (en) * | 2020-07-28 | 2022-03-23 | 주식회사 에스티아이테크 | A Bracket for Securing a Board and an Assembly with the Same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US4787143A (en) * | 1985-12-04 | 1988-11-29 | Tdk Corporation | Method for detecting and correcting failure in mounting of electronic parts on substrate and apparatus therefor |
| JP3730340B2 (en) * | 1996-11-20 | 2006-01-05 | 株式会社アドバンテスト | Semiconductor test equipment |
| US6480751B1 (en) * | 1997-01-16 | 2002-11-12 | Matsushita Electric Industrial Co., Ltd. | Component supplying method, component arrangement data forming method and electronic component mounting apparatus using the methods |
| US6040530A (en) * | 1997-12-05 | 2000-03-21 | Hewlett-Packard Company | Versatile printed circuit board for testing processing reliability |
| JPH11326448A (en) * | 1998-05-20 | 1999-11-26 | Advantest Corp | Ic testing device |
| CN1240939A (en) * | 1998-06-09 | 2000-01-12 | 株式会社爱德万测试 | Electronic component and device testing unit |
| KR20000008963U (en) * | 1998-10-29 | 2000-05-25 | 김영환 | Semiconductor Device Package Tester with Novel Socket Adapter |
| JP2000310664A (en) * | 1999-04-27 | 2000-11-07 | Ando Electric Co Ltd | Ic testing device and external equipment discriminating method in the same |
| JP3797529B2 (en) * | 1999-05-20 | 2006-07-19 | 富士写真フイルム株式会社 | Integrated circuit with continuity detection function |
| JP2001004701A (en) * | 1999-06-22 | 2001-01-12 | Advantest Corp | Method for recognizing id and apparatus for recognizing id using this method |
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2002
- 2002-03-01 JP JP2002056570A patent/JP3790175B2/en not_active Expired - Fee Related
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2003
- 2003-02-25 CN CNA2006100042601A patent/CN1811479A/en active Pending
- 2003-02-25 DE DE10392347T patent/DE10392347T5/en not_active Withdrawn
- 2003-02-25 KR KR1020057023622A patent/KR100966686B1/en active IP Right Grant
- 2003-02-25 WO PCT/JP2003/002037 patent/WO2003075026A1/en active Application Filing
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| Publication number | Publication date |
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| KR20040082446A (en) | 2004-09-24 |
| JP2003255020A (en) | 2003-09-10 |
| TW200303990A (en) | 2003-09-16 |
| KR20100050568A (en) | 2010-05-13 |
| TW200634322A (en) | 2006-10-01 |
| CN1639579B (en) | 2011-01-26 |
| KR20050121763A (en) | 2005-12-27 |
| CN1639579A (en) | 2005-07-13 |
| TW200739100A (en) | 2007-10-16 |
| WO2003075026A1 (en) | 2003-09-12 |
| TWI277757B (en) | 2007-04-01 |
| KR100966686B1 (en) | 2010-06-29 |
| DE10392347T5 (en) | 2005-04-07 |
| MY134319A (en) | 2007-12-31 |
| CN1811479A (en) | 2006-08-02 |
| TWI325060B (en) | 2010-05-21 |
| KR100624060B1 (en) | 2006-09-20 |
| JP3790175B2 (en) | 2006-06-28 |
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