DE10392347T5 - Device with a circuit for detecting substrate defects - Google Patents

Abstract

Apparatus equipped with a circuit for detecting substrate defects, comprising at least one substrate group of a plurality of combined substrates and an opposing substrate to be bonded to the substrate group,
wherein the device provided with a circuit for detecting substrate errors comprises:
ID setting boards provided on the respective substrates of the substrate group for setting corresponding fixed ID numbers to be assigned to the substrate group and outputting ID signals indicative of the corresponding ID numbers;
ID signal input boards provided on the opposite substrate corresponding to the substrate group for receiving ID signals output from the ID setting boards, and
Comparing means for receiving ID signals output from the ID signal input boards and comparing the ID signals of the respective substrates, wherein
the device equipped with a circuit for detecting substrate errors detects a combination error of the substrate in the substrate group.

Description

technical area

The The present invention relates to a device that can be connected by connecting a Substrate having one or more connection elements on one opposite substrate is operating, such as a semiconductor test device for testing of semiconductor components.

Especially The present invention relates to a device comprising a circuit for detecting substrate defects, which is a device having a Variety of substrates included in a set of substrates combined with an opposite substrate too connect, with a circuit for detecting substrate errors equipped device Comparing means, such as a matching circuit for detecting a match or mismatch a combination of the substrates in the set by receiving ID signals for The combination of substrates is so easy and so reliable to capture a combination of different types of substrates, whereby the occurrence of a damage, an error or such as substrates, receptacles and equipped components is prevented, and with a circuit for detecting substrate errors equipped device for a Semiconductor test equipment in which a plurality of DSAs having a plurality combined from socket fields to used at the same time to become.

In addition concerns The present invention relates to a device comprising a circuit for detecting substrate defects, wherein a substrate of a or more, corresponding connection elements, which are located opposite one another Substrate are connected to one or more connection elements, the one equipped with a circuit for detecting substrate errors Device one Daisy chain circuit for transfer a signal over all connected connection elements includes an output result to capture the signal so easily and reliably a bad connection or to detect a failure of corresponding connection elements, whereby the occurrence of a disorder, a decrease in processability or the like due the poor connection of the connecting elements is prevented and equipped with a circuit for detecting substrate errors Device for a semiconductor test device with a Motherboard and female panels is suitable, of which a variety be connected by connecting elements at the same time.

professional background

One Semiconductor test equipment For testing semiconductor components is typically a device that components by mounting a semiconductor component to be tested on substrates, called socket fields; Connect of the female panel to a substrate, called motherboard, on the Housing main page the test device; Inputting and outputting a fixed electrical signal, that for the Testing is required over the motherboard is testing.

at a conventional one Semiconductor test equipment Here are sockets for mounting a semiconductor component and a main board on the housing main side of the tester electrically to one another by wiring, soldering or the like, whereby the socket panels and the motherboard be formed in an integral, inseparable configuration. In such a conventional one Semiconductor test equipment with the jacks and the motherboard inseparable connected, it is not possible to individually remove or replace the jacks, which is one Problem of difficulty, for testing quite diverse Components ready to be.

Nowadays, with the increase in complexity and density of the semiconductor components, becomes a large number developed and proposed on semiconductor components that are different in the package configuration or a pen configuration. To test such structurally different semiconductor components, it is necessary to use socket fields as the interface of the semiconductor component exchange them so they fit in the pen configuration or package configuration each of the different semiconductor components fit into it. Because the conventional Semiconductor test equipment by inseparably fixing the socket field on the motherboard the main housing side of the test device configured as mentioned above, it was difficult just to remove or replace the jacks, and when testing other types of semiconductor components it was necessary the whole test device including to replace a motherboard.

In such a conventional semiconductor test apparatus, which requires the change of the whole apparatus, it takes a lot of time to introduce a new test apparatus, as well as a longer test period and synchronization or change of a more expensive test apparatus for each semiconductor component, which leads to increasing test costs and waste of resources. That made it extremely difficult for to be ready to test quite different semiconductor components just by swapping the tester.

Then the Applicants of the present invention have decided the ones mentioned above To solve problems, and a semiconductor test device prepared with socket panels removable from a motherboard, by using connection elements as a connection structure between the socket panels and the motherboard in the semiconductor test equipment, which are separated from each other are separable, which described in Japanese Patent Application No. 2002-047186 are.

The 8th Fig. 11 shows illustrative views, each of which conceptually shows a semiconductor testing apparatus proposed by the inventors of the present application in Japanese Patent Application No. 2002-047186, wherein 8 (a) is a front view showing DSAs taken from a motherboard and 8 (b) a top view from below of the DSAs in 8 (a) is. As shown in these figures. Does this semiconductor test device have DSAs 110 with several socket fields 111 mounted on it, and a motherboard 120 which are both removable.

DSAs (Device Specific Adapters) 110 are jack-field substrates, each of which is an integral combination of a variety of female panels 111 and connection elements 114 is fixed on a SB frame (Socket Frame) 112 are mounted.

For each of the DSAs 110 are the multiple socket fields 111 arranged in rows on the SB frame as a base and the multiple connection elements 114 as it is in 8 (b) shown with the (not shown) connecting elements on the motherboard 120 engage, are exposed to the top. Because the DSAs 110 on the motherboard 120 are mounted as it is in 8 (a) is shown, are the connection elements 114 at the bottom of the DSAs with the corresponding connection elements 121 engaged on the motherboard side and are connected to it so that the multiple socket fields 111 at the DSAs, electrically with the motherboard 120 connected is. To test a variety of semiconductor components at once, the DSAs 110 here a set of multiple DSAs (a set of 2 or 4 DSAs) of the same configuration mounted on a motherboard and an array of a set of 2 DSAs 110 is in 8 (b) shown.

Because the DSAs 110 on which a variety of socket fields 111 are mounted, via the connection elements 114 removable with the motherboard 120 In such a semiconductor test device, any DSAs may be connected 110 on the motherboard 120 mounted or removed and are on the motherboard 120 interchangeable. For example, when testing semiconductor components of other package configuration or pin configuration, the DAS 110 from the motherboard 120 be removed (see 8 (a) ) and other DSAs 110 are replaced, on which the semiconductor components to be tested corresponding female panels are mounted.

Accordingly, it is in such a semiconductor test apparatus, only the DSAs for mounting of socket boxes on it that need to be changed to to test different types of semiconductor components the need to change of the entire device including the motherboard is eliminated, which has been necessary in the conventional is, and above addition, a semiconductor test device realized at low cost and with excellent versatility becomes.

Here, in a semiconductor tester, as mentioned above where DSAs are removable from the motherboard are on the motherboard multiple DSAs with female fields of the same Type, which are mounted on it, mounted such that a large number of semiconductor components can be tested at once, like it has been described above. Since the DSAs are typically in the same shape or in appearance, even if the jacks fields are different Type, construction or the like, it is difficult to make the difference of the socket fields between the DSAs. That's why it is possible that two or more DSAs with sockets, which are in type or differ in structure, in the wrong combination on the motherboard are mounted.

If the DSAs having different types of socket fields on them mounted on the motherboard are the semiconductor components to be tested not compatible with the socket configuration of the socket fields. In this situation, when the semiconductor components are forced Being mounted on the socket panels can be a physical damage for the IC sockets, the socket lines, devices (semiconductor components), modification kits to change the devices or the like occur. That's why it was necessary to prevent that incorrect placement of DSAs occurs.

For example, as a means of preventing DSAs from being mis-combined with jack boxes of different types mounted thereon, it can be envisaged that pins and pin holes or protrusions and indentations are formed in the frames of DSAs so that they only intervene between properly combined DSAs in one can be brought. However, if projections and indentations or engagement structure are provided in the frame of DSAs, the engagement structure for each type of socket array must be changed, which poses a problem that each time the semiconductor components to be tested are changed, new frames of the DSAs must be designed and manufactured.

If an engagement structure or projections and indentations or Pins are provided in frames of DSAs, in addition to the DSA per se thinner, which is a problem of reducing the strength of the frames.

Meanwhile, in a semiconductor tester of the removable DSA type as shown in FIG 8th 8, multiple socket arrays and terminal elements are arranged in such a manner that a predetermined number of socket arrays and terminal elements are arranged in a row to be modular (see FIG 8 (b) ); many connectors are provided on a DSA, and accordingly many connectors are provided on the side of the motherboard. In this situation, when DSAs are mounted on or removed from the motherboard, a bad connection or connection failure may occur in a large number of terminals between the female panels and the motherboard.

If such a connection error is found in the connection elements, It becomes difficult to carry out the normal testing, which is the processing efficiency diminish and above beyond the reliability of the test device can diminish.

in the In view of the foregoing, the claims have to development of a new agent increased to detect and prevent the occurrence a wrong combination, an incorrect use or the like of the substrate, a bad connection, connection errors or like in devices, which allows the use of substrates (DSAs) of the same type without errors combined, or a device, in which often many connection elements are connected, separated or are keyed between substrates, such as a type of semiconductor tester with removable DSAs. Then the applicant has the present Invention further decided to achieve this goal and a semiconductor test system of the present invention, which is capable of a incorrect placement of multiple substrates or the like with reliability prevent and a bad connection of multiple substrates or the like with reliability capture.

The The present invention has been made in view of the above. It It is an object of the present invention to provide a circuit to provide equipment for detecting errors, which a machine that has a plurality of substrates in a set of substrates, those with one opposite substrate to be combined is combined, the one equipped with a circuit for detecting substrate errors Device comparison means includes, such as a matching circuit for detecting a match or mismatch of one Combining the substrates in the set by receiving ID signals, the for The combination of substrates is so easy and reliable To capture a combination of different types of substrates, whereby the occurrence of a damage, an error or such as substrates, receptacles and equipped components is prevented, and equipped with a circuit for detecting substrate errors Device suitable for a semiconductor test device is where a variety of DSAs with a variety of socket fields be combined to be used at the same time.

It is another object of the present invention, one with a To provide a fault-equipped device detection circuit, in which a substrate with one or more corresponding connection elements, those with one opposite Substrate are connected to one or more connection elements, the one equipped with a circuit for detecting substrate errors Device one Daisy chain circuit for transfer a signal over all connected connection elements includes an output result to capture the signal so easily and reliably a bad connection or to detect a failure of corresponding connection elements, whereby the occurrence of a disorder, a reduction in processability or the like due to poor connection of the connecting elements is prevented, and equipped with a circuit for detecting substrate errors Device for a semiconductor test device with a Motherboard and female panels is suitable, of which a variety of Connection elements are connected simultaneously.

epiphany the invention

In order to achieve the above-mentioned objects, a device equipped with a substrate defect detection circuit according to claim 1 is a device having at least one substrate group of a plurality of combined substrates and a confronting substrate connected to the sub-substrate and the apparatus equipped with a circuit for detecting substrate defects comprises: ID setting boards provided on the respective substrates of the substrate group for setting respective set ID numbers to be assigned to the substrate group, and outputting ID signals indicative of the corresponding ID numbers; ID signal input boards provided on the opposite substrate corresponding to the substrate group for receiving ID signals output from the ID setting boards and comparing means for receiving ID signals formed of the ID signal boards; Input boards are output, and comparing the ID signals of the respective substrates, wherein the equipped with a circuit for detecting substrate errors detects a combination error of the substrate in the substrate group.

There the invention, with Device ID adjustment boards equipped with a circuit for detecting substrate errors and comparing means, such as matching circuitry for detecting a coincidence of ID signals output from the ID setting boards, It only needs ID numbers that indicate that two or more Substrate of a substrate group a fixed combination satisfied so that they receive the ID numbers from the substrates, compare and match or mismatch determine the ID numbers. That makes it possible a combination of multiple substrates only with ID numbers corresponding to the substrate group of substrates is specific to judge, without the configuration or the profile to change the substrates and above also light and reliable to capture a combination of different substrates, thereby the occurrence of damage, one Error or the like of socket panels and equipped equipment due to is prevented by incorrect placement of the substrates.

There the assessment of a combination of substrates by entering ID signals off performed on the substrates she can, about it Be performed at the same time when the substrates on the device be mounted, which ensures a quick determination it possible effectively, an original test operation and processing perform, which are carried out by mounting the substrates on the device.

There the combination of substrates by assigning ID numbers The substrates can be identified if the substrates are in type or in number may be increased or decreased, the ID numbers above addition only or added be reduced, creating a circuit for detecting errors realized with excellent versatility and scalability becomes.

Furthermore is a device equipped with a circuit for detecting substrate defects, according to Claim 2 a device a substrate with connection elements and an opposite Substrate having connection elements, which with the connection elements of the substrate to be connected, the with a circuit for Detecting substrate errors equipped device comprises: a daisy chain circuit for receiving a signal from a terminal of the substrate or of opposite located substrate and transferring the signal over the corresponding connection elements logically to all connection elements, to detect the presence or absence of an output signal, the one equipped with a circuit for detecting substrate errors Device one Connection error of all corresponding connection elements of the substrate or of opposite detected substrate detected.

According to the way configured with a circuit for detecting substrate errors equipped device of the present invention, since the daisy chain circuit for transmitting a signal over all of one or more terminal elements may be a bad one Connection, a connection error or the like between any one the connection elements are detected immediately. Because the daisy chain circuit a bad connection or the like by transmission detected a signal between the connection elements, a bad connection, a connection error or the like between any of the terminal elements are detected directly what Ensuring a quick determination makes it possible becomes, effectively, an original one Test operation and processing by mounting the Substrates are running on the device.

Also in the event that a big one Number of connection elements are connected at the same time, it is possible with such a configuration, easy and reliable to find a bad connection or a failure realized a highly reliable test device that will be a needy one Operation or a reduction in processability as a result of poor connection of the connection elements can avoid.

Moreover, a device equipped with a circuit for detecting substrate defects, according to claim 3, is a device comprising at least one substrate group of a plurality of combined substrates with terminal elements and an opposing substrate with terminal elements connected to the corresponding terminals of the substrate of the substrate group, the device equipped with a circuit for detecting substrate defects comprising: ID setting boards provided on the respective substrates of the substrate group for setting corresponding fixed ID numbers to be assigned to the substrate group and outputting ID signals indicative of the ID signals; ID signal input boards provided on the opposite substrate corresponding to the substrate group for receiving ID signals output from the ID setting boards; Comparing means for receiving ID signals output from the ID signal input boards and comparing the ID signals of the respective substrates, and a daisy-chain circuit for receiving a signal from a terminal of the substrate or the opposite substrate and transmitting the signal through the respective terminal elements logically to all the terminal elements to detect the presence or absence of an output signal, the device equipped with a circuit for detecting substrate errors including a combination error of the substrate in the substrate group and a connection failure of all corresponding terminal elements of the substrate or the opposite substrate detected.

According to the way configured with a circuit for detecting substrate errors equipped device of the present invention, as it contains both the comparison agent and such as an adjustment circuit and the like for determining a Coincidence of ID numbers assigned to the substrate groups, as well as the daisy chain circuit for detecting a bad connection When connecting the connecting elements, it is possible a combination error of the substrate and a poor connection between the connection elements the substrate and the opposite Substrate with reliability capture. With this configuration, in a device that has a Variety of combined substrates used, each of a variety substrates having substrates facing one another Substrate is to combine a combination error of the substrate by assigning ID numbers and a bad connection of the plurality be detected by connecting elements with reliability, thereby a highly reliable one Device provided which is excellent in versatility and scalability is.

Furthermore are at one with a circuit for detecting substrate errors equipped device according to claim 4, the ID setting boards a plurality of ID setting boards, which are arranged on each substrate, and set an ID number and to the corresponding substrates.

The thus constructed, with a circuit for detecting substrate errors equipped device The present invention includes a plurality of ID setting boards and all numbers through the multitude of ID setting boards can be adjusted build up an ID signal. Or an ID number can be arbitrary on the Basis of the substrate used, type of the like can be adjusted. When the substrates increase or decrease in type or number Need to become the ID numbers with this configuration only added or decreased which provides a highly reliable device which is excellent in versatility and scalability is.

Furthermore becomes at one with a circuit for detecting substrate errors equipped device according to claim 5, the daisy-chain circuit through the connection elements of Substrate and the opposite located substrate, each of which one or more pins shorted in the corresponding substrates or the opposite Substrate to be connected.

According to the way configured with a circuit for detecting substrate errors equipped device The present invention uses existing pins of the connection elements used, which are provided between the substrates, which together should be connected to short the pins in the substrates, so that it is a daisy-chain circuit of the present invention for transmitting a signal over remove all connection elements. With this expansion of the daisy chain circuit The present invention may be a bad connection, a connection failure the variety of connection elements without providing a special Circuit, means or the like can be detected, thereby it possible is made, a highly reliable Provide device, that a bad connection between the ones mounted on the device Can capture substrates without need to enlarge or Increase the complexity of the substrate, device or like.

Furthermore include in one equipped with a circuit for detecting substrate errors Device after Claim 6 the substrates DSAs, the one or more socket fields have mounted on which to be tested semiconductor components and connected, and the opposite substrate a Motherboard of a semiconductor test device, on which the DSAs are mounted and connected.

Furthermore include in one equipped with a circuit for detecting substrate errors Device after Claim 7 the substrates DSAs, the one or more socket fields have mounted on which to be tested semiconductor components and, the substrate groups are a combination of the substrates include the DSAs, and that opposite substrate comprises a motherboard of a semiconductor tester, where the plurality of DSAs that make up the substrate group is integrally mounted and connected.

The thus configured, with a circuit for detecting substrate errors equipped device The present invention may be embodied in a semiconductor test apparatus of the type with removable DSAs, by using DSAs as the inventive substrates, a motherboard on which the DSAs are mounted as the located opposite Substrate and a DSA group of multiple DSAs as the substrate group the multiple substrates. With this configuration, in a semiconductor test apparatus that is characterized by independent change a DSA with socket fields for various semiconductor tests is applicable, an error detection circuit used in the present invention to easily and reliably a wrong combination of DSAs, failure or bad connection to detect the connection elements, causing the occurrence of a wrong Placement or poor fixation is prevented, so that a highly reliable Semiconductor test equipment is provided for testing semiconductor components.

Short description the drawing

1 Fig. 13 is an exploded perspective view of a semiconductor test apparatus having a substrate defect detection circuit according to an embodiment of the present invention;

The 2 FIG. 11 are views each showing a semiconductor test apparatus having a substrate defect detection circuit of an embodiment of the present invention, of which FIG 2 (a) is a front view showing DSAs removed from a motherboard and 2 B) is a top-down view of the DSAs in 2 (a) ;

3 Fig. 12 is a cross-sectional view conceptually showing the main parts of an ID setting board and a contact pin board of an embodiment of the present invention;

4 Fig. 12 is a block diagram conceptually showing ID setting boards and an ID matching circuit in a semiconductor test apparatus having a substrate defect detection circuit of an embodiment of the present invention;

5 Fig. 10 is a circuit diagram showing details of an ID matching circuit in a semiconductor test apparatus having a substrate defect detection circuit of an embodiment of the present invention;

6 Fig. 4 is an illustrative view conceptually showing a daisy-chain circuit in a semiconductor test apparatus having a substrate defect detection circuit of an embodiment of the present invention;

7 FIG. 10 is a block diagram conceptually showing a utility board in a semiconductor test apparatus having a substrate defect detection circuit of an embodiment of the present invention; and FIG

the 8th FIG. 11 are illustrative views each conceptually showing a semiconductor testing apparatus proposed by the inventors of the present application in Japanese Patent Application No. 2002-047186, wherein FIG 8 (a) is a front view showing DSAs taken from a motherboard and 8 (b) a top view from below of the DSAs in 8 (a) is.

Best mode to run the invention

Now, preferred embodiments of a device according to the present invention equipped with a circuit for detecting substrate defects will be described with reference to FIGS 1 to 7 to be discribed.

1 FIG. 13 is an exploded perspective view of a semiconductor test apparatus having a substrate defect detection circuit according to an embodiment of the present invention. FIG. The 2 FIG. 11 is views showing a semiconductor test apparatus having a substrate defect detection circuit of the present embodiment, of which FIG 2 (a) is a front view showing DSAs removed from a motherboard and 2 B) is a top-down view of the DSAs in 2 (a) ,

As shown in these figures, the apparatus according to the present invention provided with a substrate defect detection circuit is a semiconductor test apparatus that connects as a device connecting a plurality of terminal elements on one side of the substrate to a plurality of terminal elements on a facing substrate , DSAs 10 on which a variety of socket fields 11 arranged in rows so they are mounted on semiconductor components, and a motherboard 20 at the opposite end, with which the DSAs 10 are connected. In the present embodiment, the apparatus includes an error detection circuit for detecting a misplacement of the DSAs 10 and / or a wrong connection of connection elements of the DAS 10 and a motherboard 20 ,

[Semiconductor test equipment]

First, referring to the 1 and 2 a semiconductor test apparatus which is a device equipped with a circuit for detecting substrate errors of the present embodiment. As can be seen from these figures, a semiconductor test apparatus according to the present embodiment has almost the same construction as the semiconductor test apparatus in FIG 8th , and it's a test device where DSAs 10 with socket fields 11 for mounting semiconductor components to be tested (not shown) removable thereon on the motherboard 20 and testing different types of semiconductor components by changing only the DSAs 10 can be used.

As it is in 1 is shown, each of the DSAs (Device Specific Adapters) includes 10 a variety of socket fields 11 under which connection elements 14 are arranged (see 2 B) ). The multiple socket fields 11 and the corresponding connection elements 14 are integrally arranged on a substrate, and their manufacture, peeling, changing and the like are usually carried out on the basis of a DSA. Since the multiple socket arrays are used and handled per DSA, modular socket arrays are fabricated according to a DSA, for example semiconductor components with different package configuration or pin configuration, and a DSA corresponding to the semiconductor components can be plugged in or pulled out and changed to accommodate different types of semiconductor devices Semiconductor components can be tested.

In such a semiconductor test apparatus with detachable DSAs for simultaneously testing a large number of semiconductor components, multiple DSAs; For example, a set of 2 or 4 DSAs with jacks of the same configuration are mounted on a motherboard. In the present embodiment, as it is in 1 is shown, a set of DSAs comprises two DSAs (DSA-A 10a and DSA-B 10b ), and these two DSAs 10 are integral on the motherboard 20 mounted and connected. To be more specific, on each of the DSAs 10 According to the present embodiment, a plurality of socket arrays 11 on a self-service frame (socket box frame) 12 arranged, which is a base substrate of the frame type, in the center thereof corresponding to the respective socket fields 11 to be connected connection elements 14 are arranged.

Each of the socket fields 11 is a substrate comprising a device-equipped connector (socket) which has mounted thereon a semiconductor component to be tested and electrically connected thereto, each semiconductor being mounted on a socket array 11 is mounted. Then these multiple socket fields become 11 on a frame part of the SB frame 12 mounted and fixed on it.

The SB frame 12 is formed of a frame member made of metal or the like and a plurality of spaces (see 2 B) ). In this embodiment, as in 2 8 spaces are provided in a row, or 16 spaces in total. As it is in 2 B) is shown are the connection elements 14 that with the appropriate socket fields 11 in the corresponding spaces in the SB frame 12 plugged in. Here, at the DSAs 10 According to the present embodiment, the SB frame 12 2 rows of 8 spaces on it as in the 1 and 2 is shown, and 16 spaces in total, on which 32 socket fields 11 and accordingly 32 connection elements 14 are arranged in total, 2 socket fields 11 and accordingly 2 connection elements 14 per gap. The number of socket fields 11 and the connection elements 14 and the number of SB frames 12 however, are not limited to those in the present embodiment.

As mentioned above, the connection elements are 14 in that the connecting elements 14 in the SB frame 12 are housed, to the bottom of the corresponding socket fields 11 arranged, and the connection elements 14 are with the appropriate socket fields 11 on the SB frame 12 connected while the connection elements 14 on the same bottom side of the socket field 11 are fixed and thus all connection elements 14 simultaneously with the corresponding connection elements 21 on the motherboard 20 are connected (see 1 ). If any of the connection elements 14 the DSAs 10 and the connection elements 21 the motherboard 20 Accordingly, an incorrect connection of the connection elements occurs, which by the following daisy chain circuit 40 be recorded.

Each of the socket fields on the SB frame 12 are mounted, has the shape of a Socket box substrate with 4 notches at its corners, and of these notched parts, an exposed frame part of the SB frame 12 be seen. On the exposed part of the SB frame 12 are positioning holes 15 formed in the positioning pins 22 plugged in to the DSAs 10 at specified positions corresponding to the motherboard 20 to position. The positioning holes 15 (and the positioning pins 22 ) are formed in the present embodiment at 4 positions, 2 in the longitudinal direction and 2 in the transverse direction of the SB frame (see 2 ); however, any position of the positioning pins 22 and positioning holes 15 be provided as long as the DSAs 10 are positioned at the specified positions, and the number of positioning pins 22 and the positioning holes 15 is also not limited to those in the present embodiment.

Furthermore, as it is in 2 Shown are on areas that are not attached to the multiple terminal elements 14 on the surface of the SB frame arranged with connecting elements 12 connect, ID setting boards 13 for setting ID numbers of the DSAs 10 and for issuing ID signals indicative of the ID numbers. These ID setting boards 13 will be described in detail later.

The above-mentioned DSAs 10 include a set of 2 combined DSA-A 10a and DSA-B 10b on each of which the socket fields 11 are mounted, and these 2 DSAs 10 are integral on the motherboard 20 assembled. In other words, in the present embodiment, 2 DSAs 10 used as a set combined and socket fields 11 of the same configuration mounted thereon, for example, as "DSA-A and DSA-B", "DSA-C and DSA-D" and "DSA-E and DSA-F" ... according to the types of female panels 11 be designated. In this case, combinations of "DSA-A and DSA-C" and "DSA-B and DSA-D" result in different types of jack fields 11 on the motherboard 20 are mounted, which as an error combination of DSAs 10 to be viewed as.

Then the match or mismatch of the combination of the DSAs 10 through the ID matching circuit 30 via the following ID setting boards 13 detected.

The motherboard 20 is how it is in 1 is shown, a substrate provided on the main body or the semiconductor test apparatus. As mentioned above, the motherboard 20 a variety of connection elements 21 according to the DSAs 10 with modular socket fields 11 on (see 1 ). The motherboard 20 is with the DSAs 10 via the terminals, and thereby a given electrical signal required for the test is transferred to the DSAs via the motherboard 20 so input or output that a semiconductor component on each of the socket fields 11 can be tested.

Then, in the present invention, at portions other than the plurality of multiple terminal members 21 on the motherboard interfere with contact pins 23 arranged to be in contact with the ID setting boards 13 the DSAs 10 are located. These contact pin boards 23 as well as the ID setting boards 13 the DSAs 10 will be described in detail later.

Here is the motherboard 20 In the present embodiment, a motherboard mounted on the main body of the semiconductor test apparatus, an SPCF and a metal plate, a performance board, utility board, and the like. As described above, in the present embodiment, an error detection circuit is on a utility board 20a in the motherboard 20 ,

Accordingly, in the present embodiment, "motherboard" means an opposed substrate according to the invention, with which the modular DSAs 10 are detachably connected. A structure and functions of the semiconductor test apparatus in the present embodiment besides the above-mentioned DSAs 10 and the motherboard 20 are those of an already available semiconductor tester, and its detailed description is omitted.

[ID adjustment board]

Next, referring to the 3 and 4 an ID setting board 1 described according to the present embodiment.

3 Fig. 12 is a cross-sectional view conceptually showing the main parts of the ID setting board 13 and a contact pin board 23 according to the present embodiment shows. 4 Fig. 10 is a block diagram conceptually showing a relationship between the ID setting board 13 and an ID matching circuit 30 according to the present embodiment shows.

Each of the ID setting boards 13 shown in these figures is a substrate for setting an ID number suitable for a combination of DSAs 10 (DSA-A and DSA-B and DSA-C and DSA-D ...), and outputting an ID signal indicative of the ID number, and is on the surface for arranging the terminal elements on each the DSAs 10 intended.

The ID setting board 13 is located at an area that does not match the multiple terminal elements 14 on the surface for arranging the connection elements of the SB frame 12 interferes. In the present embodiment, as it is in 2 shown are on each of the DSAs 10 ( 10a . 10b ) 8 ID setting boards arranged.

Also, on the motherboard 20 opposite the ID setting boards 13 Pin boards 23 provided as boards for input of ID signals. As it is in 1 are shown are the contact pin boards 23 provided in such a way that 8 pins for each of the 2 DSAs 10a and 10b or 16 pinboards are arranged in total at positions corresponding to the ID setting boards 13 not with the multiple connection elements 21 on the motherboard, in the same way as the ID setting boards 13 , Accordingly, if the DSAs 10 on the motherboard 20 be mounted, be contact surfaces 13a to output the ID signal of the ID setting board 13 and corresponding contact pins 23 contacted with each other so that ID signals are automatically sent to the ID matching circuit 30 output, as when mounting the DSAs 10 ,

Each of the ID setting boards 13 includes, as it is in 3 is shown having a set of pads on a substrate surface, disposed and fixed on a surface of a DSA 10 , opposite the motherboard 20 by fixing means such as bolts or the like. The set of contact surfaces 13a to output the ID signal is each with a set of 2 contact pads 13c to set the ID number on the back of the substrate (on the side of the DSA 10 ) via through holes 13b connected.

Each of the contact surfaces 13c to set the ID number can be with a GND pad 13e via a bridging line 13d get connected. The GND contact surface 13e is via a (not shown) line pattern with a bolt or the like for fixing the ID setting board 13 connected. The contact surface 13c to set the ID number can be set to GND or OPEN, depending on whether the bypass line 13d with the GND contact surface 13e connected or not.

Especially if the contact surface 13c to set the ID number to GND (with the GND pad 13e connected), a signal output from the contact surface 13a for outputting the ID signal to an ID matching circuit described below 30 LOW (0), since the input side is grounded. On the other hand, if the contact surface 13c to set the ID number to OPEN (not with the GND pad 13e connected), a signal output from the contact surface 13a for outputting the ID signal to an ID matching circuit described below 30 HIGH (1), by applying voltage Vcc to the ID matching circuit 30 (please refer 5 ).

In this way, in each of the ID setting boards of the present embodiment, a signal output from the pad 13a to output the ID signal that matches the contact surface 13c to set the ID number, depending on the presence or absence of a connection with the bypass line 13d switched to LOW (0) / HIGH (1). Then, by setting any signal, LOW (0) / HIGH (1) to the ID setting board 13 an ID signal indicative of a desired ID number into the ID matching circuit 30 be entered (see 4 ).

Here, in the present embodiment, 8 ID setting boards 13 on each of the DSAs 10 ( 10a . 10b ), and each of the ID setting boards 13 includes 2 contact surfaces 13a to output the ID signal as shown in 2 is shown. This will create an ID number that passes through the ID setting board 13 to set a 16-bit number to match the DSAs 10 ( 10a . 10b ) must be assigned. In the present embodiment, in such a 16-bit signal, the first 14 bits are assigned to an ID signal indicative of an ID number.

For example will be an ID number for a Combination of "DSA-A and DSA-B "characterizing is priced as "00000000000001" and one ID number for a combination of "DSA-C and DSA-D "characterizing is set as "00000000000010", i. Any 14-bit ID number can be set.

As it is in 4 is shown, a 14-bit ID number from each of the DSAs 10a and 10b to be input to an ID matching circuit 30 via a contact pin board 23 on the motherboard 20 ,

The number of bits in an ID signal for a TD number of each of the DSAs 10 is not limited to 14 in the present embodiment; however, it can be arbitrary according to the type of DSAs 10 be set. In addition, the number of ID setting boards 13 and the output pads are changed on the basis of the number of necessary bits. For example, in the case of a semiconductor test apparatus, 1,000 types of DSAs 10 can use 1,000 ID numbers, and therefore a 10-bit signal can be used to map 1,024 ID numbers. If the Number of outputs of an ID setting board is "2" as with the ID setting board 13 of the present embodiment, accordingly, in this case, only 5 ID setting boards in each of the DSAs 10 needed. On the other hand, in the case of a semiconductor tester, the 10,000 types of DSAs 10 can use 10,000 ID numbers, and therefore a 14-bit signal can be used to assign 16,384 ID numbers. This way, with regard to an ID setting board 13 of the present embodiment, the number of ID setting boards, the number of output bits, and the number of bits among tangible bits to be assigned to an ID signal are set flexibly.

Here, it is preferable that setting an ID number of ID setting boards 13 before assembling DSAs 10 and after setting a type of on a DSA 10 to be mounted socket fields 11 becomes a set of 2 ID setting boards 13 who are assigned the same ID number at designated locations on the DSA 10 arranged. Furthermore, an ID number that was once set may not be changed. Because a careless change of ID numbers incorrectly fixing the DSA 10 or the like, it is preferable that an ID setting board 13 removable on a DSA 10 fixed using a bolt.

[ID matching circuit]

Then an ID matching circuit 30 according to the present embodiment with reference to 5 described. 5 is a circuit diagram showing the details of an ID matching circuit 30 according to the present embodiment shows.

As it is in 5 is shown is the ID matching circuit 30 According to the present embodiment, a circuit for detecting a match or disagreement of a set of DSAs 10 ( 10a and 10b ) or comparing means for comparing ID signals. In the present embodiment, 14-bit signals are output from the ID setting boards 13 the corresponding DSAs 10a and 10b are to be input to the ID matching circuit 30 entered. To be more specific, the ID matching circuit 30 includes, as it is in 5 14, XOR circuits, 7 NOR circuits and an AND circuit in which a 14-bit signal is input. 14 bits of one from an ID setting board 13 one of each of the DSAs 10a to be inputted ID signal with corresponding 14 bits of one from an ID setting board 13 one of each of the DSAs 10b compared to input ID signal. When all these 14 bits have been aligned, a signal of HIGH (1) is output, while in the other cases a signal of LOW (0) is output, allowing a coincidence of a combination of on the motherboard 20 assembled DSAs 10 capture. When different types of DSAs 10 can be combined, an error signal (signal LOW (0)) can be output, thereby making it possible to perform processing according to the occurrence of an error. In the present embodiment, a locking mechanism for locking the DSAs 10 on the motherboard 20 controlled in such a way that the locking mechanism does not work and ID number mismatch is displayed, which will be described below.

Furthermore, in the present embodiment, the ID matching circuit 30 on a utility board 20a on the motherboard 20 arranged (see the 4 and 7 ), and if a mismatch of ID numbers is detected, the utility board handles 20a the mismatch as an "ID number error" as described below.

As comparison means for comparing ID signals, the ID matching circuit 10 assume a different configuration than the configuration shown in the present embodiment. In other words, the comparison means may employ any circuit, apparatus or the like as long as it is possible to detect wrong combination of different types of DSAs by comparing ID signals.

[Daisy chain circuit]

With reference to 6 will be a description of the daisy chain circuit 40 made according to a present embodiment. 6 is an illustrative view, conceptually a daisy chain circuit 40 according to the present embodiment shows.

As it is in 6 shown is the daisy chain circuit 40 a circuit that receives a signal from a connector 21 on the motherboard 20 (Connecting element 21 in the left end in 6 ) and a signal via a corresponding connection element 14 on the DSA 10 (Connecting element 14 in the left end in 6 ) logically to all connection elements 21 and 14 on the motherboard 20 or on the DSA 10 transmits to detect the presence or absence of an output signal. To be more specific, the daisy chain circuit includes 40 Transmission lines by assigning appropriate pins of the connection elements 21 the motherboard 20 and the connection elements 14 of the DSA 10 be formed into a cascade connection, so that all An be connected in series. In the present embodiment, as in 6 Shown are each 2 pins of the connection element 21 the motherboard 20 and the connection elements 14 the DSAs 10 short-circuited to connect all connection elements in series.

First, two pins of each connection element 21 on the side of the motherboard 20 (Pins in 6 ) associated with a cascade circuit, with one for input and the other for output. Between adjacent connection elements 21 becomes a daisy-chain output pin of one terminal 21 with the daisy-chain input pin of the other connector 21 via a short circuit line 21a connected. Then be on the side of the DSAs 10 2 pins of each connection element 14 (Socket pins in 6 ) associated with a cascade circuit, with one at the input and the other at the output. For a connection element 14 is an input and an output via a short circuit line 14a connected.

Daisy chain pins in the connection elements 21 and 14 may insert pins which are not used in connection elements or the like, and pins reserved for concatenation may be provided.

According to such a daisy chain circuit 40 be the input and output of the daisy chain circuit 40 only made continuously if all the connectors on the motherboard 20 and DSA 10 normally connected. If there is a bad connection to any connector, the daisy-chain circuit can 40 not be carried out continuously. Accordingly, once voltage is applied to an input of the daisy-chain circuit 40 is created, in the absence of a bad connection of all connection elements on the same a normal signal (signal HIGH (1)) output when the connection between the connection elements is established. Then, the presence or absence of this output signal is monitored for normal connection or bad connection of the corresponding terminal elements on the motherboard 20 and the DSA 10 to capture what it allows, errors in the connection of connecting elements between the motherboard 20 and the DSA 10 to capture at the same time when the DSA 10 on the motherboard 20 is mounted to the connecting elements of both the motherboard 20 and the DSA 10 connect to.

An output signal from this daisy chain circuit 40 gets into the utility board 20a entered (see 7 ) which determines the presence or absence of the occurrence of an error, as well as match or mismatch of ID signals. In the case of the error, the processing is performed as a "daisy-chain error".

In the daisy chain circuit 40 of the present embodiment are 2 connection elements of the motherboard 20 and the DSA 10 assigned to the cascade circuit. The number of pens, however, is limited to 2. In other words, the daisy chain circuit 40 can use any number of pins used and any connection method as long as a transmission line is formed to all the motherboard connectors 20 and the DSA 10 logically in series. Accordingly, when the motherboard 2 and the DSA 10 are provided with coaxial connectors, SIG leads and GND leads of the coaxial leads are shorted to assign the SIG leads to the daisy chain inputs and the GND leads to the daisy chain outputs, thereby reducing the daisy chain circuit 40 is built.

Furthermore, in the present embodiment, the input and output of the daisy-chain circuit 40 on the side of the motherboard 20 performed; however, the input and output can be daisy-chained 40 on the side of the DSA.

[Utility Board]

Next is a description about a utility board 20a according to the present embodiment with reference to 7 which is a block diagram conceptually a utility board 20a in a semiconductor test apparatus according to the present embodiment.

The utility board 20a In the present embodiment, a substrate is on the side of the motherboard 20 is provided, as it is in 7 the ID matching circuit is shown 30 into which an output signal from the daisy-chain circuit 40 and an ID signal from the ID setting board 13 is entered. The utility board 20a includes an AND circuit 33 for receiving output signals from the daisy chain circuit 40 and the ID matching circuit 30 ; an entrance section 34 for the daisy chain error signal for receiving an output signal from the daisy chain circuit 40 , and an entrance section 35 for the ID number error signal for receiving an output signal from the ID matching circuit 30 , which also in 7 is shown.

The AND circuit 33 outputs a signal that is indicative of "Test OK" (signal HIGH (1)), only off when signals coming out of the Dai sy chain circuit 40 and the ID matching circuit 30 are output, HIGH (1) or no error signals. The signal output from the AND circuit 33 It is used to detect no ID mismatch of the DSA 10 and no bad connection of any connector of the DSA 10 and the motherboard 20 which executes a "test OK" control. In the present embodiment, when a signal "Test OK" comes out of the AND circuit 33 is issued, a locking mechanism for locking the DSAs 10 on the side of the motherboard 20 controlled to lock the DSAs 10 to control (LOCK).

Meanwhile, the entrance part 34 for the daisy-chain error signal or the input part 35 for the ID number error signal, a signal when an input signal is LOW (0) or an error signal. This makes it possible the presence of a bad connection in any of the DSAs 10 and the motherboard 20 and mismatch of DSA ID numbers 10 which are treated as a "daisy-chain error" or as an "ID number error". In the present embodiment, an "error" signal is used to lock the locking mechanism to lock the DSA 10 on the side of the motherboard 20 to control so that it does not work (FREE), and to allow an LED or the like to light up in accordance with the "daisy chain error" and the "ID number error" so as to cause the occurrence of a malfunction on the outside of the device To display error.

[Operations to Detection of errors]

When next becomes a description of operations for detecting errors in the thus constructed semiconductor test apparatus having a detection circuit substrate defects according to the present invention embodiment made.

First, a set of 2 DSAs 10 manufactured and at specified positions of the motherboard 20 mounted so that connection elements 21 the motherboard 20 and corresponding connection elements 14 from both DSAs 10 connected to each other. If the DSAs 10 on the motherboard 20 are mounted, a contact surface 13a to output the ID signal of each ID setting board 13 of each DSA 10 in contact with a corresponding contact pin 23a each contact pin board 23 the motherboard 20 and then put an ID signal for the ID number of each of the DSAs 10 is indicative.

Output ID signals are sent via the contact pin 23a into the ID matching circuit 30 of the utility board 20a and then become ID signals of the DSAs 10 compared to detect a match or mismatch of the ID numbers. This detection result becomes the AND circuit 33 entered and the input part 35 for the ID number error signal of the utility board 20a entered.

Furthermore, if the DSAs 10 on the motherboard 20 are mounted and connecting elements of the DSAs 10 and the motherboard 20 connected to the daisy-chain circuit 40 to make it through, a daisy-chain signal is output to the AND circuit 33 and the entrance part 35 for the ID number error signal of the utility board 20a to be entered.

The AND circuit 33 of the utility board 20a outputs a signal indicative of "Test OK" (signal HIGH (1)) only when a signal output from each circuit is HIGH (1) or not an error signal.

This signal does not mean ID mismatch of the one set of 2 DSAs 10 on the motherboard 20 mounted, and no bad connection of any connection element of the DSA 10 and the motherboard 20 , and as a "test OK" is a locking mechanism for locking the DSAs 10 on the side of the motherboard 20 so controlled that the DSAs 10 Locked (LOCK), thereby making it possible to use the semiconductor components using the DSAs 10 and the motherboard 20 to test.

Meanwhile, when an input signal is LOW (0) or an error signal, the input part determines 34 for the daisy-chain error signal or the input part 35 for the ID number error signal, the presence of a bad connection in any of the DSA 10 or the motherboard 20 or a mismatch of DSA ID numbers 10 and output signals indicative of "errors". In this way, the processing for "daisy chain error" or "ID number error" is performed.

In other words, the locking mechanism for locking the DSA 10 on the side of the motherboard 20 is controlled so as not to function (FREE), and an LED or the like is allowed to light up according to "daisy-chain error" or "ID number error" to indicate on the outside of the device the occurrence of an error. Accordingly, the semiconductor test apparatus is deemed unusable in this situation and therefore prevented from being executed while DSAs 10 in wrong combination on the motherboard 20 are mounted or while a part of the connection elements are poorly connected.

As described above, includes Device according to the invention equipped with a circuit for detecting substrate errors, ID setting boards 13 for a combination of DSAs 10 characterizing, and an ID matching circuit 30 for detecting a coincidence of ID signals output from ID setting boards, and only when assigning fixed ID numbers and determining match or disagreement of the ID numbers, it becomes the device equipped with a circuit for detecting substrate errors allows to determine if the particular combination in the two DSAs 10 is constructed or not.

That's why it's possible to have a combination of DSAs 10 only by assigning special ID numbers to the DSAs 10 without changing the configuration or the profile of the DSAs 10 and thereby the occurrence of damage, failure or the like of the socket field and the equipped device due to the misplacement of the DSAs 10 to prevent.

Since the judgment of a combination of the DSAs by input of ID signals from the DSAs 10 In addition, in the present embodiment, it may be concurrently performed when the DSAs 10 on the motherboard 20 which ensures a rapid determination, thereby allowing the semiconductor test apparatus to efficiently perform original test operations and processing.

Because the combination of DSAs 10 by assigning ID numbers to the DSAs 10 Moreover, if the DSAs are increased or decreased in type or number, moreover, the ID numbers need only be added or decreased, thereby realizing an error detection circuit excellent in versatility and scalability.

Because the daisy chain circuit 40 for transmitting a signal over all the connection elements of the DSAs 10 and the motherboard 20 is provided, in the present embodiment, a bad connection, a connection error, or the like between any one of the terminal members can be directly detected.

Because the daisy chain circuit 40 Besides, for transmitting a signal between the terminal elements to detect a bad connection or the like, a bad connection or a connection error can be promptly detected when the terminal elements of the DSAs 10 and the motherboard 20 get connected.

Although in the case of a semiconductor tester, the DSAs 10 and a motherboard 20 With such a configuration, with a large number of terminal elements, it is possible to easily and reliably find a bad connection or failure, thereby realizing a highly reliable test apparatus that avoids poor operation or a reduction in workability due to a bad connection can. In particular, in the present embodiment, the provision enables both the ID matching circuit 30 and the daisy chain circuit 40 that combination error of the DSAs 10 as well as a bad connection between connection elements of the DSAs 10 and the motherboard 20 to grasp with reliability.

Therefore, in a semiconductor test apparatus comprising a plurality of combined DSAs 10 using each of the DSAs 10 having a plurality of terminal elements, a combination error of the DSAs 10 can be detected with reliability by assigning ID numbers, and a bad connection of the plurality of terminals can be easily detected, thereby providing a highly reliable semiconductor test apparatus excellent in versatility and scalability.

The Device according to the invention, with equipped with a circuit for detecting substrate errors, is described with reference to the preferred embodiment Service. However, the present invention is not limited to the above described embodiment limited. It goes without saying that any modification to the present Invention applicable within the scope of the present invention is.

For example For example, in the above-mentioned embodiment, the ID setting board will only be set and issuing ID numbers of a set of DSAs. she however, can be used as a number setting means for setting and outputting Any number used in other applications can be used. In other words, in the one described above the ID setting board sets a 2-bit signal and outputs it, which is used as an ID signal indicative of an ID number is. However, if the ID setting board has a structure, the is suitable for setting and outputting a 6-bit signal two bits in the signal for an ID signal of the present invention is used, and the others 4 bits can be assigned to another signal.

This is used at a user end as number means for input and output any serial numbers, user numbers, reference numbers or used the same.

Moreover, in the semiconductor test apparatus as described in the present embodiment, both the ID matching circuit 30 as well as the daisy chain circuit 40 intended to make combination errors of the DSAs 10 as well as bad connection between connection elements of the DSAs 10 and the motherboard 20 capture. However, it is also possible to provide only one of them.

The Substrate group, their combination by the ID matching circuit is judged in the embodiment described above from a set of two DSAs. However, one set of two DSAs is not intended to limit the present invention. It It goes without saying that a set of DSAs from at least two DSAs, for example 3 DSAs or 4 DSAs. Similarly, consist of the connection elements, of which a bad connection to be detected by the daisy-chain circuit at the top described embodiment from a variety of connection elements. However, it can only be one Connection element between substrates to be connected arranged be.

Furthermore is in the embodiment described above by illustrating the Plug in and pull out the socket panel and motherboard in the semiconductor test device a inventive circuit for detecting substrate defects has been described. The circuit for However, detection of substrate defects of the present invention is not limited to the semiconductor test device, the DSAs and a motherboard. The circuit for detection Substrate defects of the present invention may be applied to any substrate or device be applicable by combining at least 2 substrates, those with one opposite substrate to be connected, or by connecting a substrate having one or more connection elements with one opposite Substrate operates with corresponding connection elements.

industrial applicability

As It has been described above is an apparatus according to the invention, which is provided with a circuit equipped to detect substrate defects, a device in which a variety of substrates in a set of substrates with one opposite Substrate to be combined, combined with the Device equipped with a circuit for detecting substrate errors includes, such as a matching circuit for detecting a match or mismatch a combination of the substrates in the set by receiving ID signals for The combination of substrates is so easy and so reliable to capture a combination of different types of substrates, whereby the occurrence of a damage, an error or the like of substrates, receptacle panels and equipped components prevented is, and with a circuit for detecting substrate errors equipped device for a Semiconductor test equipment in which a plurality of DSAs having a plurality combined from socket fields to used at the same time to become.

In addition is an inventive device that with a circuit for detecting substrate errors is equipped, a substrate with one or more corresponding connection elements, those with one opposite located substrate with one or more connection elements connected to a circuit for detecting substrate errors equipped device a daisy chain circuit to transfer a signal over all connected connection elements includes an output result to capture the signal so easily and reliably a bad connection or to detect a failure of corresponding connection elements, whereby the occurrence of a disorder, a decrease in processability or the like due the poor connection of the connecting elements is prevented and equipped with a circuit for detecting substrate errors Device for a semiconductor test device with a Motherboard and female panels is suitable, of which a variety be connected by connecting elements at the same time.

Summary

Incorrect placement of DSAs and poor connection of terminal elements in a semiconductor tester are detected and prevented with reliability. The semiconductor test device, which has a set of DSAs 10a and 10b with socket fields 11 mounted on it and a motherboard 20 having connecting elements, which with the connecting elements 14 of the socket field 11 of the set of DSAs 10a and 10b To connect to includes: ID setting boards, which are based on the set of DSAs 10a and 10b are provided and output ID signals indicative of the ID numbers; a matching circuit for receiving the ID signals output from the ID setting board to detect coincidence or disagreement of the ID signals, and a daisy-chain circuit for receiving a signal from a terminal 21 on the motherboard 20 and transmitting the signal via corresponding connection elements 14 on DSAs, which are sequential with all connection elements 21 and 14 connected to detect the presence or absence of an output signal.

Claims (7)

With a circuit for detecting substrate errors equipped device, the at least one substrate group of a plurality of combined Substrates and one opposite having substrate to connect to the substrate group is with a circuit for detecting substrate errors equipped device includes: ID setting boards on the corresponding substrates the substrate group are provided, for setting corresponding, fixed ID numbers to be assigned to the substrate group, and outputting ID signals corresponding to the corresponding ID numbers are characteristic; ID signal input boards on the located opposite Substrate corresponding to the substrate group are provided for receiving of ID signals, which are output from the ID setting boards, and comparison means for receiving ID signals output from the ID signal input boards, and comparing the ID signals of the respective substrates, wherein the equipped with a circuit for detecting substrate errors Device one Combination error of the substrate detected in the substrate group. With a circuit for detecting substrate errors equipped device, a substrate with connection elements and a substrate opposite having connecting elements, which with the connecting elements of the substrate are to be connected,  being that with a circuit Device equipped to detect substrate defects comprises: a Daisy chain circuit for receiving a signal from a terminal the substrates or the opposite located substrate and transferring the signal over the corresponding connection elements logically to all connection elements, to detect the presence or absence of an output signal, in which that with a circuit for detecting substrate errors equipped device a connection error from all corresponding connection elements the substrates or the opposite detected substrate detected. With a circuit for detecting substrate errors equipped device, the at least one substrate group of a plurality of combined Substrates with connection elements and an opposite substrate with Having connecting elements, which with the corresponding connection elements the substrates of the substrate group are to be joined, the equipped with a circuit for detecting substrate errors Device includes: ID Einstellplatinen, provided on the respective substrates of the substrate group are, for setting corresponding, fixed ID numbers, the the substrate group, and outputting ID signals, the for the ID signals are indicative; ID-signal input circuit boards, those on the opposite Substrate corresponding to the substrate group are provided for receiving of ID signals, which are output from the ID setting boards;  comparison means for receiving ID signals output from the ID signal input boards, and comparing the ID signals of the respective substrates, and a Daisy chain circuit for receiving a signal from a terminal the substrates or the opposite located substrate and transferring the signal over the corresponding connection elements logically to all connection elements, to detect the presence or absence of an output signal, in which that with a circuit for detecting substrate errors equipped device a combination error of the substrates in the substrate group and a connection error from all corresponding connection elements the substrates or the opposite Substrate detected. With a circuit for detecting substrate errors equipped device according to one of the claims 1 to 3, wherein the ID setting boards have a plurality of ID setting boards are located on each substrate and an ID number adjust and output to the appropriate substrates. With a circuit for detecting substrate errors equipped device according to claim 2 or 3, wherein the daisy-chain circuit through the connection elements of the substrates and the opposite substrate each of which shorted one or more pins in the corresponding substrates or the opposite substrate, that is to be connected. With a circuit for detecting substrate errors equipped device according to one of the claims 1 to 5, wherein the substrates include DSAs containing one or more socket fields have mounted on which to be tested semiconductor components and are connected, and the opposite substrate one Motherboard of a semiconductor test device, on which the DSAs are mounted and connected. A device equipped with a circuit for detecting substrate defects according to any one of claims 1, 3 or 4, wherein the substrates comprise DSAs having one or more female fields on which semiconductor components to be tested are mounted and connected, the substrate groups comprise a combination of the substrates of the DSAs, and the opposing substrate comprises a motherboard of a semiconductor test device on which the plurality of DSAs, which build the substrate group, is integrally mounted and connected.