TWI324817B - Multiple chip package - Google Patents

Multiple chip package Download PDF

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Publication number
TWI324817B
TWI324817B TW095148003A TW95148003A TWI324817B TW I324817 B TWI324817 B TW I324817B TW 095148003 A TW095148003 A TW 095148003A TW 95148003 A TW95148003 A TW 95148003A TW I324817 B TWI324817 B TW I324817B
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TW
Taiwan
Prior art keywords
wafer
chip package
conductive layer
carrier
electrically connected
Prior art date
Application number
TW095148003A
Other languages
English (en)
Other versions
TW200828532A (en
Inventor
Sheng Hsiung Chen
Jen Te Tseng
Original Assignee
Advanced Semiconductor Eng
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Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW095148003A priority Critical patent/TWI324817B/zh
Priority to US11/898,950 priority patent/US7667303B2/en
Publication of TW200828532A publication Critical patent/TW200828532A/zh
Application granted granted Critical
Publication of TWI324817B publication Critical patent/TWI324817B/zh

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Description

1324817
CONFIDENTIAL 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種多晶片封裝結構，且特別β有 於一種具有導電層作為銲線轉運站的多晶片封裝結構關 【先前技術】 對於高密度，高效能以及成本效益的需求加迷了夕曰 片封裝（Multiple Chips Package, MCP)的研發和庙夕日曰 X 屬用。桓 組裝配整合了系統與多種晶片，並可選擇—種或更多、、 動元件。然而’隨之而來的問題是，更多的晶片與被 件整合在同一個封裝件内’導致打線變得越來越困難元 舉例來說’在方形扁平式封裝結構(Quad Figt Package, QFP)的架構下，僅僅是承載二個晶片就 & 成打線上的困難。第1圖是傳統方形扁平式封裝結 的俯視圖及側視圖。請參照第1圖，導線架（丨ead P) 上的晶粒承載座（dje pad)1〇承載了下晶粒2〇與上b曰勒W 30。下晶粒20透過第一銲線L1電性連接於晶粒承 10。上晶粒30透過第二銲線L2電性連接於第—晶片^ 以及第三銲線L3連接至晶粒承載座1〇。除此之外曰曰粒 承載座10、下晶粒20以及上晶粒3〇還必須透過第四3曰辑& 線L4、第五銲線L5以及第六銲線L6分別與弓丨腳4〇電性 連接。 然而’第三銲線極易與相鄰的其他銲線群交錯X而產 生短路問題。由於佈線密集又違反銲線規則，要打第三銲 1324817
CONFIDENTIAL 線時必須特別小心才能避免造成相鄰銲線受損或塌陷。就 . 算打線時沒有發生受損或塌陷的問題，在後續的封膠過程 中液態膠體在包覆封裝件的過程中也很容易產生沖線 (wire sweep)的問題，造成短路。此外，若是晶粒位置偏 移，第三銲線則必然會與相鄰的其他銲線群接觸而發生短 路的問題。在在都影響封裝件的良率甚鉅。因此，如何找 • 出一個有效的方法解決多個的晶片與被動元件整合在同 一個封裝件内的打線問題，乃是目前業界整合多晶片封裝 φ 的關鍵因素之一。 【發明内容】 有鑑於此，本發明的目的就是在提供一種多晶片封裝 件，將晶片與晶片之間、晶片與承載器之間雜複的銲線可 以經過彙整而統一藉由導電層這個轉運站轉接出去，可以 避免銲線交錯、沖線而短路的問題。 根據本發明的目的，提出一種多晶片封裝件，包括承 • 載器、第一晶片、第二晶片以及第一導電層。第一晶片係 設置於承載器之上，並透過至少一第一銲線電性連接於承 載器。第二晶片係設置於第一晶片上，並透過至少一第二 銲線電性連接於第一晶片。第一導電層係設置於第二晶片 之上，並透過至少一第三銲線電性連結第一晶片或第二晶 片。其中，至少一第四銲線係電性連接第一導電層與承載 器。 根據本發明的目的，再提出一種多晶片封裝件包括承 1324817
' CONFIDENTIAL / 載器、第一晶片、第二晶片、第一導電層以及至少一第一 . 銲線。承載器其具有一上表面，上表面具有接地區。第一 晶片，係設置於承載器之上。第二晶片係設置於第一晶片 上。第一導電層，係設置於第二晶片之上。至少一第一銲 線，電性連結第一導電層及承載器。 為讓本發明之上述目的、特徵、和優點能更明顯易 • 懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說 明如下： 【實施方式】 本發明之主要目的在於將晶片上的接點匯聚至導電 層，再將其轉而連接至承載器上的標的區域(例如是接地區 或電源區）。本發明之多晶片封裝件包括承載器、第一晶 片、第二晶片以及第一導電層。第一晶片係設置於承載器 之上，並透過至少一第一銲線電性連接於承載器。第二晶 片係設置於第一晶片上，並透過至少一第二銲線電性連接 • 於第一晶片。第一導電層係設置於第二晶片之上，並透過 至少一第三銲線電性連結第一晶片或第二晶片。其中，至 少一第四銲線係電性連接第一導電層與承載器。 需注意的是，這樣的作法可以有多種應用的方式，也 可以應用在不同的封裝結構中，以下係舉幾組較佳實施例 並配合圖示做詳細說明。然熟習此技藝者當可明瞭，此些 實施例僅為本發明之發明精神下的幾種實施方式，並不會 限縮本發明之欲保護範圍。
CONFIDENTIAL 圖式簡單說明】 CONFIDENTIAL 第1圖 側視圖 疋傳統方形扁平式封裝結構(QFP)的俯視圖及 第2圖繪示依照本發明之第一實施例之多晶片封裝 件的俯視圖與侧視圖^ ^ 第3圖繪示依照本發明之第二實施例之多晶片封妒 件的俯視圖與側視圖。 、 【主要元件符號說明】 10 : 晶粒承載座 20 ： 下晶粒 30 ： 上晶粒 40 : 引腳 100 多晶片封袭件 110 承載器 120 第一晶片 130 第-—晶片 140 第一導電層 142 絕緣層 148 導電塊 150 引腳 200 多晶片封裝件 210 承載器 212 .接地區 13 1324817
CONFIDENTIAL 212a :接地層 214 : 電源區 216 ： 錫球 220 ： 第一晶片 230 ： 第二晶片 240 : 第一導電層 242 ： 第一絕緣層 250 : 第二導電層 252 ： 第二絕緣層 L7 L1 :第一銲線 L2 :第二銲線 L3 :第三銲線 L4 :第四銲線 L5 :第五銲線 L6 :第六銲線 第七銲線

Claims (1)

1324817 广修正 厂日補充 .. 你//月 十、申請專利範圍： — 1. 一種多晶片封裝件，包括： 一承載器，具有一區域； 一第一晶片，係設置於該承載器之上，並透過至少一 第一銲線電性連接於該承載器，該第一晶片具有至少二電 性接觸點； 一第二晶片，係設置於該第一晶片上，並透過至少一 第二銲線電性連接於該第一晶片，該第二晶片具有至少二 電性接觸點；以及 一第一導電層，係設置於該第二晶片之上，並透過至 少二第三銲線電性連結該第一晶片或該第二晶片其中任 意二電性接觸點； 其中，至少一第四銲線係電性連接該第一導電層與該 承載器之該區域，藉此將該第'一晶片或該第二晶片之該·一 電性接觸點與該承載器之該區域得以電性導通。 2. 如申請專利範圍第1項所述之多晶片封裝件，其 中該區域係一接地區。 3. 如申請專利範圍第1項所述之多晶片封裝件，其 中該多晶片封裝件更包括第一絕緣層，該第一絕緣層置於 該第一導電層與該第二晶片之間。 4. 如申請專利範圍第1項所述之多晶片封裝件，其 中該多晶片封裝件更包括複數個導電塊，係形成於該第一 導電層上，用以電性連接該第三銲線以及該第四銲線。 5. 如申請專利範圍第1項所述之多晶片封裝件，其 15 中該第一導電層係一金屬片。 6.如申請專利範圍第1項所述之多晶片封裂件，盆 中該第一導電層係一金屬薄膜。 /、 7_如申請專利範圍第1項所述之多晶片封裝 盆 中該第一導電層係包含鋁。 、，八 8.如申請專利範圍第1項所述之多晶片封努 中該多晶片封裝件更包括： 農件’其 一虛晶片，係設置於該第二晶片上，該虛晶片包括一 及該第一導電層’該第一導電層係形成於該矽主 :· Μ請專利範圍第2項所述之多晶片封裝件，盆 第四銲線係連接該第一導電層以及該承载器之該接 括：10.如申請專利範圍第2項所述之多晶片封裝件更包 一第二絕緣層，係設置於該第一導電層表面； 一第二導電層，係設置於該第二絕緣層之上 >、-第五鋅線電性連接於該承載器之該接地區。 其中:含圍第10項所述之多晶片封裝件， -晶片。〃第六鮮線電性連接該第二導電層及該第 其中Γ含至如範圍第10項所述之多晶片封料^ 二晶片。〆線電性連接該第二導電層及該第
月於，卜 私飞々Λ ! J ”ν_ / Ά 中^=申請專利範圍第1項所述之多晶片封裝件：其 係一基板’該基板内包含一接地層，並連接至 3上表面之該接地區。 中申請專利範㈣1韻述之多W封裝件，其 T該承载|g係一導線架。 15· 一種多晶片封裝件，包括： 二承载器’其具有一上表面，該上表面具有一接地區，· 厂第—晶片，係設置於該承载器之上，該第一晶片具 有至少二電性接觸點； 厂第二晶片，係設置於該第一晶片上，該第二晶片具 有至乂二電性接觸點；以及 一晶片之上’並透過至 或該第二晶片之該二 一第一導電層，係設置於該第 少二第一銲線電性連結該第一晶片 電性接觸點； 至少一第二銲線，電性連結該第一導電層及該接地 :’藉此將該第—晶片或該第二晶片之該二電性接觸點接 地。 1 =16·如申請專利範圍第15項所述之多晶片封裝件， /、中該承载器係一基板，該基板内包含一接地層，並 至該上表面之接地區。 17. 如申請專利範圍第15項所述之多晶片封裝件， 其中該承載器係一導線架。 18. 如申請專利範圍第15項所述之多晶片封裝件， 其中該多晶片封裝件更包括第一絕緣層，該第一絕緣層置 17 17 17
(^4¾¾ 於該第一導電層與該第二晶片之間。 ’ 盆中請專職㈣15項所述之多晶片封裳件， 一導；：：片封裝：更包括複數個導電塊，係形成於該第 導，層上，用以電性連接該第—銲線與該第 4 其中t如巾請專職圍第15項所述之多晶片封事件 其中該第-導電層係—金屬片。 5對裝件， =如申請專職圍第15销叙多晶 其中該第一導電層係一金屬薄膜。 裝件 22. 如申請專利範圍第15項所述之多晶片封 八中該第—導電層係包含鋁。 、 23. 如申請專利範圍第15項所述之多晶片封裝 ，、中該多晶片封裝件更包括： 石夕主；虛晶片’係設置於該第二晶片上’該虛晶片包括-體以及該第一導電層，該第一導電層係形成於丄 24. 其中該第 接地區。 25. 包括： 如申請專利範圍第15項所述之多晶片封裝件， 一銲線係連接該第一導電層以及該承載器之該 如申請專利範圍第15項所述之多晶片封裝件更 一第二絕緣層，係設置於該第一導電層表面； 一第二導電層，係設置於該第一絕緣層之上，並透過 至少一第三銲線電性連接於該承載器之該接地區。 26·如申請專利範圍第25項所述之多晶片封裝件， 18 1324817
其中包含至少一第四銲線電性連接該第二導電層及該第 一晶片。 27.如申請專利範圍第25項所述之多晶片封裝件， 其中包含至少一第四銲線電性連接該第二導電層及該第 二晶片 〇 19 1324817 « I »
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