TWI319616B - Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging - Google Patents
Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packagingInfo
- Publication number
- TWI319616B TWI319616B TW095113528A TW95113528A TWI319616B TW I319616 B TWI319616 B TW I319616B TW 095113528 A TW095113528 A TW 095113528A TW 95113528 A TW95113528 A TW 95113528A TW I319616 B TWI319616 B TW I319616B
- Authority
- TW
- Taiwan
- Prior art keywords
- wave pattern
- semiconductor
- rigid wave
- circuit board
- printed circuit
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title abstract 4
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000004806 packaging method and process Methods 0.000 title 1
- 238000005336 cracking Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 238000000465 moulding Methods 0.000 abstract 1
Classifications
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- H01L2924/151—Die mounting substrate
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- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15323—Connection portion the connection portion being formed on the die mounting surface of the substrate being a land array, e.g. LGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15333—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a land array, e.g. LGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/106,699 US7355283B2 (en) | 2005-04-14 | 2005-04-14 | Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging |
Publications (2)
Publication Number | Publication Date |
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TW200644206A TW200644206A (en) | 2006-12-16 |
TWI319616B true TWI319616B (en) | 2010-01-11 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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TW095113528A TWI319616B (en) | 2005-04-14 | 2006-04-14 | Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging |
Country Status (7)
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US (4) | US7355283B2 (zh) |
EP (1) | EP1869704A1 (zh) |
JP (1) | JP2008537336A (zh) |
KR (1) | KR100934269B1 (zh) |
CN (1) | CN100547779C (zh) |
TW (1) | TWI319616B (zh) |
WO (1) | WO2006113171A1 (zh) |
Families Citing this family (14)
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US7355283B2 (en) | 2005-04-14 | 2008-04-08 | Sandisk Corporation | Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging |
FR2919486B1 (fr) * | 2007-07-31 | 2009-10-02 | Captomed Entpr Unipersonnelle | Capteur de pression auto-etalonnable. |
US20090302479A1 (en) * | 2008-06-06 | 2009-12-10 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Semiconductor structures having vias |
US9164404B2 (en) * | 2008-09-19 | 2015-10-20 | Intel Corporation | System and process for fabricating semiconductor packages |
US9165841B2 (en) * | 2008-09-19 | 2015-10-20 | Intel Corporation | System and process for fabricating semiconductor packages |
US20110024898A1 (en) * | 2009-07-31 | 2011-02-03 | Ati Technologies Ulc | Method of manufacturing substrates having asymmetric buildup layers |
TWI508268B (zh) * | 2011-07-13 | 2015-11-11 | Powertech Technology Inc | 無基板之快閃記憶卡之製造方法 |
KR102040194B1 (ko) * | 2013-03-25 | 2019-11-04 | 삼성에스디아이 주식회사 | 이차전지 연결용 회로기판 |
US20150053459A1 (en) | 2013-08-20 | 2015-02-26 | Carestream Health, Inc. | Patterning of electrically conductive films |
US20150107878A1 (en) | 2013-10-21 | 2015-04-23 | Carestream Health, Inc. | Invisible patterns for transparent electrically conductive films |
US9953934B2 (en) * | 2015-12-16 | 2018-04-24 | Intel Corporation | Warpage controlled package and method for same |
US10074590B1 (en) | 2017-07-02 | 2018-09-11 | Infineon Technologies Ag | Molded package with chip carrier comprising brazed electrically conductive layers |
CN109712955B (zh) * | 2018-11-23 | 2021-05-11 | 华为技术有限公司 | 一种基于pcb本体出引脚的封装模块及其制备方法 |
CN110745772B (zh) * | 2019-10-21 | 2023-10-20 | 重庆大学 | 一种mems应力隔离封装结构及其制造方法 |
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US5313102A (en) * | 1989-12-22 | 1994-05-17 | Texas Instruments Incorporated | Integrated circuit device having a polyimide moisture barrier coating |
DE69431023T2 (de) * | 1993-09-01 | 2003-02-06 | Toshiba Kawasaki Kk | Halbleiteraufbau und Verfahren zur Herstellung |
US5686356A (en) * | 1994-09-30 | 1997-11-11 | Texas Instruments Incorporated | Conductor reticulation for improved device planarity |
US5468655A (en) * | 1994-10-31 | 1995-11-21 | Motorola, Inc. | Method for forming a temporary attachment between a semiconductor die and a substrate using a metal paste comprising spherical modules |
JPH1154658A (ja) * | 1997-07-30 | 1999-02-26 | Hitachi Ltd | 半導体装置及びその製造方法並びにフレーム構造体 |
EP0924762A3 (en) | 1997-12-22 | 2002-04-24 | Siemens Aktiengesellschaft | Interconnections in integrated circuit devices |
TW432569B (en) | 1999-08-05 | 2001-05-01 | Ind Tech Res Inst | IC die formed with a built-in stress test pattern and its manufacturing method |
US6449748B1 (en) * | 1999-08-09 | 2002-09-10 | Lsi Logic Corporation | Non-destructive method of detecting die crack problems |
US6251695B1 (en) | 1999-09-01 | 2001-06-26 | S3 Graphics Co., Ltd. | Multichip module packaging process for known good die burn-in |
US6245597B1 (en) * | 1999-09-28 | 2001-06-12 | Microchip Technology Incorporated | Method for reducing die cracking in integrated circuits |
US6497943B1 (en) * | 2000-02-14 | 2002-12-24 | International Business Machines Corporation | Surface metal balancing to reduce chip carrier flexing |
US6344401B1 (en) | 2000-03-09 | 2002-02-05 | Atmel Corporation | Method of forming a stacked-die integrated circuit chip package on a water level |
US6365966B1 (en) * | 2000-08-07 | 2002-04-02 | Advanced Semiconductor Engineering, Inc. | Stacked chip scale package |
JP3827520B2 (ja) * | 2000-11-02 | 2006-09-27 | 株式会社ルネサステクノロジ | 半導体装置 |
US6396135B1 (en) * | 2000-12-21 | 2002-05-28 | National Semiconductor Corporation | Substrate for use in semiconductor packaging |
KR100500469B1 (ko) * | 2001-01-12 | 2005-07-12 | 삼성전자주식회사 | 정렬마크와 이를 이용하는 노광정렬시스템 및 그 정렬방법 |
JP2002217215A (ja) * | 2001-01-16 | 2002-08-02 | Toshiba Microelectronics Corp | 半導体装置 |
JP2003007916A (ja) * | 2001-06-19 | 2003-01-10 | Sanyo Electric Co Ltd | 回路装置の製造方法 |
JP2003124387A (ja) * | 2001-10-10 | 2003-04-25 | Sony Corp | 半導体装置及び該半導体装置に使用されるプリント基板 |
US6709977B2 (en) * | 2002-02-12 | 2004-03-23 | Broadcom Corporation | Integrated circuit having oversized components and method of manafacture thereof |
JP3679786B2 (ja) * | 2002-06-25 | 2005-08-03 | 松下電器産業株式会社 | 半導体装置の製造方法 |
US6992380B2 (en) * | 2003-08-29 | 2006-01-31 | Texas Instruments Incorporated | Package for semiconductor device having a device-supporting polymeric material covering a solder ball array area |
JP4359257B2 (ja) * | 2004-07-06 | 2009-11-04 | 三星電機株式会社 | Bgaパッケージおよびその製造方法 |
US7355283B2 (en) * | 2005-04-14 | 2008-04-08 | Sandisk Corporation | Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging |
-
2005
- 2005-04-14 US US11/106,699 patent/US7355283B2/en not_active Expired - Fee Related
-
2006
- 2006-04-06 EP EP06740712A patent/EP1869704A1/en not_active Withdrawn
- 2006-04-06 KR KR1020077026534A patent/KR100934269B1/ko not_active IP Right Cessation
- 2006-04-06 CN CNB2006800119781A patent/CN100547779C/zh not_active Expired - Fee Related
- 2006-04-06 WO PCT/US2006/013038 patent/WO2006113171A1/en active Application Filing
- 2006-04-06 JP JP2008506538A patent/JP2008537336A/ja active Pending
- 2006-04-14 TW TW095113528A patent/TWI319616B/zh not_active IP Right Cessation
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2007
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2013
- 2013-07-15 US US13/941,823 patent/US8878368B2/en not_active Expired - Fee Related
-
2014
- 2014-10-30 US US14/528,671 patent/US9230919B2/en not_active Expired - Fee Related
Also Published As
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WO2006113171A1 (en) | 2006-10-26 |
US20060231943A1 (en) | 2006-10-19 |
TW200644206A (en) | 2006-12-16 |
EP1869704A1 (en) | 2007-12-26 |
US7355283B2 (en) | 2008-04-08 |
US20150054177A1 (en) | 2015-02-26 |
KR20080024463A (ko) | 2008-03-18 |
CN100547779C (zh) | 2009-10-07 |
KR100934269B1 (ko) | 2009-12-28 |
US8487441B2 (en) | 2013-07-16 |
US20130299959A1 (en) | 2013-11-14 |
US20080054445A1 (en) | 2008-03-06 |
CN101238576A (zh) | 2008-08-06 |
US9230919B2 (en) | 2016-01-05 |
US8878368B2 (en) | 2014-11-04 |
JP2008537336A (ja) | 2008-09-11 |
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Legal Events
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MM4A | Annulment or lapse of patent due to non-payment of fees |