TWI319616B - Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging - Google Patents

Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging

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Publication number
TWI319616B
TWI319616B TW095113528A TW95113528A TWI319616B TW I319616 B TWI319616 B TW I319616B TW 095113528 A TW095113528 A TW 095113528A TW 95113528 A TW95113528 A TW 95113528A TW I319616 B TWI319616 B TW I319616B
Authority
TW
Taiwan
Prior art keywords
wave pattern
semiconductor
rigid wave
circuit board
printed circuit
Prior art date
Application number
TW095113528A
Other languages
English (en)
Other versions
TW200644206A (en
Inventor
Chin Tien Chiu
Chih Chin Liao
Ken Jian Ming Wang
Han Shiao Chen
Cheemen Yu
Hem Takiar
Original Assignee
Sandisk Corp
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Publication date
Application filed by Sandisk Corp filed Critical Sandisk Corp
Publication of TW200644206A publication Critical patent/TW200644206A/zh
Application granted granted Critical
Publication of TWI319616B publication Critical patent/TWI319616B/zh

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    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15323Connection portion the connection portion being formed on the die mounting surface of the substrate being a land array, e.g. LGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15333Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a land array, e.g. LGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
TW095113528A 2005-04-14 2006-04-14 Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging TWI319616B (en)

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US11/106,699 US7355283B2 (en) 2005-04-14 2005-04-14 Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging

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TWI319616B true TWI319616B (en) 2010-01-11

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EP (1) EP1869704A1 (zh)
JP (1) JP2008537336A (zh)
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WO2006113171A1 (en) 2006-10-26
US20060231943A1 (en) 2006-10-19
TW200644206A (en) 2006-12-16
EP1869704A1 (en) 2007-12-26
US7355283B2 (en) 2008-04-08
US20150054177A1 (en) 2015-02-26
KR20080024463A (ko) 2008-03-18
CN100547779C (zh) 2009-10-07
KR100934269B1 (ko) 2009-12-28
US8487441B2 (en) 2013-07-16
US20130299959A1 (en) 2013-11-14
US20080054445A1 (en) 2008-03-06
CN101238576A (zh) 2008-08-06
US9230919B2 (en) 2016-01-05
US8878368B2 (en) 2014-11-04
JP2008537336A (ja) 2008-09-11

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