TW432569B - IC die formed with a built-in stress test pattern and its manufacturing method - Google Patents

Abstract

The present invention discloses an IC die formed with a built-in stress test pattern and its manufacturing method. The method comprises: forming a stress test pattern on the corner region of the IC die, depositing a dielectric layer on a substrate; forming a plurality of diagonally arranged linear metal wires made of a first metal material; depositing an insulated material layer on the top of the metal wires; and forming a plurality of L-shaped metal stripes of a second metal material arranged in a manner that the two sides of the L-shape are parallel with the two sides of the corner region, and are overlapped with the metal stripes so that the insulated material layer is disposed therebetween. The metal wires and the metal stripes are connected to contact pads, respectively. After the IC die is packaged, multiple thermal cycle tests are performed to measure the resistance between the two metal layers from the contact pads, thereby determining the formed thermal mechanical stress.

Description

^ 432569

V. Description of the invention (1) [Scope of the invention The present invention relates to an integrated circuit 卞 di a with a built-in stress test pattern steam (bui 11-instresstestpa 11 er η), a method thereof, and particularly a kind of Using the two-metal method of bimetal sandwiching bright particles (layers), a built-in stress test pattern is formed at each insulation angle i, and then encapsulated in a molding compound, and the method of demonizing grains ... 4. Cyclic just-trial crystal [Background of the invention] In the manufacturing of integrated circuit (1C) devices, it is common that the failure of the product due to stress and deformation is caused by the confusion in the material, t too many lattice vacancies, ', and internal forces caused by impurities' thermal gradient generated in the process to change with the temperature formed after bonding with the inhomogeneity. For example, the same material crystal system, complex Vapor deposition materials of crystalline or single crystal systems show a large internal stress when they are right or wrong. Both will be in the process of sedimentation _ This kind of stress and deformation problems often occur in one day, the film of material When it is completed, these different materials can be: ^ ^ There are no oxide, metal conductor layer, protective dielectric layer and used for packaging ^ = silicon, silicon. The wafer composition usually includes a semiconductor-dielectric layer structure, It is particularly easy to produce differential expansion induced stress due to different thermal expansion coefficients of various materials. In addition, various films of different materials may have internal stress generated during the deposition process, which will further increase the thermal initiation. (ThermaUy_induced) stress.

B4325S 9

In order to determine the value of the above-mentioned stress in the IC device and adversely affect the quality control or reliability of the device, the measurement appears to be quite equivalent = Ma Ho. The reliability problem when the farmer is closed usually involves depositing on the silicon surface. Cracking (cracking) occurs. The thermal cycle measurement using cold-headed alternating Le / film layers is iso t, t ^… 乂 # is called iso mi —. It can also be obtained by the expansion coefficient of different material interfaces: Thermal mechanical stress. The difference between the number and the number of c is composed of generally square grains. It has been found that the area where the differential expansion induces the most serious stress formation ^ θ, falls, and most of the material layers exist in the form of shear stress. At the same time, the insulation between the dielectric layer and the metal layer is seriously affected, and the adhesion between the oxide layer and the silicon surface will be severed. @Presence of various reliability: the adverse effects of silicon. Since most of the materials used to form metal layers and dielectric banks are fixed and cannot be changed, the choice of the elastic edge 11 layer becomes an important factor in IC packaging, and its selection must reduce the top / product generation to lowest. For this purpose, a built-in: = test pattern must be formed on the κ test grain to evaluate the different expansion coefficients between the materials. Taking the adverse effects of the present invention [Objective of the invention] The purpose of the present invention is to provide an IC die with a built-in stress test, which will not cause the c-packaged tea to cause the traditional test method.

1 ^ / ti | G LL · / I FIG. Another object of the present invention is to provide an IC die with a built-in solution, which can be easily fabricated during the manufacturing process. Another object of the present invention is to provide a Built-in stress test

Page 5 1 P4 325 6 9 _ p. Description of the invention (3) The pattern of I c grains does not require additional process steps compared to ordinary grain fabrication. It is still another object of the present invention to provide an I c crystal grain with a built-in stress test pattern. The built-in stress test pattern is formed at four corners of the grain. Yet another object of the present invention is to provide an IC die 'having a built-in stress test pattern, which has at least two stress test patterns formed at one of four corners, respectively. A further object of the present invention is to provide an I c die with at least two stress test patterns formed therein, wherein each pattern is formed on a silicon substrate firstly to form a dielectric layer, and then sequentially form a first-metal layer, a The dielectric insulating material layer and the first metal layer are finally packaged in a molding compound. 'Another' purpose of the present invention is to propose a method for testing the thermomechanical stress after IC die packaging. By providing at least two corners of the IC die with built-in, force test patterns, [C die in After the package, the thermal cycle test is used to detect the first and second metal layers in the test pattern to determine the leakage current and the thermomechanical stress mechanism. Ϊ́ Π: Τ Π = provides a test for 1C die sealing after thermal sealing, spoon Eight / By using the built-in stress measurement in the corner area of the 1 c grain, the L-shaped profile is completely formed. 5 A linear metal guide is formed. A first metal layer of the wire and a formation [the general description of the invention] the second metal beauty -sacrifice

Trying to post! The purpose of this invention is to provide a kind of circuit chip with built-in stress measurement phantom product and its method.

r V. Description of the invention ¢ 4) In a preferred embodiment, the 1C die with a built-in stress test pattern has four corner regions on the silicon substrate, and at least ~ two blind_intention-force test patterns are formed respectively In one of the four areas, the test pattern includes a U material layer deposited on a silicon plate, and then a plurality of linear metal wires arranged diagonally of the first gold are formed, and then an electrically insulating material layer is deposited on the metal wires. The top surface 'of the L-shaped second metal metal strip is finally formed, which is arranged in such a way that the two sides of the L-shape are parallel to the two sides of the corner area, and overlap with the metal wires, so that the layer of the electrically insulating material is interposed therebetween. between. Built-in stress test patterns formed in IC grains, each of which [type metal strip s electric! · When connected to the contact pad as a contact probe, three stress measurements can be formed in the corner area, and an alignment mark is formed in the fourth corner area. The sample IC chip is one of most crystalline silicon formed on a silicon wafer, and the l-shaped metal bar may include a number between about two and ten. The number of L-shaped metal strips is between three and five. A can form an I ^ Ϊ arrangement with each other. 'L-shaped metal strips are superimposed on the metal wire, so that it is from above. The lead is in the heart. Intersect, metal wire :. Strips can be made of A or Shao alloy A. The die will go one step further to complete the package with the die edge a. _Q ^^^ t is more targeted at the disclosure-a kind of K die is tested for thermal mechanical packaging. An integrated circuit die 1 is provided-which has four, four, and four pictures: an ancient stone substrate, and at least two stress test patterns. Stress 2 & 2 ^ b ~ The dielectric material layer is formed on a silicon substrate, a linear metal wire arranged diagonally by the first metal,-an electrically insulating material 7 "belonging to the top of the wire & Secondary metal

* 43256 9 two wires are used in the trial product bit method; the step three is more inclusive, and the wire product is circulated for a second time. Example V. Description of the invention (5) Several L-shaped metal bars, with their L-shape Lined up and overlapped between metal guides. Next, package the integrated circuit die and body circuit package; and then detect the thermo-mechanical stress between the metal wire and the metal strip after the thermal cycle test. This step of molding a composite material of polymer material for testing thermomechanical stress is used as a test pattern for detecting a contact pad of a contact point in any of the four corner regions. The step of forming a metal wire and a metal strip is formed. A step of a metal strip having a thickness of about 0.5 / zm; and further comprising at least 10 times of the number of cold and hot times of 55 ° C to 150 ° C, or a cycle of cold and heat to make the above and the present invention easier to understand The following is a detailed description of the following. [Explanation of the drawings] FIG. 1 is a large number of [C crystal grains with the built-in application of the present invention on the crystal grains. FIG. 2 is an enlarged plan view of the IC crystal grains of FIG. 1. Let the C edge metal layers on the two sides of the corner area be formed in the k compound—base circuit package to w, +1 product to > ten times; most of its current is measured to determine ^ include packaging The integrated circuit includes — further comprising electrically connecting metal strips to: further includes forming three stress measurement areas, and forming an alignment mark containing one of aluminum or aluminum alloy cards or one of aluminum or aluminum alloys and one of them The gold circuit package having a thickness of about 10 μm is placed in a step with a temperature of about 100 ′, and the number of cold and hot cycles is between 10 and 100. The features, characteristics, and advantages can be made clearer, and in accordance with the accompanying drawings, the top view formed on a Shixi substrate and a force test pattern are detailed. Corners with built-in stress test patterns

[4 ^ 256 V. Description of the invention (6) Special Figure 3 is an enlarged plan view of the built-in stress test pattern of Figure 2. Don't show the metal wires and L-shaped metal strips. The fourth figure is an enlarged sectional view of the built-in stress test pattern of the present invention. It is not gold, and an insulating layer is sandwiched between layer 1 and metal layer 2. Figures A through D are the test results of the stress test pattern of the present invention formed at different insulating layers in thickness and overetching time conditions. Figures 6 A through C are the different embodiments of the stress test pattern of the present invention. Fig. 7 is the curve of the pattern failure corresponding to the increase in the number of people, which is drawn from the test results in Fig. 5 a to D. [Explanation of the Example] The present invention discloses a structure and a method for forming at least two force test patterns at four corners of an IC grain. Basically, the stress test chart is as follows: 沉积 = a layer of dielectric material is deposited on the -silicon substrate, and then forms a majority of the linear metal wires arranged diagonally, and then a second gold 层 layer is deposited on the silicon substrate. The top of the metal wire ® finally forms a number of Tailings bars on both sides of the L plastic. The two sides of the T-shaped parallel to the corner I range between '-1'. And overlap with the metal wire-so that the electrical The present invention can be used to evaluate different manufacturing materials, and can be used to evaluate the new molding process used in IC packages: components and die formation. In the case of the molding compound or the packaging metal bar and each metal wire are electrically connected to the ^ \ pattern, each L-shaped gold has to flow through the metal bar and the metal wire. , So that-can be measured when a bad current flows through the page 9 ® 4 32 5 b ^ V. Description of the invention (7). The new stress test pattern used is to predict the thermo-mechanical response between layers of different materials, or between welding wires and packaging materials by using a bimetal method of “two layers, metal and no insulation”. This bimetallic stress pattern is most suitable for forming in corners or corner areas because the 'corner area-domain pass-through' is the concentration of thermo-mechanical stress after the packaging process. The two metal layers are deposited by a common process during the production process, without the need for additional masks or photolithography procedures. First, a traditional metal deposition step is used, for example, a metal sputter process is used to deposit a metal layer, and then it is etched to form a specific pattern. For example, a metal layer 1 made of aluminum alloy or aluminum alloy is deposited first, and then etched into a pair of diagonally arranged linear metal wires located in the C-corner-corner area; similarly, a conductive metal layer 2 is deposited and then etched An L-shaped metal strip is on the top surface of an insulating layer, and the insulating layer is located between the metal layer 1 and the metal layer 2. The thermal connection between the layers is formed when the two leakage currents are formed by the stress of the construction machinery. When wiring, know the type of electricity. When using «,", and contact pads, the metal layer can be used to test the IC cover of the electrical system. Therefore, the reliable 4 td stress condition cannot be measured and can be predicted by the existence of the connection. The stress resistance value is built in the package of the IC crystal package, that is, the butt welding is predictable in advance. Mechanical stress, the amount of contact, resistance will be very high. This leakage of electricity can be compared with the force of the test pattern invented by any new IC test pattern. Generally, it can be measured by males. In general, two large amounts of thermal stress current values represent experimental data, and the metal layer stress test chart method can be used for negative fractures generated after the measurement. The amount of padding gives a thermal stress value, and therefore, the heat shows. Plate, and the effect of forming a molding line or. Compared to Xi

Page 10 w V. Description of the invention (8) Please refer to "Figure 1", which illustrates the layout of the wafer of the present invention. The wafer layout 10 is formed on a silicon substrate 12 and has a plurality of IC grains 16 that can be formed on a silicon wafer of any size. For example, it is a 6-inch, 8-inch, or 12-inch wafer. Each of the IC crystals 16 is provided with a built-in stress test pattern 20 at three positions in the four corner regions, and an alignment mark (a 1 i g n m e n t m a r k) 2 2 is provided in the fourth corner. The number of stress test patterns on the IC die 16 is not necessarily three, but may be two. At this time, the positions of the other corner regions are set with alignment marks 22. In addition, when a stress test pattern is formed on the IC grains 16, the IC grains 16 are generally not provided with an IC circuit. Please refer to "Fig. 2" for an enlarged view of the IC die. The provided stress test pattern 20 is located at the three corner areas of the IC die 16 and the alignment mark 22 is located at the fourth corner. The contact pads 26 are respectively connected to the metal layer 1 and the metal layer 2 through a via (v 丨 a) (not shown) (none shown). The detailed stress test pattern is enlarged and shown in "Figure 3". In Figure 3 ", a bimetal method is used to sandwich an insulating layer to form the stress test pattern 20 '. This can be understood more clearly from the sectional view of" Figure 4. "A thermal oxide layer is first formed on the top surface of a stone substrate 30 μ, the thickness is about 1 // in ~ 5 / ze, and then, the metal layer 丄 (not shown) is deposited on the top surface of the thermal oxide layer 3 2 in total, and then a plurality of diagonally arranged The linear metal wire 36, the metal wire 36, and the two sides 3, 3, 4 of the grain 36 respectively form a 45 ° intersection, forming a thickness of between about 0.5 and 10, preferably between i and, for example, A suitable metal layer i may have a thickness of l · 2 パ m. Then, a dielectric material f, such as an insulating layer 40 of oxide or nitride, will be deposited on the metal wire. The appropriate thickness is between ㈣㈣ ... between.

P43256 9 V. Description of the Invention (9) The insulating layer 40 can be formed by a suitable deposition method, one of which is a chemical vapor deposition technique. The surface of the insulating layer 40 will be wavy, because a thicker portion formed with the metal wire 36 will cause a larger shrinkage. After that, a metal layer 2 (not shown) is deposited on the top surface of the insulating layer 40, and then a plurality of L-shaped metal bars 50 'are defined by the lithography technique, as shown in "Figs. 3 and 4". The other L-shaped metal strips 48, 52, and 54 are also formed in the same process, and the same mask can be used in the lithography and etching processes. As shown in FIG. 3, all four l-shaped metal bars overlap at a 45 ° angle with the metal wires 36, and the distance between the metal wires is much smaller than the distance between the L-shaped metal bars. The contact pad is connected to the L-shaped metal bar. For example, the metal pad 60 is electrically connected to the L-shaped metal bar 50 through a metal wire 62 and a via (not shown), and the metal pad 70 is connected through a metal wire 72 and A dielectric layer (not shown) is electrically connected to the L-shaped metal strip 54. Metal wires are connected to the contact pads (not shown in "Figure 3"), which are determined by the contact pads 60 and 70 in the star detection test. When a current flows through the insulation layer 4 of "Figure 4", the metal The resistance value between layer 1 and metal layer 2. "Figure 5 A to D" shows the results of the novel stress test pattern of the present invention: "Figures 5 A and 5 B" > Do not exemplify that the IC die has two different stress tests in different angular regions In the case of patterns b, ^, for pattern 1), the width of the σ L-shaped metal strip is 50 # m with a pitch of 30, and the width of the L-shaped metal strip of pattern c is “^^, and the pitch is 55 // [11; the width of the L-shaped metal strip in case d is iQ _. The thickness of the insulating layer formed by the ic grains in "Figure ^ a" is 8000a, and after 40 seconds of overetching (overetching) In Fig. 5 β, the thickness of the insulation layer formed by [c grains]

Page 12 1432569 V. Description of the invention (ίο) The degree is 9 0 0 0 A, after 40 seconds of over-etching; similarly, the thickness of the insulating layer formed by the test grains in FIG. 5 C is 8 0 0 0 A, After 50 seconds of over-etching, the thickness of the insulating layer formed by the test grains in "Figure 5D" was 9 0 0 A, and after 50 seconds of over-etching ° In the above figure, the number of times of thermal cycling tests increased The corresponding data of the number of pattern failures can be compared with the results drawn in "Figure 7", and it can be seen that usually with the increase of the number of thermal cycle tests, more failure results are produced. The patterns b, c, and d listed in "Fig. 5 A ~ D" are only an example, and are not limited to the stress test patterns that can be used in the present invention. For example, the "6th A to C" diagrams are several other variations. In the embodiment, anyone who can match the specific pattern of the IC die or achieve the purpose of the invention test can be used as the embodiment. Therefore, any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention, and the protection scope of the present invention shall be determined by the scope of the attached patent application. [Illustration of symbols in the figure] 1 0 chip layout 1 2 silicon substrate 1 6 I C die 2 0 stress test pattern 2 2 alignment mark 26 contact pad 3 0 broken substrate 3 2 thermal oxide layer

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Claims (1)

"43256 9_ χ, patent application scope 1, an integrated circuit die formed with a built-in stress test pattern, including a stone substrate with four corner areas; and at least two stress test patterns formed on the four One of the corner areas includes: a dielectric material layer formed on the silicon substrate; a plurality of diagonally arranged linear metal wires formed of a first metal; an electrically insulating material layer formed on the metals The top surface of the wire; and a plurality of L-shaped metal bars formed of a second metal, arranged so that both sides of the L-shape are parallel to both sides of the corner region, and overlapped with the metal wires to make the electrical property The insulating material layer is interposed between W 2 and the integrated circuit die described in item 1 of the scope of the patent application, and further includes a contact pad as a contact point for detection, and each of the metal bars forms an electrical connection with it. 3. The integrated circuit die as described in item 1 of the scope of patent application, wherein the test patterns are three and are formed in any two of the four corner regions. 4. The integrated circuit die described in item 3 of the scope of the patent application, further including an alignment mark formed in the fourth corner region. 5. The integrated circuit die described in item 1 of the scope of patent application. Is one of a plurality of integrated circuit dies formed on a silicon wafer. Page 15 PT4 325 6 9 6. Scope of patent application 6. The integrated circuit die as described in item 1 of the scope of patent application, wherein the number of these metal bars is between about 2 and 10. 7. The integrated circuit die as described in item 1 of the scope of patent application, wherein the number of these metal bars is preferably between 35 and 5. 8. The integrated circuit die as described in item 1 of the scope of patent application, wherein the metal bars are arranged to be parallel to each other. 9. According to the integrated circuit die described in item 1 of the scope of the patent application, wherein the overlap of the metal bar and the metal wires is viewed from the direction above the integrated circuit die, the L of the metal bar is The two sides of the pattern intersect with the metal wire by 45 °. 10. The integrated circuit die as described in item 1 of the scope of patent application, wherein the first metal and the second metal are one of Shao or Ming alloy. 1 1. The integrated circuit die as described in item 1 of the scope of the patent application, further comprising a molding compound formed on the integrated circuit die to encapsulate the metal bars. 1 2. A method for testing the thermo-mechanical stress of an integrated circuit die package, comprising: providing an integrated circuit die, including a silicon substrate having four corner regions, and at least two stress test patterns, each having A dielectric material layer is formed on the silicon substrate, a plurality of diagonally arranged linear metal wires formed of a first metal, an electrically insulating material layer is formed on a top surface of the metal wires, and a second A plurality of L-shaped metal bars formed of metal are arranged such that two sides of the L-shape are parallel to the two sides of the corner region and overlap the metal The layer on page 16 is between rM4 325 ^ 9 ------- 6. Apply for patent scope wire, make the electrical insulation metal package the integrated circuit die in a molded composite circuit package; cold and heat cycle test the The integrated body detects the metal wire and the to determine the thermo-mechanical stress. 1 3, as in the scope of the patent application, the method of thermomechanical stress of the package, and the step of molding the composite material. 4, as in the scope of the patent application, the method of thermomechanical stress of the package, as a contact pad to detect the contact point. The scope of the patent No. # 2 is a method of applying thermomechanical stress to any of the four corner regions. 16. The method of forming a thermo-mechanical stress in the scope of the patent application to form the metal wire and the metal 17. The method of forming the thermo-mechanical stress in the scope of the patent application to form a package with a thickness of about 0.5 in the metal Steps. 18, as described in the scope of the patent application _ extract the contents of the circuit package at least between the metal strips of item 12 as described in item 2 further includes a packaging step. The item ′ described in item 12 further includes an electrical step. As described in item 12, it further includes forming a region, and the item described in item 12 further includes the step of aluminum strip 12. As described in item 12, it further includes aluminum metal wire and a thickness of ten times; and Test the integrated circuit die by measuring its current. The integrated circuit is connected to the gold shoulder strips to the test integrated circuit die in a test integrated circuit die. The three stress test patterns of the integrated test die form an alignment mark on the test product. One of the body circuit grains or aluminum alloys. One of the test body circuit grains or alloys is about 1 0 # m. The test body circuit grains described by the J member "1432569 VI. The method for applying thermomechanical stress to a patented package, further comprising the step of subjecting the integrated circuit package to a plurality of cold and heat cycles at a temperature between about -55 ° C and 150 ° C. 1 9 、 If applied The method for testing the thermo-mechanical stress of a chip package of an integrated circuit as described in item 18 of the patent scope, wherein the number of times of these cold and heat cycles is at least 10. 20, as described in item 18 of the scope of patent application The method for testing the thermo-mechanical stress of integrated circuit die packages, wherein the number of the cold and heat cycles is between 10 and 100 times. Page 18