TWI318008B - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device

Info

Publication number
TWI318008B
TWI318008B TW095135544A TW95135544A TWI318008B TW I318008 B TWI318008 B TW I318008B TW 095135544 A TW095135544 A TW 095135544A TW 95135544 A TW95135544 A TW 95135544A TW I318008 B TWI318008 B TW I318008B
Authority
TW
Taiwan
Prior art keywords
semiconductor device
manufacturing semiconductor
manufacturing
semiconductor
Prior art date
Application number
TW095135544A
Other languages
English (en)
Other versions
TW200721494A (en
Inventor
Tomonari Yamamoto
Tomohiro Kubo
Original Assignee
Fujitsu Microelectronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Microelectronics Ltd filed Critical Fujitsu Microelectronics Ltd
Publication of TW200721494A publication Critical patent/TW200721494A/zh
Application granted granted Critical
Publication of TWI318008B publication Critical patent/TWI318008B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
TW095135544A 2005-09-28 2006-09-26 Method of manufacturing semiconductor device TWI318008B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005282652 2005-09-28
JP2006251373A JP5135743B2 (ja) 2005-09-28 2006-09-15 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
TW200721494A TW200721494A (en) 2007-06-01
TWI318008B true TWI318008B (en) 2009-12-01

Family

ID=37894617

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095135544A TWI318008B (en) 2005-09-28 2006-09-26 Method of manufacturing semiconductor device

Country Status (4)

Country Link
US (1) US7598162B2 (zh)
JP (1) JP5135743B2 (zh)
KR (1) KR100852973B1 (zh)
TW (1) TWI318008B (zh)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7772064B2 (en) * 2007-03-05 2010-08-10 United Microelectronics Corp. Method of fabricating self-aligned contact
US8273633B2 (en) * 2007-03-26 2012-09-25 Taiwan Semiconductor Manufacturing Co., Ltd. Method of enhancing dopant activation without suffering additional dopant diffusion
JP5086700B2 (ja) * 2007-06-06 2012-11-28 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5338042B2 (ja) * 2007-06-11 2013-11-13 富士通セミコンダクター株式会社 電界効果トランジスタの製造方法
JP2009188209A (ja) * 2008-02-06 2009-08-20 Panasonic Corp 不純物活性化熱処理方法及び熱処理装置
JP5235486B2 (ja) * 2008-05-07 2013-07-10 パナソニック株式会社 半導体装置
TWI535901B (zh) * 2008-09-29 2016-06-01 勝高股份有限公司 矽晶圓及其製造方法
US8592309B2 (en) * 2009-11-06 2013-11-26 Ultratech, Inc. Laser spike annealing for GaN LEDs
US10000965B2 (en) 2010-01-16 2018-06-19 Cardinal Cg Company Insulating glass unit transparent conductive coating technology
US10060180B2 (en) 2010-01-16 2018-08-28 Cardinal Cg Company Flash-treated indium tin oxide coatings, production methods, and insulating glass unit transparent conductive coating technology
US10000411B2 (en) 2010-01-16 2018-06-19 Cardinal Cg Company Insulating glass unit transparent conductivity and low emissivity coating technology
JP5499804B2 (ja) * 2010-03-19 2014-05-21 富士通セミコンダクター株式会社 半導体装置の製造方法
JP2011205049A (ja) * 2010-03-26 2011-10-13 Toshiba Corp 半導体集積回路
US8470700B2 (en) * 2010-07-22 2013-06-25 Globalfoundries Singapore Pte. Ltd. Semiconductor device with reduced contact resistance and method of manufacturing thereof
US11087984B2 (en) * 2018-10-29 2021-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Selective deposition by laser heating for forming a semiconductor structure
US11028012B2 (en) 2018-10-31 2021-06-08 Cardinal Cg Company Low solar heat gain coatings, laminated glass assemblies, and methods of producing same
WO2021152943A1 (ja) * 2020-01-30 2021-08-05 パナソニックＩｐマネジメント株式会社 撮像装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5266510A (en) * 1990-08-09 1993-11-30 Micron Technology, Inc. High performance sub-micron p-channel transistor with germanium implant
KR20010065303A (ko) 1999-12-29 2001-07-11 박종섭 반도체 소자의 트랜지스터 제조방법
US6391731B1 (en) * 2001-02-15 2002-05-21 Chartered Semiconductor Manufacturing Ltd. Activating source and drain junctions and extensions using a single laser anneal
JP3904936B2 (ja) * 2001-03-02 2007-04-11 富士通株式会社 半導体装置の製造方法
JP3746246B2 (ja) * 2002-04-16 2006-02-15 株式会社東芝 半導体装置の製造方法
JP4236992B2 (ja) * 2002-06-24 2009-03-11 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
JP3699946B2 (ja) * 2002-07-25 2005-09-28 株式会社東芝 半導体装置の製造方法
JP2005136351A (ja) * 2003-10-31 2005-05-26 Fujitsu Ltd 半導体装置及びその製造方法
JP2005142344A (ja) * 2003-11-06 2005-06-02 Toshiba Corp 半導体装置の製造方法および半導体製造装置
US6897118B1 (en) * 2004-02-11 2005-05-24 Chartered Semiconductor Manufacturing Ltd. Method of multiple pulse laser annealing to activate ultra-shallow junctions

Also Published As

Publication number Publication date
JP5135743B2 (ja) 2013-02-06
TW200721494A (en) 2007-06-01
JP2007123844A (ja) 2007-05-17
US20070072355A1 (en) 2007-03-29
KR20070035998A (ko) 2007-04-02
KR100852973B1 (ko) 2008-08-19
US7598162B2 (en) 2009-10-06

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees