TWI315848B - Dual thread processor - Google Patents

Dual thread processor

Info

Publication number
TWI315848B
TWI315848B TW095108580A TW95108580A TWI315848B TW I315848 B TWI315848 B TW I315848B TW 095108580 A TW095108580 A TW 095108580A TW 95108580 A TW95108580 A TW 95108580A TW I315848 B TWI315848 B TW I315848B
Authority
TW
Taiwan
Prior art keywords
thread processor
dual thread
dual
processor
thread
Prior art date
Application number
TW095108580A
Other languages
English (en)
Other versions
TW200710723A (en
Inventor
hong yi Chen
Sehat Sutardja
Original Assignee
Marvell World Trade Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marvell World Trade Ltd filed Critical Marvell World Trade Ltd
Publication of TW200710723A publication Critical patent/TW200710723A/zh
Application granted granted Critical
Publication of TWI315848B publication Critical patent/TWI315848B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
TW095108580A 2005-03-18 2006-03-14 Dual thread processor TWI315848B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/084,364 US8195922B2 (en) 2005-03-18 2005-03-18 System for dynamically allocating processing time to multiple threads

Publications (2)

Publication Number Publication Date
TW200710723A TW200710723A (en) 2007-03-16
TWI315848B true TWI315848B (en) 2009-10-11

Family

ID=36577509

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095108580A TWI315848B (en) 2005-03-18 2006-03-14 Dual thread processor

Country Status (6)

Country Link
US (2) US8195922B2 (zh)
EP (1) EP1703377A3 (zh)
JP (2) JP2006260571A (zh)
CN (1) CN100440139C (zh)
SG (1) SG126072A1 (zh)
TW (1) TWI315848B (zh)

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US8468324B2 (en) 2013-06-18
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JP2006260571A (ja) 2006-09-28
JP2008047145A (ja) 2008-02-28
SG126072A1 (en) 2006-10-30
US20060212687A1 (en) 2006-09-21
CN100440139C (zh) 2008-12-03
EP1703377A3 (en) 2007-11-28
CN1841314A (zh) 2006-10-04
US20120239908A1 (en) 2012-09-20
TW200710723A (en) 2007-03-16
JP4610593B2 (ja) 2011-01-12

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