TWI315548B - Planarizing gate material to improve gate critical dimension in semiconductor devices - Google Patents

Planarizing gate material to improve gate critical dimension in semiconductor devices

Info

Publication number
TWI315548B
TWI315548B TW092130613A TW92130613A TWI315548B TW I315548 B TWI315548 B TW I315548B TW 092130613 A TW092130613 A TW 092130613A TW 92130613 A TW92130613 A TW 92130613A TW I315548 B TWI315548 B TW I315548B
Authority
TW
Taiwan
Prior art keywords
gate
semiconductor devices
planarizing
critical dimension
improve
Prior art date
Application number
TW092130613A
Other languages
English (en)
Chinese (zh)
Other versions
TW200414326A (en
Inventor
Shibly S Ahmed
Cyrus E Tabery
Haihong Wang
Bin Yu
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of TW200414326A publication Critical patent/TW200414326A/zh
Application granted granted Critical
Publication of TWI315548B publication Critical patent/TWI315548B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6212—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies having non-rectangular cross-sections

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
TW092130613A 2002-11-08 2003-11-03 Planarizing gate material to improve gate critical dimension in semiconductor devices TWI315548B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/290,276 US6787439B2 (en) 2002-11-08 2002-11-08 Method using planarizing gate material to improve gate critical dimension in semiconductor devices

Publications (2)

Publication Number Publication Date
TW200414326A TW200414326A (en) 2004-08-01
TWI315548B true TWI315548B (en) 2009-10-01

Family

ID=32229010

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092130613A TWI315548B (en) 2002-11-08 2003-11-03 Planarizing gate material to improve gate critical dimension in semiconductor devices

Country Status (8)

Country Link
US (1) US6787439B2 (enExample)
EP (1) EP1559137A1 (enExample)
JP (1) JP2006505949A (enExample)
KR (1) KR101062029B1 (enExample)
CN (1) CN100505182C (enExample)
AU (1) AU2003282842A1 (enExample)
TW (1) TWI315548B (enExample)
WO (1) WO2004044973A1 (enExample)

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US6909151B2 (en) * 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US7456476B2 (en) * 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US7105390B2 (en) * 2003-12-30 2006-09-12 Intel Corporation Nonplanar transistors with metal gate electrodes
US7624192B2 (en) * 2003-12-30 2009-11-24 Microsoft Corporation Framework for user interaction with multiple network devices
US7268058B2 (en) * 2004-01-16 2007-09-11 Intel Corporation Tri-gate transistors and methods to fabricate same
US7115947B2 (en) * 2004-03-18 2006-10-03 International Business Machines Corporation Multiple dielectric finfet structure and method
US7154118B2 (en) 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
CN100461373C (zh) * 2004-05-20 2009-02-11 中芯国际集成电路制造(上海)有限公司 化学机械抛光用于接合多晶硅插拴制造方法及其结构
US7579280B2 (en) * 2004-06-01 2009-08-25 Intel Corporation Method of patterning a film
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US7071064B2 (en) * 2004-09-23 2006-07-04 Intel Corporation U-gate transistors and methods of fabrication
US7332439B2 (en) 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US7422946B2 (en) * 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US7361958B2 (en) * 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7193279B2 (en) * 2005-01-18 2007-03-20 Intel Corporation Non-planar MOS structure with a strained channel region
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US20060202266A1 (en) 2005-03-14 2006-09-14 Marko Radosavljevic Field effect transistor with metal source/drain regions
US7563701B2 (en) * 2005-03-31 2009-07-21 Intel Corporation Self-aligned contacts for transistors
JP4648096B2 (ja) * 2005-06-03 2011-03-09 株式会社東芝 半導体装置の製造方法
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7279375B2 (en) 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US7402875B2 (en) 2005-08-17 2008-07-22 Intel Corporation Lateral undercut of metal gate in SOI device
US20070090416A1 (en) * 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US7479421B2 (en) 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US7485503B2 (en) 2005-11-30 2009-02-03 Intel Corporation Dielectric interface for group III-V semiconductor device
US7396711B2 (en) * 2005-12-27 2008-07-08 Intel Corporation Method of fabricating a multi-cornered film
US20070152266A1 (en) * 2005-12-29 2007-07-05 Intel Corporation Method and structure for reducing the external resistance of a three-dimensional transistor through use of epitaxial layers
US7544594B2 (en) * 2006-06-28 2009-06-09 Intel Corporation Method of forming a transistor having gate protection and transistor formed according to the method
US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
US7435671B2 (en) * 2006-08-18 2008-10-14 International Business Machines Corporation Trilayer resist scheme for gate etching applications
EP2070533B1 (en) * 2007-12-11 2014-05-07 Apoteknos Para La Piel, s.l. Use of a compound derived from P-hydroxyphenyl propionic acid for the treatment of psoriasis
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
JP2010258124A (ja) * 2009-04-23 2010-11-11 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
CN102386065A (zh) * 2010-09-01 2012-03-21 无锡华润上华半导体有限公司 改善光刻临界尺寸均匀性的方法
US9041125B2 (en) * 2013-03-11 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Fin shape for fin field-effect transistors and method of forming
US9437445B1 (en) * 2015-02-24 2016-09-06 International Business Machines Corporation Dual fin integration for electron and hole mobility enhancement
US11018225B2 (en) * 2016-06-28 2021-05-25 International Business Machines Corporation III-V extension by high temperature plasma doping

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TW508737B (en) * 2001-05-02 2002-11-01 United Microelectronics Corp Planarization method for bottom anti-reflective layer during dual damascene process
US20020171107A1 (en) * 2001-05-21 2002-11-21 Baohong Cheng Method for forming a semiconductor device having elevated source and drain regions

Also Published As

Publication number Publication date
AU2003282842A1 (en) 2004-06-03
CN100505182C (zh) 2009-06-24
KR101062029B1 (ko) 2011-09-05
WO2004044973A1 (en) 2004-05-27
CN1711630A (zh) 2005-12-21
US6787439B2 (en) 2004-09-07
EP1559137A1 (en) 2005-08-03
US20040092062A1 (en) 2004-05-13
KR20050062655A (ko) 2005-06-23
TW200414326A (en) 2004-08-01
JP2006505949A (ja) 2006-02-16

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