1310561 九、發明說明： 【發明所屬之技術領域】 本發明大體上係有關於一種快閃記憶體裝置，以及更 特別地，是有關於一種使用一頁緩衝器以驗證一快閃記憶 體裝置的方法，其中可減少程式化或抹除驗證時間及可縮 短總驅動時間。 【先前技術】 近年來，對於半導體記憶體裝置已有增加之需求，其 Φ 中該等半導體記憶體裝置可被電性程式化及抹除以及不需 要在固定間隔下更新重寫資料之功能。再者，已發展一種 高整合技術之記憶體胞元，以發展具有能儲存大量資料之 大容量的記憶體裝置。 要增加該等記憶體胞元之整合，一 NAND快閃記憶體 裝置可具有串接以形成一個字串及共用一接點之兩個字串 的複數個單元。在該N AND快閃記憶體裝置中，藉由控制 該記憶體胞元之臨界電壓，同時藉由F-N穿隧以將電子注 φ 入一浮動閘極及從該浮動閘極釋放電子’以實施程式化及 抹除。 於是，因爲從該單元釋放該浮動閘極之電子，所以一 抹除單元具有一負臨界電壓。因爲將該等電子注入該浮動 閘極，所以一程式化單元具有一正臨界電壓。然而，在該 NAND快閃記憶體裝置之情況中，可能因電荷獲得及電荷漏 失而發生失靈。可以實施有關於這些特性之一些驗證。爲 了驗證是否已正常地實施程式化及抹除’而使用了 一頁緩 衝器。 1310561 該頁緩衝器用以從一 I/O墊接收大容量資料及供應該 接收資料至記憶體胞元或儲存記憶體胞元之資料及然後輸 出該儲存資料。過去，該頁緩衝器係由單一暫存器所構成， 以便暫時儲存資料。該頁緩衝器現在是由雙暫存器所構 成，以便在該NAND快閃記憶體裝置中程式化大容量資料 時增加該程式化速度。 要實施具有該雙暫存器結構之頁緩衝器的NAND快閃 記憶體裝置之抹除驗證，使用一種藉由施加0V電壓至全部 字元線以確認是否已導通所有單元之行掃描方法。在該行 掃描方法中，如果關閉一單元，則確定失靈。 爲了抹除驗證，在相同於一般讀取操作之方式中經由3 個步驟（包括預充電、評估及感測）對一選擇位元線實施抹除 驗證。在該行掃描方法中，藉由將該等位元線劃分成爲偶 數位元線及奇數位元線以抹除驗證。於是，在驗證該等偶 數位元線後，驗證該等奇數位元線。因此，經由兩次驗證 程序以確定已實施抹除。此導致一長抹除驗證時間。 同時，在一多層單元中，一抹除單元之臨界電壓分佈 對一程式化單元之臨界電壓具有影響。於是，對一已完成 抹除之單元實施一後程式化。藉由使用一 IS PP方法以實施 該後程式化及在該後程式化後實施抹除驗證。於是’如果 該抹除驗證變長，則延長總抹除時間。 再者，在程式化之同時，以相同於上述方式延長程式 化驗證時間。於是，總程式化時間變長。 【發明内容】 因此，本專利提出上述問題，以及揭露一種驗證一快 1310561 閃記憶體裝置之方法，其中該方法可縮短驗證時間及縮短 總驅動時間。 本專利進一步揭露一種驗證一快閃記憶體裝置之方 法 其中 偶數位兀線及一奇數位元線同時被預充電及評 估及接著連續地被感測，因此，減少驗證時間。 本專利進—步揭露一種驗證一快閃記憶體裝置之方 法’其中該方法相較於習知技藝可藉由同時預充電及評估 偶數位元線及奇數位元線及然後連續地感測該等偶數位元 線及奇數位兀線以減少一半驗證時間及因而減少總驅動時 間之2/3 。 依據本發明之一觀點，提供一種驗證一快閃記憶體裝 置之方法’該方法包括：分別使連接至一偶數位元線及一奇 數位元線之記憶體胞元串進行放電；施加一電壓至分別連接 至該偶數位元線及奇數位元線之每一記憶體胞元串，因而 預充電該等記憶體胞元串；藉由感測連接至該偶數位元線之 記憶體胞元串的狀態，以驗證是否已抹除連接至該偶數位 兀線之記憶體胞元串；以及藉由感測連接至該奇數位元線之 記憶體胞元串的狀態，以驗證是否已抹除連接至該奇數位 元線之記憶體胞元串。 並且’在此專利中描述一種驗證一快閃記憶體裝置之 方法’該方法包括：放電分別連接至一偶數位元線及一奇數 位元線之記憶體胞元串；施加一電壓至分別連接至該偶數位 元線及奇數位元線之記億體胞元串，因而預充電該等記憶 體胞元串；藉由感測連接至該偶數位元線之記憶體胞元串的 狀態’以驗證是否已程式化連接至該偶數位元線之記憶體 1310561 胞元串；以及藉由感測連接至該奇數位元線之記憶體胞元串 的狀態’以驗證是否已程式化連接至該奇數位元線之記億 體胞元串。 此專利又另外描述一種驗證一快閃記憶體裝置之方 法，其中該快閃記憶體裝置包括一第一電晶體，用以經由 一偶數位元線及一奇數位元線供應一驗證信號至一記憶體 - 胞元陣列以回應一第一控制信號；一第二電晶體，用以經由 該偶數位元線及奇數位元線連接該記憶體胞元陣列及一第 I 一節點以回應一第二控制信號；一第三電晶體，用以供應一 電流至該第一節點以回應一第三控制信號；一閂鎖器，用以 儲存來自該記憶體胞元陣列之一選擇單元的輸出資料；以及 一第四電晶體，用以依據該第一節點之一電壓位準及一第 四控制信號來控制該閂鎖器之狀態。該方法包括：分別彳吏連 接至該偶數位元線及該奇數位元線之記憶體胞元串進行放 電以回應該第一控制信號；同時供應一電壓至該第一節點以 回應該第三控制信號，及同時供應該第一節點之一電壓至 分別連接至該偶數位元線及該奇數位元線之記憶體胞元串 ® 以回應第一電壓位準之第二控制信號，因而預充電該等記 憶體胞元串；藉由儲存連接至該偶數位元線之記憶體胞元串 的狀態以驗證是否已抹除連接至該偶數位元線之記憶體胞 元串以回應第二電壓位準之第二控制信號；以及藉由儲存連 接至該奇數位元線之記憶體胞元串的狀態以驗證是否已抹 除連接至該奇數位元線之記億體胞元串以回應第三電壓位 準之第二控制信號。 可以使該第一控制信號保持在丨.6至5.5V之電壓位準 1310561 或一電源電壓Vcc。 可以使第一電壓位準之第二控制信號保持在1.0至 5 ·5ν之電壓位準或一電源電壓Vcc，可以使第二電壓位準之 第二控制信號保持在1.0至2.2V之電壓位準，以及可以使 該第二電壓位準保持在一相同於或低於該第一電壓位準之 電壓位準。 ^ 可以將第二電壓位準之第二控制信號的施加時間設定 成比第三電壓位準之第二控制信號的施加時間長。 φ 【實施方式】 現在，將參考所附圖式以描述本發明之各種實施例。 因爲爲了使熟習該項技藝之一般人士能了解本專利而提供 各種實施例，所以可以各種方式來修改該等實施例及本專 利之範圍並非侷限於稍後所述之各種實施例。 第1圖係在依據本發明之一實施例的一驗證一 NAND 快閃記憶體裝置之方法中所使用之一頁緩衝器的電路圖。 在第1圖中顯示在一具有一主暫存器及一快取暫存器之雙 φ 暫存器結構的頁緩衝器中之主暫存器的電路圖。 參考第1圖，一位元線選擇單元120包括複數個電晶 -體。驅動第一及第二NMOS電晶體N 1 0 1及N 1 02以分別回 ‘應偶數及奇數放電信號DISCHe及DISCHo，以及因此施加 一驗證電壓VIRPWR至一記憶體胞元陣列1 1〇的一記憶體胞 元串該記憶體胞元陣列1 1 0係連接至一偶數位元線BLe或 一奇數位元線B L 〇。驅動第三及第四N Μ 0 S電晶體N 1 0 3及 Ν104以分別回應偶數及奇數位元線選擇信號BSLe及 BSLo，以及於是，將該元陣列11〇之一位元線連接至一感 1310561 測節點s〇。 驅動一PMOS電晶體P101以回應一預充電信號PRECHb 及因而施加一電壓至該感測節點S〇。 —第五NM0S電晶體N105連接該感測節點SO及一閂 鎖器130之一輸出節點QAb以回應在一回寫程式化時之一 回寫信號C0PYBACK。該閂鎖器130暫時儲存該記憶體胞 元陣列1 1 0所輸出之輸出資料及外部所供應之資料。依據 該感測節點 SO之一電壓位準驅動一第六NM0S電晶體 N106。驅動一第七NM0S電晶體N107以回應一讀取信號 READ-L及因而連接該閂鎖器130之輸出節點QAb及一接地 端 V s s。 驅動一第八NM0S電晶體N108以回應一信號DI_L& 因而連接一 1/◦端YA及該閂鎖器130之輸出節點QAb。驅 動一第九NM0S電晶體N109以回應一信號nDI_L及因而連 接該I/O端YA及該閂鎖器130之一輸入節點QA。驅動一 第十NM0S電晶體N110以回應一重置信號RESET_L及因而 重置該閂鎖器130。驅動一第十一 NM0S電晶體N1 1 1以回 應在一程式化操作時之一信號PR〇GRAM_L及因而傳送所 要程式化之資訊至一選擇位元線。 驅動一第十二NM0S電晶體N1 12以回應一信號 PBD0_L及因而輸出一程式化節點NA之一電壓位準。再 者’一反向器1101反向該閂鎖器130之輸出節點QAb的電 壓位準並傳送一反向電壓位準至該程式化節點NA。 第2圖係用以描述依據本發明之一實施例的一驗證一 NAND快閃記憶體裝置之方法的頁緩衝器之操作波形。下面 -10- 1310561 將參考第1及2圖來描述依據本發明之一實施例的一 NAND 快閃記憶體裝置之一抹除驗證方法。 1) 週期A:放電 針對相同期間同時施加爲1 · 6至5.5 V之高位準或一電 源電壓Vcc的偶數及奇數放電信號DISCHe及DISCHo，以 便導通該第一及第二NM0S電晶體N101及N102。於是，經 由該第一及第二NM0S電晶體N101及N102,將該驗證信號 VIRPWR之電壓位準供應至該等位元線BLe及BLo。在抹除 驗證時之驗證信號VIRPWR維持0V之電壓位準。於是，以 0V之電壓供應至該偶數及奇數位元線BLe及BLo。再者， 供應該重置信號RES ET-L成爲高位準之脈衝，以便導通該 第十NM0S電晶體N110。因此，該節點QA變爲低位準以 及該節點QAb維持高位準。結果，重置該閂鎖器130。在 此時，供應0至1V之電壓至該所有字元線WL0至WL3 1， 以及亦供應0V之電壓至該汲極選擇線DSL及該源極選擇線 SSL。 2) 週期B:預充電 當施加低位準的該偶數及奇數放電信號DISCHe及 DISCHo時，關閉該第一及第二NM0S電晶體N101及N102。 再者，因爲施加低位準的該預充電信號PRECHb，所以導通 該第一 PM0S電晶體P101。於是，施加該電源電壓Vcc至 該感測節點SO，以便使該感測節點SO維持高位準。此外， 施加該偶數及奇數位元線選擇信號BSLe及BSLo成爲1.〇 至5.5V之電壓位準或約該電源電壓Vcc之第一電壓VI。因 此，分別施加該第一電壓VI及一電壓（VI-Vth)至該偶數及 Ι31〇561 奇數位元線BLe及BLo,其中該第一電壓VI減去該第三或 第四NMOS電晶體N103或N104之臨界電壓Vt。在此情況 中，施加一電壓至該汲極選擇線DSL。 3) 週期C:評估 當施加低位準的該偶數及奇數位元線選擇信號BSLe及 ' BSLo時，關閉該第三及第四NMOS電晶體N103及N104。 於是，停止對該偶數及奇數位元線BLe及BLo之供電，以 及依據分別連接至該偶數及奇數位元線BLe及BLo之記憶 φ 體胞元的狀態，來控制該偶數及奇數位元線BLe及BLo的 電壓位準。亦即，如果該記憶體胞元不是處於一抹除狀態， 則使該偶數或奇數位元線BLe或BLo之電壓位準保持爲 Vl-Vt之電壓位準。然而，如果該記憶體胞元處於一抹除狀 態，則使該偶數或奇數位元線BLe或BLo之電壓位準逐漸 從Vl-Vt減少及然後保持爲一低位準。在此時，因爲藉由 低位準之預充電信號PRECHb使該第一 PMOS電晶體P101 維持導通，所以該感測節點SO維持一高位準。同時，經由 一汲極選擇線DSL及一源極選擇線SSL而施加一高位準之 ^ 信號。設定該單元評估週期以維持1〇μ3或更少時間。 4) 週期D :偶數單元感測 當施加該預充電信號PRECHb成爲一高位準時’關閉該 第一 PMOS電晶體P201。當施加成爲第二電壓V2(該第二電 壓V2維持約1·〇至2.2V之電壓位準）至該偶數位元線選擇 信號BSLe時，導通該第三NMOS電晶體N103。如果該記憶 體胞元不是一抹除單元’則使該偶數位元線BLe之電壓位 準保持爲V ；l - Vt之電壓位準及使該感測節點SO之電壓位準 -12- 1310561 保持爲一高位準。如果該記憶體胞元處於一抹除狀態，則 使該偶數位元線BLe之電壓位準逐漸減少及然後維持爲一 低位準，以及使該感測節點SO之電壓位準保持爲一低位 準。在此狀態中，如果施加一高位準之脈衝爲1.〇至1 0μ5 的該讀取信號READ_L，則當一記憶體胞元不是一抹除單元 •時，使該感測節點SO保持爲一高位準。於是，導通該第六 NM0S電晶體N106及導通該第七NM0S電晶體N107以回應 高脈衝之讀取信號READ_L。結果，使該點QAb維持爲一低 φ 位準及使該節點QA維持爲一高位準。相反地，如果該記憶 體胞元爲該抹除單元，則使該感測節點SO保持爲一低位準 及關閉該第七NM0S電晶體N107。因此，使該節點QA保 持爲一高位準及使該節點QA保持爲一低位準。於是，偵測 該節點QA之電壓位準，以便感測該等偶數單元之狀態。 5)週期E:奇數單元感測 當施加低位準的該偶數位元線選擇信號BSLe時，關閉 該第三NM0S電晶體N103。當施加成爲一第三電壓V3(該 | 第三電壓V3維持爲約1.〇至2.2V之電壓位準）的該奇數位 元線選擇信號BSLo時，導通該第四NM0S電晶體N104。 需要該第三電壓V3低於或相同於該第二電壓V2及該第三 電壓V3之施加時間短於該第二電壓V2之施加時間。如果 該記憶體胞元不是一抹除單元，則使該奇數位元線BLo之 電壓位準保持爲V 1 -Vt之電壓位準及使該感測節點SO之電 壓位準保持爲一高位準。 然而，如果該記憶體胞元處於一抹除狀態，則使該奇 數位元線BLo之電壓位準逐漸減少及然後保持爲一低位 -13- 1310561 準，以及使該感測節點so之電壓位準保持爲一低位 此狀態中，施加該讀取信號READ_L成爲一高位準 有1.0至ΙΟμΞ。如果該記憶體胞元不是該抹除單元 該感測節點SO保持爲一高位準。於是，導通該第六 電晶體N106及導通該第七NM0S電晶體N107以回 脈衝之讀取信號READ_L。因爲使該節點QAb保持爲 準，所以使該節點QA保持爲一闻位準。相反地，該 胞元爲該抹除單元，使該感測節點S 0保持爲一低位 閉該第七NM0S電晶體N07。因此，使該節點QAb 一高位準及該節點QA保持爲一低位準。於是，偵測 QA之電壓位準，以便感測該等奇數單元之狀態。 上面已描述依據本發明之一實施例的NAND快 體裝置之一抹除驗證方法。然而，該方法可以以相 應用至一程式化驗證方法。於是，省略此一方法之 述。 如以上所述，同時預充電及評估以及然後連續 偶數位元線及奇數位元線。於是，相較於該習知技 少一半抹除驗證時間及相較於該習知技藝可減少總 間。因此，可改善一裝置之操作速度。再者，本發 相同方式應用至程式化驗證。因此，亦可減少程式化 雖然已參考各種實施例來實施上述描述，但是 熟習該項技藝之一般人士在不脫離本專利及所附請 精神及範圍內可以實施本專利之變更及修改。 【圖式簡單說明】 第1圖係在依據本發明之一實施例的一驗證一 準。在 之脈衝 ，則使 NM0S 應該高 一低位 記憶體 準及關 保持爲 該節點 閃記憶 同方式 詳細描 地感測 藝可減 抹除時 明可以 時間。 了解到 求項之1310561 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention generally relates to a flash memory device and, more particularly, to a page buffer for verifying a flash memory device. Method, which can reduce the stylization or erase verification time and shorten the total drive time. [Prior Art] In recent years, there has been an increasing demand for semiconductor memory devices in which the semiconductor memory devices can be electrically programmed and erased and the function of rewriting data is not required to be updated at regular intervals. Furthermore, memory cells of highly integrated technology have been developed to develop large-capacity memory devices capable of storing large amounts of data. To increase the integration of the memory cells, a NAND flash memory device can have a plurality of cells concatenated to form a string and share two strings of one contact. In the N AND flash memory device, by controlling the threshold voltage of the memory cell while tunneling through the FN to inject electrons into and out of the floating gate. Stylized and erased. Thus, since the electrons of the floating gate are released from the cell, an erasing cell has a negative threshold voltage. Since the electrons are injected into the floating gate, a stylized unit has a positive threshold voltage. However, in the case of the NAND flash memory device, malfunction may occur due to charge acquisition and charge loss. Some verification of these characteristics can be implemented. A page buffer was used to verify that stylization and erasure were performed normally. 1310561 The page buffer is used to receive large-capacity data from an I/O pad and supply the received data to a memory cell or a memory cell and then output the stored data. In the past, the page buffer was constructed from a single register to temporarily store data. The page buffer is now constructed by a dual register to increase the stylized speed when programming large amounts of data in the NAND flash memory device. To perform erase verification of a NAND flash memory device having a page buffer of the dual register structure, a line scanning method for confirming whether all cells have been turned on by applying a voltage of 0 V to all word lines is used. In this line scan method, if a unit is turned off, it is determined that it is malfunctioning. To erase the verification, an erase bit verification is performed on a selected bit line via three steps (including pre-charging, evaluation, and sensing) in the same manner as a normal read operation. In the line scanning method, the verification is performed by dividing the bit lines into even bit lines and odd bit lines. Thus, after verifying the even bit lines, the odd bit lines are verified. Therefore, the verification process has been performed via two verification procedures. This results in a long erase verification time. At the same time, in a multi-level cell, the threshold voltage distribution of a wiper unit has an effect on the threshold voltage of a stylized cell. Thus, a post-programming is performed on a unit that has been erased. The post-programming is performed by using an IS PP method and the erasure verification is performed after the post-stylization. Then 'if the erase verification becomes longer, the total erase time is extended. Furthermore, while stylizing, the programmatic verification time is extended in the same manner as described above. As a result, the total stylization time becomes longer. SUMMARY OF THE INVENTION Accordingly, this patent addresses the above problems and discloses a method of verifying a fast 1310561 flash memory device, wherein the method can shorten the verification time and shorten the total driving time. The present patent further discloses a method of verifying a flash memory device in which an even bit line and an odd bit line are simultaneously precharged and evaluated and then continuously sensed, thereby reducing the verification time. The present patent further discloses a method of verifying a flash memory device, wherein the method can simultaneously pre-charge and evaluate even bit lines and odd bit lines by simultaneously pre-charging and then continuously sensing the Wait for even bit lines and odd bit lines to reduce the verification time by half and thus reduce the total drive time by 2/3. According to one aspect of the present invention, a method for verifying a flash memory device is provided, the method comprising: respectively discharging a memory cell string connected to an even bit line and an odd bit line; applying a voltage Connecting to each of the memory cell strings of the even bit line and the odd bit line, respectively, thereby precharging the memory cell strings; by sensing the memory cells connected to the even bit lines The state of the string to verify whether the memory cell string connected to the even bit line has been erased; and to verify if the state has been erased by sensing the state of the memory cell string connected to the odd bit line In addition to the memory cell string connected to the odd bit line. And 'a method of verifying a flash memory device is described in the patent'. The method includes: discharging a memory cell string respectively connected to an even bit line and an odd bit line; applying a voltage to separately connecting Up to the even-numbered bit line and the odd-numbered bit line, so that the memory cell strings are precharged; by sensing the state of the memory cell string connected to the even bit line To verify whether the memory 1310561 cell string connected to the even bit line is programmed; and by sensing the state of the memory cell string connected to the odd bit line to verify whether the programmatic connection is made to The odd-numbered bit line is a string of billions of cells. The patent further describes a method for verifying a flash memory device, wherein the flash memory device includes a first transistor for supplying a verification signal to an even bit line and an odd bit line. The memory-cell array is responsive to a first control signal; a second transistor is configured to connect the memory cell array and an I-th node via the even bit line and the odd bit line to respond to a first a second control signal; a third transistor for supplying a current to the first node in response to a third control signal; a latch for storing output data from a selection unit of the memory cell array And a fourth transistor for controlling the state of the latch according to a voltage level of the first node and a fourth control signal. The method includes: respectively discharging a memory cell string connected to the even bit line and the odd bit line to discharge a first control signal; simultaneously supplying a voltage to the first node to respond to the third Controlling a signal, and simultaneously supplying a voltage of the first node to a memory cell string® respectively connected to the even bit line and the odd bit line to respond to a second control signal of the first voltage level, thereby pre- Charging the memory cell strings; verifying whether the memory cell string connected to the even bit line has been erased in response to the state of the memory cell string connected to the even bit line a second control signal of a voltage level; and responsive to storing a state of the memory cell string connected to the odd bit line to verify whether the cell line connected to the odd bit line has been erased in response a second control signal of the third voltage level. The first control signal can be maintained at a voltage level 1310561 of 丨.6 to 5.5V or a supply voltage Vcc. The second control signal of the first voltage level can be maintained at a voltage level of 1.0 to 5·5 ν or a power supply voltage Vcc, so that the second control signal of the second voltage level can be maintained at a voltage level of 1.0 to 2.2V. And the second voltage level can be maintained at a voltage level that is the same as or lower than the first voltage level. ^ The application time of the second control signal of the second voltage level can be set to be longer than the application time of the second control signal of the third voltage level. φ [Embodiment] Various embodiments of the present invention will now be described with reference to the accompanying drawings. Since various embodiments are provided to enable a person skilled in the art to understand the present invention, the embodiments and the scope of the patents are not limited to the various embodiments described hereinafter. 1 is a circuit diagram of a page buffer used in a method of verifying a NAND flash memory device in accordance with an embodiment of the present invention. A circuit diagram of the main register in a page buffer of a dual φ register structure having a main register and a cache register is shown in FIG. Referring to Fig. 1, a one-bit line selection unit 120 includes a plurality of electro-crystal bodies. Driving the first and second NMOS transistors N 1 0 1 and N 1 02 to respectively return 'even and odd discharge signals DISCHe and DISCHo, and thus applying a verify voltage VIRPWR to a memory cell array 1 1〇 Memory cell string The memory cell array 110 is connected to an even bit line BLe or an odd bit line BL 〇. Driving the third and fourth N Μ 0 S transistors N 1 0 3 and Ν 104 to respectively respond to the even and odd bit line selection signals BSLe and BSLo, and then, connecting one bit line of the element array 11 至 to one Sense 1310561 measured node s〇. A PMOS transistor P101 is driven in response to a precharge signal PRECHb and thus a voltage is applied to the sense node S. - The fifth NMOS transistor N105 is coupled to the sense node SO and one of the output nodes QAb of a latch 130 in response to a writeback signal C0PYBACK at the time of a write stylization. The latch 130 temporarily stores the output data output by the memory cell array 110 and the externally supplied data. A sixth NM0S transistor N106 is driven according to a voltage level of the sensing node SO. A seventh NM0S transistor N107 is driven in response to a read signal READ-L and thus an output node QAb of the latch 130 and a ground terminal Vss. An eighth NM0S transistor N108 is driven in response to a signal DI_L&; thus a 1/ terminal YA and an output node QAb of the latch 130 are connected. A ninth NM0S transistor N109 is driven in response to a signal nDI_L and thus the I/O terminal YA and one of the input nodes QA of the latch 130. A tenth NM0S transistor N110 is driven in response to a reset signal RESET_L and thus the latch 130 is reset. An eleventh NM0S transistor N1 1 1 is driven to respond to a signal PR 〇 GRAM_L during a stylized operation and thereby transmit the desired program information to a selected bit line. A twelfth NM0S transistor N1 12 is driven in response to a signal PBD0_L and thus a voltage level of a stylized node NA. Further, an inverter 1101 reverses the voltage level of the output node QAb of the latch 130 and transmits a reverse voltage level to the stylized node NA. 2 is a diagram showing operational waveforms of a page buffer for a method of verifying a NAND flash memory device in accordance with an embodiment of the present invention. -10- 1310561 An erase verification method for a NAND flash memory device in accordance with an embodiment of the present invention will be described with reference to FIGS. 1 and 2. 1) Period A: Discharge simultaneously applies even and odd discharge signals DISCHe and DISCHo of a high level of 1.6 to 5.5 V or a supply voltage Vcc for the same period to turn on the first and second NMOS transistors N101 and N102 . Thus, the voltage levels of the verify signal VIRPWR are supplied to the bit lines BLe and BLo via the first and second NMOS transistors N101 and N102. The verify signal VIRPWR maintains a voltage level of 0V during erase verify. Thus, the even and odd bit lines BLe and BLo are supplied with a voltage of 0V. Further, the reset signal RES ET-L is supplied to a high level pulse to turn on the tenth NMOS transistor N110. Therefore, the node QA becomes a low level and the node QAb maintains a high level. As a result, the latch 130 is reset. At this time, a voltage of 0 to 1 V is supplied to all of the word lines WL0 to WL3 1, and a voltage of 0 V is also supplied to the drain selection line DSL and the source selection line SSL. 2) Period B: Precharge When the even and odd discharge signals DISCHe and DISCHo of the low level are applied, the first and second NMOS transistors N101 and N102 are turned off. Furthermore, since the low level of the precharge signal PRECHb is applied, the first PMOS transistor P101 is turned on. Thus, the supply voltage Vcc is applied to the sense node SO to maintain the sense node SO at a high level. Further, the even and odd bit line selection signals BSLe and BSLo are applied to a voltage level of 1. 至 to 5.5 V or a first voltage VI of the power supply voltage Vcc. Therefore, the first voltage VI and a voltage (VI-Vth) are respectively applied to the even and Ι31〇561 odd bit lines BLe and BLo, wherein the first voltage VI is subtracted from the third or fourth NMOS transistor N103 Or the threshold voltage Vt of N104. In this case, a voltage is applied to the drain select line DSL. 3) Period C: Evaluation When the even and odd bit line selection signals BSLe and 'BSLo of the low level are applied, the third and fourth NMOS transistors N103 and N104 are turned off. Thus, the power supply to the even and odd bit lines BLe and BLo is stopped, and the even and odd bit lines are controlled according to the states of the memory φ body cells respectively connected to the even and odd bit lines BLe and BLo. The voltage level of BLe and BLo. That is, if the memory cell is not in an erased state, the voltage level of the even or odd bit line BLe or BLo is maintained at the voltage level of V1-Vt. However, if the memory cell is in an erased state, the voltage level of the even or odd bit line BLe or BLo is gradually reduced from Vl - Vt and then maintained at a low level. At this time, since the first PMOS transistor P101 is kept turned on by the low level precharge signal PRECHb, the sense node SO maintains a high level. At the same time, a high level ^ signal is applied via a drain select line DSL and a source select line SSL. Set the unit evaluation period to maintain 1〇μ3 or less. 4) Period D: Even cell sensing The first PMOS transistor P201 is turned off when the precharge signal PRECHb is applied to a high level. When the second voltage V2 is applied (the second voltage V2 maintains a voltage level of about 1 〇 to 2.2 V) to the even bit line selection signal BSLe, the third NMOS transistor N103 is turned on. If the memory cell is not a eraser unit, the voltage level of the even bit line BLe is maintained at V; the voltage level of l - Vt is maintained and the voltage level of the sense node SO is maintained at -12 - 1310561 To a high level. If the memory cell is in an erased state, the voltage level of the even bit line BLe is gradually reduced and then maintained at a low level, and the voltage level of the sensing node SO is maintained at a low level. In this state, if a high level pulse is applied to the read signal READ_L of 1. 0μ5, when the memory cell is not an erase unit, the sense node SO is kept at a high level. quasi. Then, the sixth NMOS transistor N106 is turned on and the seventh NMOS transistor N107 is turned on in response to the high pulse read signal READ_L. As a result, the point QAb is maintained at a low φ level and the node QA is maintained at a high level. Conversely, if the memory cell is the erase unit, the sense node SO is maintained at a low level and the seventh NMOS transistor N107 is turned off. Therefore, the node QA is maintained at a high level and the node QA is maintained at a low level. Thus, the voltage level of the node QA is detected to sense the state of the even cells. 5) Period E: Odd unit sensing When the even bit line selection signal BSLe of the low level is applied, the third NMOS transistor N103 is turned off. When the odd bit line selection signal BSLo which becomes a third voltage V3 (the third voltage V3 is maintained at a voltage level of about 1. 〇 to 2.2V) is applied, the fourth NMOS transistor N104 is turned on. The application time required for the third voltage V3 to be lower than or equal to the second voltage V2 and the third voltage V3 is shorter than the application time of the second voltage V2. If the memory cell is not a erase cell, the voltage level of the odd bit line BLo is maintained at a voltage level of V 1 -Vt and the voltage level of the sense node SO is maintained at a high level. However, if the memory cell is in an erased state, the voltage level of the odd bit line BLo is gradually reduced and then maintained at a low level of -13 - 1310561, and the voltage level of the sensing node so is Keeping it in a low state, in this state, the read signal READ_L is applied to a high level of 1.0 to ΙΟμΞ. If the memory cell is not the erase unit, the sense node SO remains at a high level. Then, the sixth transistor N106 is turned on and the seventh NMOS transistor N107 is turned on to return the pulse read signal READ_L. Since the node QAb is kept accurate, the node QA is kept at a certain level. Conversely, the cell is the erase unit, and the sense node S 0 is kept at a low level to close the seventh NMOS transistor N07. Therefore, the node QAb is kept at a high level and the node QA is kept at a low level. Thus, the voltage level of the QA is detected to sense the state of the odd cells. One of the erase verification methods of the NAND fast device according to an embodiment of the present invention has been described above. However, the method can be applied to a stylized verification method. Thus, the description of this method is omitted. As described above, the pre-charge and evaluation are followed by continuous even bit lines and odd bit lines. Thus, less than half of the verification time is erased compared to the prior art and the total amount can be reduced compared to the prior art. Therefore, the operating speed of a device can be improved. Furthermore, this method applies the same way to stylized verification. Therefore, it is also possible to reduce the stylization. While the above description has been made with reference to the various embodiments, the modifications and variations of the present invention can be implemented by those skilled in the art without departing from the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a verification standard in accordance with an embodiment of the present invention. In the pulse, the NM0S should be high and low. The memory is quasi-and closed. The node is flash memory. The same way, the detailed sensing can be subtracted. Understand the project
NAND -14- 1310561 快閃記憶體裝置之方法中所使用之一頁緩衝器的電路圖； 以及 第2圖係用以描述依據本發明之一實施例的一驗證一 NAND快閃記憶體裝置之方法的頁緩衝器之操作波形。 【主要元件符號說明】NAND-14-1310561 circuit diagram of a page buffer used in a method of flash memory device; and FIG. 2 is a diagram for describing a method of verifying a NAND flash memory device according to an embodiment of the present invention The operational waveform of the page buffer. [Main component symbol description]
1 10 記 憶 體胞元 陣 列 120 位 元 線選擇 單 元 130 閂 鎖 器 BLe 偶 數 位元線 BLo 奇 數 位元線 BSLe 偶 數 位元線 •ΪΒΒ m 擇 信 號 BSLo 奇 數 位元線 選 擇 信 號 COPYBACK 回 寫 信號 DI_L 信 Orfe Wu DISCHe 偶 數 放電信 號 DISCHo 奇 數 放電信 號 DSL 汲 極 選擇線 1101 反 向 器 N101 第 一 NM0S 電 晶 體 N102 第 二 NM0S 電 晶 體 N103 第 二 NM0S 電 晶 體 N 104 第 四 NM0S 電 晶 體 N 105 第 五 NM0S 電 晶 體 N 106 第 Γ - NM0S 電 晶 體 -15- 13105611 10 Memory cell array 120 Bit line selection unit 130 Latch BLe Even bit line BLo Odd bit line BSLe Even bit line • ΪΒΒ m Select signal BSLo Odd bit line select signal COPYBACK Write back signal DI_L Letter Orfe Wu DISCHe Even discharge signal DISCHo Odd discharge signal DSL Datum selection line 1101 Inverter N101 First NM0S transistor N102 Second NM0S transistor N103 Second NM0S transistor N 104 Fourth NM0S transistor N 105 Fifth NM0S Transistor N 106 Dijon - NM0S Transistor-15 - 1310561
N107 第七NMOS電晶體 N 108 第八NMOS電 曰 晶體 N109 第九NMOS電 晶體 N1 10 第十NMOS電晶體 N1 1 1 第十一 NMOS電晶體 N 1 1 2 第十二NMOS 電晶體 NA 程式化節點 nDI_L 信號 P101 PMOS電晶體 P201 第一 PMOS電 晶體 PRECHb 預充電信號 PROGRAM_L 信號 QA 輸入節點 QAb 輸出節點 READ_L 讀取信號 RESET_L 重置信號 SO 感測節點 SSL 源極選擇線 VI 第一電壓 V2 第二電壓 V3 第三電壓 V c c 電源電壓 VIRPWR 驗證電壓 Vss 接地端 -16- 1310561N107 seventh NMOS transistor N 108 eighth NMOS transistor crystal N109 ninth NMOS transistor N1 10 tenth NMOS transistor N1 1 1 eleventh NMOS transistor N 1 1 2 twelfth NMOS transistor NA stylized node nDI_L signal P101 PMOS transistor P201 first PMOS transistor PRECHb precharge signal PROGRAM_L signal QA input node QAb output node READ_L read signal RESET_L reset signal SO sense node SSL source select line VI first voltage V2 second voltage V3 Third voltage V cc Power supply voltage VIRPWR Verify voltage Vss Ground terminal -16- 1310561
Vt 臨界電壓 WL0-WL31 字元線Vt threshold voltage WL0-WL31 word line
YA I/O端YA I/O end