KR100224275B1 - Program verifying method of nand type nonvolatile semiconductor device - Google Patents

Abstract

The present invention relates to a NAND type nonvolatile semiconductor memory device, and more particularly, to a program verification method of a NAND type nonvolatile semiconductor memory device for sufficiently precharging bit lines of a sense amplifier stage to a ground voltage level during program verification. In addition, according to the present invention, the PiSAE signal, which is enabled only at the time of sensing and disabled at the time of precharging of the second bit lines, is also enabled in the form of a pulse at the time of precharging, and at the same time, the VSA voltage is set to 0 volts so that the second bit is set. A pass was formed that could discharge the lines to zero volts. This makes it possible to sufficiently precharge the second bit lines to zero volts. As a result, it is possible to prevent the threshold voltages of the NMOS transistors of the first sense amplification means from increasing. Therefore, it is possible not only to secure a sensing margin when verifying a program, but also to prevent a loss of a sensing speed.

Description

(A program verifing method of NAND type non volatile semiconductor memory device)

The present invention relates to a NAND type nonvolatile semiconductor memory device, and more particularly, to a program verification method of a NAND type nonvolatile semiconductor memory device for sufficiently precharging bit lines of a sense amplifier stage to a ground voltage level during program verification. .

1 is a block diagram showing the configuration of a NAND type nonvolatile semiconductor memory device.

In the NAND type nonvolatile semiconductor memory device shown in FIG. 1, the cell array 100, the separation means 200, the first sense amplification means 300, the second sense amplification means 400, and the precharge and equalization means ( 500). The cell array 100 is an area for storing data, and first bit lines SBL and SBLB are electrically connected to the cell array 10. The second bit lines LBL and LBLB corresponding to the first bit lines SBL and SBLB are selectively electrically insulated through the separation means 200. The separating means 200 electrically switches the first and second bit lines SBL, SBLB, LBL, and LBLB in response to the first and second separation control signals PiISOe and PiISOo applied from the outside. And NMOS transistors M1 and M2. The NMOS transistor M1 has a gate terminal connected to a signal line L1 to which the first separation control signal PIISOe is applied, and a channel is connected between the first bit line SBL and the second bit line LBL. . The NMOS transistor M2 has a gate connected to a signal line L2 to which the second separation control signal PIISOo is applied, and a channel is connected between the first bit line SBLB and the second bit line LBLB.

The first sense amplifier 300 senses and amplifies the voltages of the first bit lines SBL and SBLB first and transfers them to the corresponding second bit lines LBL and LBLB, respectively. That is, the first sense amplifier 300 corresponds to the voltages of the first bit lines SBL and SBLB in response to a sense enable control signal PiSAE and a driving voltage VSA. It is transferred to the second bit lines LBL and LBLB, and is made of NMOS transistors M3 to M6. Each of the NMOS transistors M3 and M4 is connected in series between the second bit line LBL and the signal line L4 to which the driving voltage VSA is applied, and the first bit line SBL and the sense in Gate terminals are respectively connected to the signal line L3 to which the enable control signal PiSAE is applied. Each of the NMOS transistors M5 and M6 is connected in series between the second bit line LBLB and the signal line L4 to which the driving voltage VSA is applied, and the first bit line SBLB and the sense are connected in series. Gates are respectively connected to the signal line L3 to which the enable control signal PiSAE is applied.

In addition, the second sense amplifier 400 serves to sense and amplify secondary voltages transferred to the second bit lines LBL and LBLB through the first sense amplifier 300. The second sense amplifier 400 includes latched NMOS transistors M7 and M8 and latched PMOS transistors M9 and M10. That is, the latched NMOS transistors M7 and M8 have gate terminals connected to the second bit line LBLB and the second bit line SBL, respectively, and each channel is serially connected between the second bit lines LBL and LBLB. It is connected. Each of the latched PMOS transistors M9 and M10 has a gate terminal connected to a second bit line LBLB and a second bit line LBL, and each channel is connected in series between the second bit lines LBLB and LBLB. have. If a 0 volt is transferred to the second bit line LBL and a power supply voltage Vcc is transferred to the second bit line LBLB, the seventh NMOS transistor M7 and the tenth PMOS transistor M10 are turned on, respectively. Predetermined driving voltages LA and LAB applied from the outside are transferred to the corresponding second bit lines LBL and LBLB through the transistors M7 and M10.

The precharge and equalization means 500 is a means for precharging and equalizing the second bit lines LBL and LBLB to a predetermined voltage level before sensing data stored in the cell array 10. . That is, the precharge PMOS transistors M11 and M12 enabled in response to a PiSAEQB signal applied from the outside to precharge the second bit lines LBL and LBLB to the ground voltage Vss during program verification. And an equalizing NMOS transistor M13 enabled in response to a PiSAEQ signal to equalize the precharged second bit lines LBL and LBLB. That is, when the PiSAEQB signal is applied at a low level, the precharge PMOS transistors M11 and M12 are turned on and the second bit lines LBL are driven by a driving voltage LA applied from the outside. , LBLB) is precharged. When the PiSAEQ signal is applied at a high level, the equalizing NMOS transistor M13 is turned on to equalize the precharged second bit lines LBL and LBLB.

2 is an operation timing diagram at the time of program verification according to the prior art. 1 to 2, a program verification operation according to the prior art will be described.

Subdividing the program verifying operation, first, the first bit lines SBL and SBLB and the second bit lines LBL and LBLB are respectively precharged to a predetermined voltage level. Although not shown in the drawing, the first bit lines SBL and SBLB are simultaneously precharged to a predetermined voltage level (eg, 1 / 2Vcc) through precharge and equalization means. The second bit lines LBL and LBLB are precharged to a predetermined voltage level through the precharge and equalization means 500 shown in FIG. 1. As shown in FIG. 2, the PiSAEQ signal transitions from a low level to a high level, and the PiSAEQB signal transitions from a high level to a low level. Accordingly, the precharge PMOS transistors M11 and M12 and the equalization NMOS transistor M13 of the precharge and equalization means 500 are turned on. At this time, a driving voltage LA of 0 volt is applied through the signal line L6 commonly connected to each terminal of the precharge PMOS transistors M11 and M12 (). LBL and LBLB are precharged to the threshold voltage Vtp level of the precharge PMOS transistor, and are equalized through the equalizing NMOS transistor M13.

The Vtp level precharged in the second bit lines LBL and LBLB continuously turns on the NMOS transistors M7 and M8 of the second sensing amplifier 400 to turn on the second bit lines. The voltage levels of (LBL, LBLB) are readjusted to the threshold voltage (Vtn) level of the NMOS transistor. Here, an on cell (era cell or erased cell) is included in the first bit line SBL among the first bit lines SBL and SBLB shown in FIG. 1, and a reference cell is included in the first bit line SBLB. Assume that each reference cell is selected. The reference cell refers to a cell designed to maintain an intermediate level of the amount of current flowing through the erased cell and the programmed cell during development.

Subsequently, when the predetermined word line is enabled, the first bit line SBL and the first bit line SBLB are developed at the levels of the on cell and the reference cell, respectively. In addition, the NMOS transistors M4 and M6 of the first sense amplifier 300 are turned on in response to a high level pulse signal, that is, a PiSAE signal. As a result, the amplification pressures of the first bit lines SBL and SBLB are amplified and transferred to the second bit lines LBL and LBLB precharged to the Vtn level. That is, since the voltage level of the first bit line SBLB in which the reference cell is selected is higher than the voltage level of the first bit line SBL in which the on cell is selected, among the NMOS transistors M3 and M5 of the first sensing amplifier 300. The NMOS transistor M5 is turned on. As a result, the driving voltage VSA of the power supply voltage Vcc level is supplied to the second bit line SBLB through the NMOS transistors M5 and M6 of the first sensing amplifier 300. In addition, the second bit line LBL is charged to zero volts so that the voltage difference between the second bit lines LBL and LBLB is amplified more. The voltage difference between the second bit lines LBL and LBLB is amplified by the second sensing by the second sense amplifier 400. That is, the second bit line LBL with the on cell selected is amplified to the power supply voltage Vcc, and the second bit line LBLB with the reference cell selected is amplified to 0 volts, respectively.

However, according to the program verification method as described above, the NMOS transistors of the second sense amplification means 400 without sufficiently lowering the voltage levels of the second bit lines LBL and LBLB at the time of bit line precharging. It is precharged to the threshold voltage Vtn level of (M7, M8). As a result, the source-body voltage difference of the NMOS transistors M3 and M5 of the first sense amplifier 300 increases. The voltage difference causes a body effect to increase the threshold voltages of the NMOS transistors M3 and M5. Through Equation 1 below, it can be seen that the threshold voltage of the transistor is increased by the body effect.

[Equation 1]

As shown in Equation 1, as the voltage difference V _SB of the source-bulk of the NMOS transistors M3 and M5 increases, the threshold voltage V _T also increases. As a result, as the threshold voltage increases, the amount of current flowing through the transistors M3 and M5 is limited. As a result, in sensing and amplifying the voltages of the first bit lines SBL and SBLB, not only the sensing margin is lowered, but also the loss of the sensing speed occurs.

Accordingly, an object of the present invention is to provide a program verification method of a NAND type nonvolatile semiconductor memory device for securing a sensing margin and preventing a loss of a sensing speed during program verification.

1 is a block diagram showing a configuration of a bit line sensing amplifier circuit of a NAND type nonvolatile semiconductor memory device;

2 is an operation timing diagram for program verification according to the prior art;

3 is an operation timing diagram for program verification according to a preferred embodiment of the present invention;

* Explanation of symbols on the main parts of the drawings

100: cell array 200: separation means

300: first detection amplification means 400: second detection amplification means

500: precharge and equalization means

According to one aspect of the present invention for achieving the above object, a cell array for storing data; First bit lines electrically connected to the cell array; Second bit lines respectively corresponding to the first bit lines; Separating means for selectively electrically insulating the first bit lines and the second bit lines in response to first and second separation control signals; Receiving a driving voltage of a predetermined level and voltages of the first bit lines, amplifying the voltages of the first bit lines in response to a sensing control signal applied from the outside, and transferring the amplified voltages to the corresponding second bit lines; 1 sensing amplification means; Second sense amplifying means for sensing and amplifying the voltages of the second bit lines; A program verification method of a NAND type nonvolatile semiconductor memory device comprising precharge and equalization means for precharging and equalizing the second bit lines to a predetermined voltage level in response to predetermined control signals. A first step of activating the first sense amplifying means and the precharge and equalization means to precharge the second bit lines to a ground voltage level; A second step of deactivating the first sense amplifying means; Developing a first bit line; A fourth step of allowing the first sense amplification means to be activated for a predetermined time so as to first sense and amplify the voltages of the developed first bit lines and transfer them to the corresponding second bit lines; And a fifth step of secondly sensing and amplifying voltages of the second bit lines transferred through the second sense amplifier.

In this embodiment, the first step is the control signal is applied to the ground voltage level, the control signal is applied to the power supply voltage level, the sensing control signal is applied as a pulse of a power supply voltage level having a predetermined width. The driving voltage may be applied at a ground voltage level.

By such a circuit, by sufficiently precharging the bit lines of the sense amplifier stage to the ground voltage level, it is possible to secure the sensing margin during program verification and to prevent the loss of the sensing speed.

Hereinafter, reference will be made in detail with reference to FIG. 3 according to an embodiment of the present invention.

Referring to FIG. 3, the novel program verification method of the present invention not only secures a sensing margin by precharging the bit lines LBL and LBLB of the sense amplifier stage to the ground voltage Vss, but also reduces the loss of the sensing speed. Verification method to prevent. In the conventional case, the bit lines LBL and LBLB of the sense amplifier stage are not sufficiently precharged to the ground voltage Vss, thereby causing a body effect on the NMOS transistors M3 and M5 of the first sense amplifier 300. As a result, its threshold voltage increased.

However, according to the program verifying method of the present invention, first, the bit lines LBL and LBLB of the sense amplifier stage are precharged as before. At the same time, the PiSAE signal applied to the NMOS transistors M4 and M6 of the first sensing amplifier 300 is enabled in the form of a pulse in the precharge period and the VSA voltage is applied to 0 volts. As a result, the bit lines LBL and LBLB of the sense amplifier stage can be sufficiently precharged to the ground voltage Vss. Therefore, it is possible to prevent the threshold voltage from increasing by reducing the voltage difference between the source and bulk of the NMOS transistors M3 and M5 of the first sensing amplification means 300. As a result, in addition to securing the sensing margin when verifying the program, it is possible to prevent the loss of the sensing speed.

3 is a timing diagram of an operation during program verification according to an exemplary embodiment of the present invention. Hereinafter, a program verifying operation according to the present invention will be described with reference to FIGS. 3 and 1.

Subdividing the program verifying operation, first, the first bit lines SBL and SBLB and the second bit lines LBL and LBLB are respectively precharged to a predetermined voltage level. Although not shown in the drawing, the first bit lines SBL and SBLB are simultaneously precharged to a predetermined voltage level (eg, 1 / 2Vcc) through precharge and equalization means. The second bit lines LBL and LBLB are precharged to a predetermined voltage level through the precharge and equalization means 500 shown in FIG. 1. As shown in FIG. 2, the PiSAEQ signal transitions from a low level to a high level, and the PiSAEQB signal transitions from a high level to a low level. Accordingly, the precharge PMOS transistors M11 and M12 and the equalization NMOS transistor M13 of the precharge and equalization means 500 are turned on. In this case, a driving voltage LA of 0 volt is applied through the signal line L6 commonly connected to each terminal of the precharge PMOS transistors M11 and M12 (.) Accordingly, the second bit lines LBL and LBLB are precharged to the threshold voltage Vtp level and equalized through the equalizing NMOS transistor M13.

The Vtp level precharged in the second bit lines LBL and LBLB continuously turns on the NMOS transistors M7 and M8 of the second sensing amplifier 400 to turn on the second bit lines. The voltage levels of (LBL, LBLB) are readjusted to the Vtn level. At the same time, as shown in FIG. 3, the PiSAE signal applied to the NMOS transistors M4 and M6 of the first sensing amplification means 300 is enabled with a pulse of the power supply voltage Vcc level and at the same time the VSA voltage. Is applied to 0 volts. This forms a pass through which the second bit lines LBL and LBLB can be discharged to a voltage level of zero volts. That is, during precharging, the NMOS transistors M4 and M6 of the first sense amplifier 300 are turned on to discharge the second bit lines LBL and LBLB to a voltage level of 0 volts.

Subsequently, assume that the first bit line SBL and the first bit line SBLB are developed at the level of the on cell and the reference cell, respectively, when the predetermined word line is enabled. The NMOS transistors M4 and M6 of the first sense amplifier 300 are turned on in response to a high level pulse signal, that is, a PiSAE signal. At this time, the VSA voltage is applied to the power supply voltage (Vcc) level. As a result, the voltages of the first bit lines SBL and SBLB are amplified and transferred to the second bit lines LBL and LBLB precharged to the ground voltage Vss level. That is, since the voltage level of the first bit line SBLB in which the reference cell is selected is higher than the voltage level of the first bit line SBL in which the on cell is selected, the NMOS transistors M3 and M5 of the first sensing amplification means 300. The NMOS transistor M5 is turned on.

As a result, the VSA voltage of the power supply voltage Vcc level is supplied to the second bit line SBLB through the NMOS transistors M5 and M6 of the first sense amplifier 300. In addition, the second bit line LBL is charged to zero volts so that the voltage difference between the second bit lines LBL and LBLB is amplified more. The voltage difference between the second bit lines LBL and LBLB is amplified by the second sensing by the second sense amplifier 400. That is, as shown in FIG. 3, the second bit line LBL in which the on cell is selected is amplified to a power supply voltage Vcc, and the second bit line LBLB in which the reference cell is selected is zero amplified, respectively.

As described above, the PiSAE signal, which is enabled only during sensing and disabled upon precharge of the second bitlines, is also enabled in pulse form during precharge, and at the same time, the VSA voltage is set to 0 volts to designate the second bitlines. A pass capable of being discharged with zero volts was formed. This makes it possible to sufficiently precharge the second bit lines to zero volts. As a result, it is possible to prevent the threshold voltages of the NMOS transistors of the first sense amplification means from increasing. Therefore, it is possible not only to secure a sensing margin when verifying a program, but also to prevent a loss of a sensing speed.

Claims (2)

A cell array 100 for storing data; First bit lines SBL and SBLB electrically connected to the cell array 100; Second bit lines LBL and LBLB respectively corresponding to the first bit lines SBL and SBLB; Separation means for selectively electrically insulating the first bit lines SBL and the second bit lines LBL and LBLB in response to first and second separation control signals PiISOe and PiISOo. 200); The first bit lines SBL and SBLB are received in response to a sensing control signal PiSAE received from an external device by receiving a driving voltage VSA having a predetermined level and voltages of the first bit lines SBL and SBLB. A first sense amplifying means (300) for amplifying the voltages of the amplifying circuits and amplifying the voltages of the amplifying voltages and transmitting the amplified voltages to the corresponding second bit lines (LBL, LBLB); Second sense amplification means (400) for sensing and amplifying voltages of the second bit lines (LBL, LBLB); NAND type including precharge and equalization means 500 for precharging and equalizing the second bit lines LBL and LBLB to a predetermined voltage level in response to predetermined control signals PiSAEQB and PiSAEQ. In the program verification method of the nonvolatile semiconductor memory device, A first step of activating the first sense amplifying means (300) and the precharge and equalization means (500) to precharge the second bit lines (LBL, LBLB) to a ground voltage (Vss) level; A second step of deactivating the first sense amplifying means (300); Developing a third bit line (SBL, SBLB); The first sense amplification means 300 is activated for a predetermined time so as to first sense and amplify voltages of the developed first bit lines SBL and SBLB to correspond to the second bit lines LBL. , LBLB) to convey it; And a fifth step of secondly detecting and amplifying voltages of the second bit lines LBL and LBLB transferred through the second sensing amplification means 300. Program verification method. The method of claim 1, In the first step, the control signal PiSAEQB is applied at the ground voltage Vss level, the control signal PiSAEQ is applied at the power supply voltage Vcc level, and the sensing control signal PiSAE has a predetermined width. A method of verifying a program of a NAND type nonvolatile semiconductor memory device, wherein the driving voltage VSA is applied at a ground voltage Vss level.