KR20080102037A - Verifying method for multi-level cell nand flash memory device and post programming method using the same - Google Patents

Abstract

A verifying method for a multi-level cell NAND flash memory device is provided to drastically reduce a time to be required to an erase operation by narrowing a threshold voltage distribution width of a memory cell. A verifying method for a multi-level cell NAND flash memory device comprises the following steps: a step for pre-charging an even bit line and an odd bit line to a fixed voltage(620); a step for sharing data among the even bit line and odd bit line(630); a step for sensing whether a programmed memory cell exists in a cell string connected to the even bit line and odd bit line or not(640); and a step for supplying a pre-charge voltage to a common source line(CSL) in which the even bit line and odd bit line are connected.

Description

Verifying method for Multi-Level Cell NAND flash memory device and post programming method using the same}

1 is a diagram illustrating threshold voltage distributions of program and erase states of a single level cell NAND flash memory device.

FIG. 2 is a diagram illustrating a threshold voltage distribution of a 2 (bit) multi-level cell NAND flash memory device.

3 is a cell string and page buffer structure shown for explaining a verification method of a NAND flash memory device according to the present invention.

4 is a flowchart illustrating a post program process of a NAND flash memory device according to the present invention.

5 is a flowchart illustrating a post program verification step of the NAND flash memory device according to the present invention.

6 is a timing diagram illustrating a post program verification step of a NAND flash memory device according to the present invention.

The present invention relates to a method of driving a flash memory device, and more particularly, to a verification method and a post program method of a multi-level cell NAND flash memory device.

The flash memory device is a nonvolatile memory device that can be electrically programmed and erased, and is used in portable home appliances such as MP3 players, digital cameras, camcorders, notebook computers, PDAs, and cellular phones. It is widely used in portable electronics, computer BIOS, printer, and USB drive.

Among flash memory devices, NAND flash memory devices are particularly advantageous for high integration because a plurality of memory cells are connected in series to form a single string, and their use as a data storage medium continues to increase. To increase storage capacity at smaller chip sizes, a multi-level cell (hereinafter referred to as "MLC") that selectively stores more than two bits of data in one memory cell is referred to. A structure has been proposed. MLC differs from Single Level Cell (SLC) in which one memory cell has two states of program / erase, and has two bits and three bits with one memory cell. And because it can represent more than four bits of data, it can achieve twice as much memory capacity as SLC.

FIG. 1 illustrates threshold voltage distributions of program and erase states of a flash memory device having an SLC structure, and FIG. 2 illustrates threshold voltage distributions of a flash memory device having a 2 (bit) MLC structure.

Memory cells of the NAND flash memory device are in an erased state or a programmed state. As shown in FIG. 1, memory cells in an erased state have a threshold voltage distribution 110 that is relatively low, such as less than 0V. On the other hand, memory cells in the programmed state have a threshold voltage distribution 120 that is relatively high, for example, higher than 0V.

Compared to SLC, in the case of MLC, for example, 2 (bit), as shown in FIG. 2, the threshold voltage distribution 210 of the erased state and the threshold voltage distributions 221, 222 of the plurality of programmed states, 223). The erased threshold voltage distribution 210 and the programmed threshold voltage distributions 221, 222, and 223 are distinguished by the first read voltage Vread0 (generally 0V). The threshold voltage distributions 221, 222, and 223 of the programmed state are distinguished by the second read voltage Vread1 and the third read voltage Vread2, respectively. As described above, in the multi-level cell NAND flash memory device, the threshold voltage distributions 221, 222, and 223 of the programmed state are mutually intersected between the first read voltage Vread0 (or the erase voltage) and the pass voltage Vpass. Since they must be spaced apart, the width of the threshold voltage distributions should be as narrow as possible. This is because there is a limit to increasing the pass voltage (Vpass). In case of MLC, not only the threshold voltage of the program state but also the threshold voltage distribution of the erase state should be controlled to be narrowly formed.

The most commonly used method of erasing NAND flash memory devices having an MLC structure is performed in the order of a pre-program, a normal erase, and a post program.

Among these, the post program is a soft program performed after the normal erase operation and before the various program states, and is performed to narrow the widened threshold voltage distribution after the erase operation. The post program is performed in an Incremental Step Pulse Program (ISPP) method. Unlike a typical ISPP method, a post program is performed in block units. That is, a program bias is applied to all word lines of one block at the same time to program to a desired level. In addition, low program pulses and step voltages are used to change the threshold voltage of the memory cells due to the post program operation.

In the post program process, a verify pulse is performed after application of a program pulse. Unlike the general program verification operation in which the operation is terminated only when all memory cells exceed the verification level, only one verification step is performed in the post program phase. The post program operation is terminated even if the cell exceeds the verification level. Unlike the erase operation in the SLC structure, the overall erase operation time is increased because the MLC structure needs to perform a post program process.

Meanwhile, NAND flash memory devices share the same page buffer with the even bit line and the odd bit line. The post program operation of the MLC flash memory device is divided into even pages and odd pages. That is, after the program verify operation is performed on the memory page of the even page, the program operation is performed on the memory cell of the odd page, and the post program operation is terminated when even one memory cell exceeds the verification level. Therefore, the post program time is long, and thus the time required for the entire erasing operation is long.

When the erase verification is performed on the even bit line and the odd bit line at the same time in order to reduce the time taken for the erase operation of the flash memory device having the MLC structure, both bit lines must not be discharged to exceed the erase verify level. The memory cell is recognized as a memory cell to terminate the erase operation. Therefore, the erase operation time is reduced compared to the method of separately verifying the even bit line and the odd bit line, but since the memory cells exceed the erase verify level, the data retention margin is reduced or doubled. This results in appearing.

SUMMARY OF THE INVENTION The present invention provides a method of verifying a NAND flash memory device capable of simultaneously performing verification of an even bit line and an odd bit line, thereby preventing data retention margins from being reduced or failure and reducing verification time. There is.

Another technical problem to be achieved by the present invention is to perform a post program verification on an even bit line and an odd bit line at the same time, thereby preventing a data retention margin from being reduced or an erase failure, and reducing a verification time. Is to provide a post program method.

According to an aspect of the present invention, there is provided a method of verifying a NAND flash memory device, the method comprising: precharging an even bit line and an odd bit line to a predetermined voltage for program or erase verification; Sharing data between the even bit line and the odd bit line; And detecting whether a programmed memory cell exists in a cell string connected to the even bit line and the odd bit line according to a data sharing result between the even bit line and the odd bit line.

In the precharging the even bit line and the odd bit line, a precharge voltage may be applied to a common source line CSL connected to the even bit line and the odd bit line.

Prior to precharging the even bit line and the odd bit line, the even bit line and the odd bit line may be discharged and the sensing output Q node of the page buffer may be set.

In the step of sharing data between the even bit line and the odd bit line, the even bit line selection transistor and the odd bit line selection transistor of the page buffer to which the even bit line and the odd bit line are connected are simultaneously turned on. Can be.

It is preferable to determine that a memory cell having passed the verification level exists in the even bit line or the odd bit line only when the state of the sensing output Q node of the page buffer is changed.

In accordance with another aspect of the present invention, a post program method of a NAND flash memory device includes a program pulse in an erased memory cell including a plurality of even bit lines and a plurality of odd bit lines. Programming by applying; Performing program verification on the even bit line and the odd bit line simultaneously; And completing the program when the cell passing the program verifying step exists in the even bit line or the odd bit line.

Performing program verification on the even bit line and the odd bit line simultaneously includes discharging the even bit line and the odd bit line, initializing a sense output (Q) node of a page buffer, and performing the even bit. Pre-charging a line and an odd bit line to a predetermined voltage, sharing data between the even bit line and the odd bit line, and according to a result of data sharing between the even bit line and the odd bit line, the even And detecting whether a programmed memory cell exists in a cell string connected to the bit line and the odd bit line.

In the precharging the even bit line and the odd bit line, a precharge voltage may be applied to a common source line CSL connected to the even bit line and the odd bit line.

In the sharing of data between the even bit line and the odd bit line, the even bit line selection transistor and the odd bit line selection transistor of the page buffer may be turned on at the same time.

Only when the state of the sense output Q node of the latch circuit is changed, it is preferable to determine that the memory cell having passed the verification level exists in the even bit line or the odd bit line.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

3 is a diagram illustrating a structure of a cell string and a page buffer in order to explain a method of erasing a flash memory device according to the present invention.

In the NAND flash memory device, a memory cell array, which is a data storage area, includes a plurality of cell strings 310 and 320 connected to corresponding bit lines BLe and BLo, respectively. Although only two cell strings are shown in the drawing, a plurality of the cell strings are disposed in the memory cell array. Although only three memory cell transistors are shown in each cell string in the drawing, 32 or more memory cell transistors may be disposed in one cell string.

Each cell string 310/320 may include a drain select transistor 311/321 connected to a corresponding bit line BLe / BLo, a source select transistor 312/322 connected to a common source line CSL, And a plurality of memory cell transistors 313, 314, 315, 323, 324, and 325 disposed in series between the drain select transistors 311/321 and the source select transistors 312/322. The even bit line BLe and the odd bit line BLO are connected to one page buffer.

The page buffer includes a bit line selection and bias circuit 410, a precharge circuit 420, and a register circuit 430.

The bit line selection and bias circuit 410 selects one of the even bit line BLe and the odd bit line BLO, and simultaneously presets the selected bit line among the even bit line BLe and the odd bit line BLO. Preset bias is applied. The bit line selection and bias circuit 410 consists of four nMOS transistors M01, M02, M11, and M12. The nMOS transistor M01 is controlled by the DISCHe control signal, the nMOS transistor M02 is controlled by the DISCHo control signal, the nMOS transistor M11 is controlled by the BSLe control signal, and the nMOS transistor M12 is controlled by BSLo. Controlled by signal.

The precharge circuit 420 precharges the selected bit line to a voltage having a predetermined size, and includes one pMOS transistor M30. The pMOS transistor M30 is disposed between the precharge voltage Vpre and the sensing node SO, and is controlled by the PRECH control signal.

The register circuit 430 latches and stores the sensed data. The register circuit 430 includes a latch formed of nMOS transistors M40, M50, M60, and M70 and two inverters IN0 and IN1. Although only one register circuit 430 is shown in the figure, for example, a 2-bit MLC includes a main register circuit for latching and storing MSB data, and a cache register circuit for latching and storing LSB data, respectively. .

4 is a flowchart of a post program process in an erase method of a flash memory device according to the present invention.

Referring to FIG. 4, when a post program is started during an erase operation, a program voltage of one pulse is applied to word lines of all memory cells in a selected block (step 510). At this time, about 10-20V is applied as a program voltage. Next, the program state of the memory cells in the block is verified. The verification operation is simultaneously performed on the memory cells of the even page and the odd page (step 520). In the related art, since the verification is first performed on the even or odd page, and then the verification operation is performed on the remaining odd or even pages, the time required for the entire erase operation is long. In the present invention, since the post program verification operation is performed on the even and odd pages at the same time, the time required for the entire erase operation can be greatly reduced. The post program verification step 520 of the present invention, which simultaneously validates even and odd pages, will be described in detail below.

It is determined whether the memory cell has passed or failed the post program verification step (step 530). In this case, unlike the verification of the normal program operation, when one memory cell of the selected memory cells exceeds the verification level, the post program operation is completed. If none of the cells have passed the verification level, the program voltage increased by the predetermined step voltage Vstep is applied again to program the ISPP method.

5 is a flowchart illustrating a post program verification step in the erase method of the flash memory device according to the present invention, and FIG. 6 is a timing diagram of the post program verification step.

Referring to the cell string and page buffer structure of FIG. 3, the flowchart of FIG. 5, and the timing diagram of FIG. 6, first, all charges remaining in the bit line are discharged to perform a post program verification operation. Set the buffer (step 610, t1).

In order to discharge the bit line, a high signal of 0.1 to 5 V is applied to the control signals DISCHe and DISCHo. Accordingly, the nMOS transistors M01 and M02 are turned on, and the power supply line VIRPWR is grounded (0V), or a low voltage of 1V or less is applied. Since the nMOS transistors M01 and M02 are turned on, charges occupied in the even bit line BLe and the odd bit line BLO are all pulled out through the nMOS transistors M01 and M02 to the power supply line VIRPWR. As a result, both the even bit line BLe and the odd bit line BLO are discharged. To set the Q node of the register circuit 430 high, changing the PRECH control signal low causes the precharge transistor M30 to turn on so that the SO node is charged to the preset voltage Vpre, When the DI transistor M50 is turned on, the Q node is set high. The preset voltage for precharging the SO node is about 0.1-5V. A voltage of 0V is applied to the word lines of all memory cells in the block.

Next, the bit line is precharged for data sensing (steps 620 and t2).

In order to precharge the bit line, a precharge bias of about 0.1 to 5 V is applied to the common source line CSL, and a high signal is applied to the source select line SSL to turn on the source select transistor. Then, charge is transferred from the common source line to the bit line through the cell string. Since the verification voltage of 0V is applied to the word lines of all memory cells, if any memory cell in the string has a threshold voltage exceeding the verification level, that is, if there is a memory cell whose threshold voltage is higher than 0V, the memory cell transistor Since the bit line is turned off, the bit line including the memory cell is not precharged to maintain the ground state. On the other hand, if no memory cell has a threshold voltage exceeding the verification level, all the memory cell transistors are turned on, so that the voltage of the bit line rises to the precharge level.

Next, in order to simultaneously verify the even bit line and the odd bit line, sharing of data is performed between the even bit line and the odd bit line (steps 630 and t3).

Selecting the even bit line selection transistor M11 and the odd bit line by simultaneously applying a high signal of about 0.1 to 5 V to the two bit line selection signals BSLe and BSLo connected to the even bit line and the odd bit line. The transistor M12 is turned on at the same time. In the normal read or verify operation, since the even page and the odd page are read or verified separately, one of the bit line select transistors M11 and M12 is turned on and the other is turned off to the even bit line. One of the bit lines and the odd bit line is selected. However, in the present invention, both bit line transistors M11 and M12 are simultaneously turned on to verify the even page and the odd page at the same time. The common source line CSL control signal, the drain select line DSL control signal, and the source select line SSL control signal are turned low.

Since both bit line select transistors M11 and M12 are turned on, data sharing, that is, charge distribution, occurs between the two bit lines depending on whether the bit lines are precharged. If one of the memory cells connected to the even bit line and the odd bit line also has not exceeded the verify level (0V), since the even bit line and the odd bit line are both precharged in the precharge step (step 620), two bits are used. No charge distribution occurs between the lines and the SEN node remains in the precharge state (Vpre).

On the other hand, if both the even bit line and the odd bit line have exceeded the verify level, that is, if there are memory cells exceeding the verify level in the even bit line and the odd bit line, respectively, the two bit lines are pre-charged (step 620). Since all are not precharged and are in the ground state, the SEN node remains in the ground state.

If only one bit line of the even bit line or the odd bit line has exceeded the verify level, that is, if there is a memory cell exceeding the verify level in one of the two bit lines, the precharge step (step 620). In this case, since one bit line is precharged and the other bit line is grounded, charge distribution occurs between the two bit lines. As a result, the SEN node maintains a voltage level (1 / 2Vpre) of about half of the precharge level.

Next, the transistors constituting the page buffer and the latch are properly controlled to sense the state of the memory cell and latch the sensed data (steps 640 and t3).

In the state where the SO node is precharged, a high signal of about 0.1 to 5 V is applied as the SEN signal to turn on the sensing transistor M20, and the precharge signal PRE is changed to low to precharge the transistor. Turn off M30).

If the SEN node is at the precharge level, since the sensing transistor M20 is turned off, the SO node maintains the precharge level, and the READ transistor M40 is turned on. When the nDI transistor M70 is turned on in this state, since the charge of the Q node is discharged through the nDI transistor M70 and the READ transistor M40, the Q node is changed from high to low.

If charge distribution occurs at the SEN node and is lower than half of the precharge level, charge distribution occurs between the SO node and the SEN node, causing the SO node to be lower than the precharge level, and the READ transistor M40 is turned off. do. In this state, even when the nDI transistor M70 is turned on, the read READ transistor M40 is turned off, so that the Q node of the latch circuit maintains high data.

Next, recovery of the bit lines BLe and BLo is performed, and the sensed data is stored in all latches in the page buffer (step 650).

As a result, the next post-program pulse is applied to the memory cells that have not exceeded the verify level due to the low data of the Q node, and when the memory level exceeds the verify level of a single memory cell, the data of the Q node becomes high. Because of the state, the post program, that is, the erase operation is terminated.

The method for simultaneously verifying the even page and the odd page can be usefully applied not only to the above-described post program step but also to the general erase verification step, thereby greatly reducing the erase time.

As described above, according to the data erasing method of a flash memory device according to the present invention, a program verifying step is performed in a post program step for narrowing a threshold voltage distribution width of a memory cell after erasing by simultaneously performing an even page and an odd page. The time required for the erase operation can be greatly reduced.

The present invention is not limited to the above embodiments, and various modifications can be made by those skilled in the art within the technical spirit of the present invention.

Claims (10)

Precharging the even bit line and the odd bit line to a predetermined voltage for program or erase verification; Sharing data between the even bit line and the odd bit line; And And detecting whether a programmed memory cell is present in a cell string connected to the even bit line and the odd bit line, according to a result of data sharing between the even bit line and the odd bit line. The method of claim 1, In the precharging the even bit line and the odd bit line, And applying a precharge voltage to a common source line (CSL) connected to the even bit line and the odd bit line. The method of claim 1, Before the step of precharging the even bit line and the odd bit line, Discharging the even bit line and the odd bit line, and setting a sensing output (Q) node of a page buffer to a high or low level. . The method of claim 1, In the step of sharing data between the even bit line and the odd bit line, simultaneously turning on the even bit line selection transistor and the odd bit line selection transistor of the page buffer to which the even bit line and the odd bit line are connected. And a method of verifying a NAND flash memory device. The method according to claim 1 and 2, Only when the sense output (Q) node of the page buffer is changed to low or high, it is determined that the memory cell having passed the verification level exists in the even bit line or the odd bit line. A method of verifying a NAND flash memory device. Programming by applying a program pulse to one block of erased memory cells including a plurality of even bit lines and a plurality of odd bit lines; Performing program verification on the even bit line and the odd bit line simultaneously; And And completing a program when the cell having passed the program verifying step exists in the even bit line or the odd bit line. The method of claim 6, Simultaneously performing program verification on the even and odd bit lines, Discharging the even bit line and the odd bit line, and initializing a sense output (Q) node of a page buffer; Precharging the even bit line and the odd bit line to a predetermined voltage; Sharing data between the even bit line and the odd bit line, and And detecting whether a programmed memory cell exists in a cell string connected to the even bit line and the odd bit line according to a data sharing result between the even bit line and the odd bit line. Post program method of the device. The method of claim 7, wherein In the precharging the even bit line and the odd bit line, And applying a precharge voltage to a common source line (CSL) connected to the even bit line and the odd bit line. The method of claim 7, wherein In the sharing of data between the even bit line and the odd bit line, the even bit line selection transistor and the odd bit line selection transistor of the page buffer are simultaneously turned on. The method of claim 7, wherein A post program of a NAND flash memory device, characterized in that it is determined that a memory cell having passed the verification level exists in the even bit line or the odd bit line only when the state of the sensing output Q node of the page buffer is changed. Way.

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