JP2009043322A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase a storage capacity while securing reliability and performance. <P>SOLUTION: A memory part has a plurality of memory cells in which a plurality of kinds of data can be stored and an internal voltage generation circuit which generates internal voltage for accessing the memory cells. A memory controller controls reading and writing of data from and to the memory part. The memory controller has a function of properly reading the internal voltage generated by the internal voltage generation circuit of the memory part. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device.

  NAND flash memory is known as one of electrically rewritable nonvolatile semiconductor memories (EEPROM). The NAND flash memory has a smaller unit cell area than the NOR type and can easily be increased in capacity. The read / write speed per cell is slower than that of the NOR type, but by increasing the cell range (physical page length) in which reading / writing is simultaneously performed between the cell array and the page buffer, In particular, high-speed reading / writing is possible.

  Taking advantage of these features, NAND flash memories are used as various recording media including file memories and memory cards.

  In a memory card or the like, a nonvolatile memory and a memory controller are packaged, and reading / writing of the nonvolatile memory is controlled by a command and a logical address supplied from a host. For example, it has been proposed to read data of a plurality of sectors by giving a logical address and the number of sectors from a host (see Patent Document 1).

On the other hand, in the conventional NAND flash memory, in order to increase the storage capacity, multi-value data such as 4-value or 8-value is stored in one memory cell by increasing the number of identifiable threshold distributions per memory cell. Things have been done. However, there has been a problem that reliability and performance that can be guaranteed are lowered due to multi-value and miniaturization.
JP 2006-155335 A

  An object of the present invention is to provide a semiconductor memory device having an internal potential automatic adjustment function in order to ensure reliability and performance.

  A nonvolatile semiconductor memory device according to an aspect of the present invention includes a memory unit including a plurality of memory cells capable of storing a plurality of types of data, and an internal voltage generation circuit that generates an internal voltage for accessing the memory cells; A memory controller that controls reading and writing of data to and from the memory unit, and the memory controller has a function of appropriately reading an internal voltage generated by an internal voltage generation circuit of the memory unit.

  According to the present invention, it is possible to improve reliability and performance.

  Embodiments of the present invention will be described below with reference to the drawings.

[Configuration of semiconductor memory]
FIG. 1 is a block diagram showing a semiconductor memory according to the present embodiment.

  The semiconductor memory of this embodiment constitutes a memory module integrally packaged by, for example, one or a plurality of NAND flash memories 21 and a memory controller 22 that controls reading / writing. Since all the mounted flash memories 21 are controlled as a logical memory by a single memory controller 22, this is hereinafter referred to as a logical block address NAND flash memory (hereinafter abbreviated as an LBA-NAND memory). That's it.

  The NAND flash memory 21 mounted on the LBA-NAND memory 20 is composed of one or a plurality of memory chips. In FIG. 1, two memory chips chip 1 and chip 2 are shown, but in this case as well, they are controlled by one memory controller 22. The maximum number of memory chips is determined by the current capacity of the regulator and other factors.

  The memory controller 22 includes a NAND flash interface 23 for transferring data to and from the flash memory 21, a host interface 25 for transferring data to and from the host device, and a buffer RAM 26 for temporarily storing read / write data and the like. This is a one-chip controller having a hardware sequencer 27 that is used for MPU 24 that performs data transfer control, firmware / FW sequence control of firmware (FW) in the NAND flash memory 21, and the like.

  Whether the NAND flash memory 21 and the memory controller 22 are one chip or different chips is not essential for the LBA-NAND memory 20.

  FIG. 2 is a functional block diagram of the NAND flash memory 21 in the LBA-NAND memory 20. The NAND flash memory 21 includes a memory cell array 1 and a sense amplifier circuit 3 that performs data write and read operations on the memory cell array 1. Data exchange between the sense amplifier circuit 3 and the external input / output terminal I / O is performed via the data bus 10 and the I / O buffer 8.

  Various control signals (chip enable signal / CE, address latch enable signal ALE, command latch enable signal CLE, write enable signal / WE, read enable signal / RE, etc.) are input to the internal controller 5 from the memory controller 22. . The internal controller 5 identifies the address “Add” and the command “Com” supplied from the input / output terminal I / O based on these control signals, and the address is sent to the row decoder 2 and the column decoder via the address register 6. 7 and the command is decoded internally. Further, the internal controller 5 stores the internal Ready / Busy state in the status register 4 so that the Ready / Busy signals RY / BY can be referred to from the outside. The row decoder 2 selects a word line WL of the memory cell array 1 according to the row address, and the column decoder 7 selects a data latch SDC (to be described later) of the sense amplifier circuit 3 according to the column address.

  The internal controller 5 performs data read control, data write and erase sequence control according to the control signal and command. An internal voltage generation circuit 9 is provided to generate an internal voltage (an internal voltage boosted from the power supply voltage) necessary for each operation mode. The internal voltage generation circuit 9 performs a boosting operation for generating a necessary voltage based on the set value set in the parameter register 11 by the internal controller 5.

  FIG. 3 shows the configuration of the memory cell array 1 in the memory core portion of the NAND flash memory 21.

  The memory cell array 1 is configured by arranging NAND cell units (NAND strings) NU in which a plurality of electrically rewritable nonvolatile memory cells (32 memory cells in the illustrated example) M0 to M31 are connected in series. .

  One end of the NAND cell unit NU is connected to the bit lines BLo and BLe via the selection gate transistor S1, and the other end is connected to the common source line CELSRC via the selection gate transistor S2. Control gates of memory cells M0-M31 are connected to word lines WL0-WL31, respectively, and gates of select gate transistors S1, S2 are connected to select gate lines SGD, SGS.

  A set of NAND cell units arranged in the word line direction constitutes a block serving as a minimum unit of data erasure, and a plurality of blocks BLK0 to BLKn-1 are arranged in the bit line direction as shown in the figure.

  A sense amplifier circuit 3 for reading and writing cell data is arranged on one end side of the bit lines BLe and BLo, and a row decoder 2 for selecting and driving a word line and a selection gate line is arranged on one end side of the word line. . The figure shows a case where adjacent even-numbered bit lines BLe and odd-numbered bit lines BLo are selectively connected to each sense amplifier SA of the sense amplifier circuit 3 by a bit line selection circuit. In this case, the unselected bit line BL is grounded to prevent capacitive coupling between adjacent bit lines. In addition to such a configuration, an ABL (All Bit Line) type sense amplifier SA may be provided for each bit line BL.

  FIG. 4 shows a configuration example of the sense amplifier SA. The sense amplifier SA is a single-ended voltage detection type sense amplifier, and the sense node Nsen is connected to the bit line BL via a clamp NMOS transistor Q1. The clamping NMOS transistor Q1 clamps the bit line voltage and functions as a pre-sense amplifier. A precharge NMOS transistor Q2 for precharging the bit line is also connected to the sense node Nsen.

  A charge holding capacitor C is connected to the sense node Nsen, and this constitutes a data storage circuit TDC that temporarily holds sense data.

  The sense node Nsen is connected to a data latch PDC which is a main data storage circuit via a transfer NMOS transistor Q3. The sense node Nsen is also connected via a transfer NMOS transistor Q4 to a data latch SDC serving as a data storage circuit used for data exchange with the outside. Therefore, the data latch SDC is connected to the data lines DL and DLn via the column selection gates Q8 and Q9 driven by the column selection signal CSL.

  A dynamic data storage circuit DDC is provided between the data node N1 of the data latch PDC and the sense node Nsen for temporarily holding write data and writing back the write data in the next cycle. The gate N3 of the NMOS transistor Q6 is its storage node, and a transfer NMOS transistor Q5 is disposed between this gate and the data node N1 of the data latch PDC. An NMOS transistor Q7 is arranged to write back desired data to the sense node Nsen according to the data of the storage node N3.

  A verify check circuit VCH is provided to monitor the data node N1n of the data latch PDC and perform a verify determination. The verify check circuit VCH includes a detection NMOS transistor Q10 whose gate is connected to the data node N1n, an NMOS transistor Q11 for selectively grounding and activating the source thereof, and a drain of the NMOS transistor Q10 as a signal line COM. NMOS transistors Q13 and Q14 for transfer gates connected to.

  The signal line COM is a common signal line provided in common to the sense amplifiers SA for one page, and a precharge circuit (not shown) is set in advance to set the signal line COM to the “H” level state. The verify check circuit VCH detects whether or not the precharged signal line COM is discharged based on the verify read data of the data latch PDC.

  The data latch PDC becomes “1” (N1 = “H”) when writing is completed at the time of write verification. Therefore, when the writing of one page is completed, the data latch PDC for one page is all “1”. The verify check circuit VCH discharges the signal line COM on the basis of N1n = “H” when there is a portion where writing is insufficient. When the writing is completed, the signal line COM is not discharged. Therefore, the controller can control the write sequence by monitoring the signal line COM.

  The sense amplifier SA in FIG. 4 is an example configured to be applicable to both a binary data storage system and a quaternary data storage system. In the case of the binary data storage system, the data latch SDC is not necessary on the principle of operation, but in the case of the quaternary storage system, this data latch SDC is indispensable.

  That is, in the quaternary data storage system, it is necessary to read out and refer to the lower page data already written in the memory cell array for the upper page write verification. Therefore, write verification is performed by holding write data in the data latch PDC and holding lower page data read from the cell array in the data latch SDC.

  In the LBA-NAND memory 20 configured as described above, commands, addresses (logical addresses or physical addresses) and data, a chip enable signal / CE, a write enable signal / WE, a read enable signal / RE, and a ready / busy signal External control signals such as RY / BY are input to the host I / F 25. In the host I / F 25, commands and control signals are distributed to the MPU 24 and the hardware sequencer 27, and addresses and data are stored in the buffer RAM 26.

  A logical address input from the outside is converted into a physical address of the NAND flash memory 21 by the NAND flash I / F 23. Further, under the control of the hardware sequencer 27 based on various control signals, data transfer control and write / erase / read sequence control are executed. The converted physical address is transferred to the row decoder 2 and the column decoder 7 via the address register 6 in the NAND flash memory 21. Write data is loaded into the sense amplifier circuit 3 via the I / O buffer 8, and read data is output to the outside via the I / O buffer 8.

[Memory area]
FIG. 5 is a diagram showing details of the memory area of the LBA-NAND memory according to this embodiment.

  The LBA-NAND memory 20 of the present embodiment has a plurality of data areas (logical block access areas) whose access can be switched by a command. Specifically, in this embodiment, there are two or three data storage areas that are divided according to use and data reliability.

  The standard operation mode shown in FIG. 5A has two data storage areas each storing information having different characteristics. One is a binary data storage area SDA (SLC Data Area) using SLC (Single Level Cell), and the other is a multi-value data storage area MDA (MLC Data Area) using MLC (Multi Level Cell). It is. The binary data storage area SDA is suitable for storing log data of a file system or network communication, and the multi-value data storage area MDA is suitable for storing music, images, various applications, and the like.

  In the optional power-on mode shown in FIG. 5B, in addition to the two data storage areas SDA and MDA that store information having different characteristics, a boot code block that stores a boot code is provided at the head of the memory area.

  In these two modes, the boundary between the binary data storage area SDA and the multi-value data storage area MDA can be arbitrarily changed by an instruction of a command. For example, in a memory having a memory capacity of 4 GB when using a memory cell array that can also use MLC (4 values) as SLC (2 values) and using the entire memory area as MLC, as shown in FIG. When the storage capacity of the value data storage area SDA is set to 0 MB, 50 MB, 500 MB, and 1 GB, the storage capacity of the multi-value data storage area MDA is 4 GB, 3.9 GB, 3 GB, and 2 GB, respectively.

  FIG. 7 is a timing chart for setting up the binary data storage area SDA.

Here, CLE is a command latch enable, / CE is a chip enable, / WE is a write enable, ALE is an address latch enable, / RE is a read enable, and RY // BY is a ready / busy control signal. Read SDA command “00h” is read at the command input timing, and then set SDA command “A5h” and allocation units 1 ^st , 2 ^nd , 3 ^rd , 4 ^th are sequentially input in five cycles of the address latch. . The allocation unit specifies the boundary position of the binary data storage area SDA as shown in FIG. 8, for example. As a result, since the boundary area between the SDA and the MDA is set in the memory controller 22, the subsequent logical address / physical address conversion processing is executed based on the set boundary area.

  FIG. 9 is a timing chart for checking the size of the binary data storage area SDA.

  The read SDA command “00h” is read at the command input timing, and then the get SDA unit command “B5h” and 4-byte dummy data are sequentially input in five cycles of the address latch. As a result, the boundary area of the SDA is read from the controller 22.

  FIG. 10 is a timing chart for checking the size of the multi-value data storage area MDA.

  The read SDA command “00h” is read at the command input timing, and then the get MDA unit command “B0h” and 4-byte dummy data are sequentially input in five cycles of the address latch. As a result, the boundary area of the MDA is read from the controller 22.

[Access to binary data storage area]
Next, a procedure for accessing the binary data storage area SDA will be described.

  First, data erasure is executed in units of blocks. Inside the NAND flash memory 21, all word lines in the selected block are set to 0V, and an erase voltage Vera of about 20V is applied to the p-type well in which the memory cell array is formed. As a result, the memory cells in the selected block are released from the floating gate electrons, and are in an erased state (data “1”) having a negative threshold voltage. Actually, in order to prevent the occurrence of an overerased state, an erase sequence is used in which the erase voltage application and the erase verify for confirming the erased state are repeated.

  When a binary data write command is input, the binary data is written to the designated address area of the binary data storage area SDA. Writing is performed in units of pages. Here, one page is composed of an odd page connected to odd-numbered bit lines and an even page connected to even-numbered bit lines among all memory cells arranged along one word line as described above. Is done. For example, when the bit line selection signal SELe in FIG. 3 is activated, writing to even pages is possible, and writing to odd pages of the bit line selection signal SELo is possible, and the data of the sensor amplifier SA corresponding to these is possible. Write data for one page is loaded into the latch PDC.

  Next, the cell channel immediately below the selected word line in the data storage area of the binary data storage area SDA has Vss (in the case of “0” write), Vdd (in accordance with the write data held by the data latch PDC of the sense amplifier SA. “1” is written, that is, when writing is prohibited). The NAND cell channel to which “1” is written becomes a floating state of Vdd by the precharge operation.

  Thereafter, a write voltage Vpgm of about 20 V is applied to the selected word line, and a write pass voltage Vpass which is an intermediate voltage is applied to the unselected word lines. As a result, in the cell to which “0” data is given, electrons are injected into the floating gate, and in the cell to which “1” data is given, the potential of the floating channel rises due to capacitive coupling from the control gate, and the electrons Injection does not occur. In this way, one page can be written simultaneously.

  In the case of data writing, in order to obtain a desired threshold distribution, application of a write voltage and write verify read are repeated. The write voltage Vpgm is stepped up with the write cycle. The verify read is a check read operation in which a verify voltage Vv corresponding to the lower limit value of the “0” data threshold distribution is applied to the selected word line. Thus, it is determined whether or not the “0” write cell has been sufficiently written.

  For the write verification, the write data held by the data latch PDC is once transferred to the data storage circuit DDC and held, and a write-back operation for determining the write data of the next cycle is performed according to the verification result. Is called. Although detailed description of the operation is omitted, control is performed so that the data latches PDC of the sense amplifiers for the lower page are all “1” when writing of the lower page is completed by the above-described write verify operation. By detecting this by the verify check circuit VCK, it is possible to determine the completion of writing.

  Data reading is performed in units of one page as in writing. A read pass voltage Vread is applied to the non-selected word line, a read voltage Vr (eg, Vss) is applied to the selected word line, and a selection voltage Vsg (eg, Vread) is applied to the drain side select gate line SGD.

  The clamping transistor Q1 and the precharging transistor Q2 are turned on to precharge all the bit lines. For example, assuming that the gate voltage of the clamping transistor Q1 is VBL + Vt (Vt is the threshold voltage of the NMOS transistor), the bit line is precharged to VBL.

  After sequentially turning off the clamping transistor Q1 and the precharging transistor Q2, the selection voltage Vsg is applied to the source side selection gate line SGS. As a result, the bit line is discharged according to whether the selected cell is on (“1” data) or off (“0” data).

  After a certain bit line discharge operation, when the sense voltage Vsen + Vt is applied to the gate of the clamping transistor Q1, the bit line data “1” and “0” are sensed as “L” and “H” data of the sense node Nsen. Is done.

[Access to quaternary data storage area]
In the case of quaternary data access, quaternary data “xy” defined by upper page data “x” and lower page data “y” is used. First, the lower page is written into the erased memory cell. That is, as shown in the upper part of FIG. 11, by writing lower page data “0” to cell data “11” in the erased state, a threshold distribution of data “10” is obtained.

  The internal operation of the NAND flash memory 21 related to the lower page write is the same as the binary data write operation to the binary data storage area SDA, and therefore detailed description thereof is omitted. When the writing of the lower page data to the multi-value data storage area MDA is completed, the upper page data is subsequently written.

  When the upper page is written, for example, four data threshold distributions as shown in the lower part of FIG. 11 are obtained. In this example, quaternary data “xy” defined by upper page data “x” and lower page data “y” is “11”, “10”, “00”, “01” in order of threshold voltages. "".

  For data “11” and “10” whose upper bits are “1”, the threshold distribution of lower page data “1” and “0” is used as it is. Therefore, the upper page write is an operation of changing the data “11” state to the data “01” state and the data “10” state to the data “00” state by writing “0”. At the time of writing the upper page, a desired threshold distribution can be obtained by sequentially performing write verification using verify voltages Vv2 and Vv3 corresponding to the threshold distribution lower limit values of data “00” and “01”.

  In the upper page write, it is necessary to sequentially perform the write verify of the data “00” and “01” using different verify voltages Vv2 and Vv3 as described above. In particular, when verifying the data “00”, the data “01” It is necessary to remove "" from the verification target. For this purpose, lower page data already written in the memory cell array is read and referenced. Therefore, while the write data is held in the data latch PDC and the upper page write is performed, the lower page data is held in the data latch SDC, and the above-described verify control is performed with reference to this.

For data reading, upper page reading and lower page reading are performed in the same manner as the binary data storage method. Upper page reading is performed by applying a read voltage Vr1 set between threshold distributions of data “10” and “00” to the selected word line. For the lower page read, the read using the read voltage Vr0 set between the threshold distributions of the data “11” and “10” and the threshold distributions of the data “00” and “01” are performed. Reading using the set read voltage Vr2 is necessary.
[Adjustment of internal voltage]
Although the physical configuration of the memory cell array 1 does not change between the binary data storage area SDA and the multi-value data storage area MDA, the required data writing accuracy is higher than that of the binary data storage area SDA. The binary data storage area SDA has higher data reliability and performance than the multi-value data storage area MDA. Since NAND devices are required to have high performance and high reliability in this way, the optimal internal voltage (gate voltage and substrate voltage at the time of data writing, data reading, erasing, etc.) suitable for cell characteristics is finely adjusted. It is desirable to do. However, in the parameter register 11 for determining the internal voltage, only one type of parameter determined at the time of shipment of the NAND chip is set, and the internal voltage is not adjusted and used after the shipment. In addition, the internal voltages of these data storage areas are not normally output to external pins, and there is a problem that it is impossible to grasp how much value is set without special measurement.

  Therefore, in this embodiment, every time a read or write command is input, an operation of reading the internal voltage generated by the internal voltage generation circuit 9 to the outside of the NAND flash memory 21 and adjusting the internal voltage to an appropriate internal voltage is performed. Performed by the controller 22.

  FIG. 12 is a flowchart showing an example in which such internal voltage control is executed using the test mode of the NAND flash memory 21.

  When a read or write command is input from the outside (S1), the memory controller 22 inputs a test mode command to the NAND flash memory 21 (S2), and reads an internal voltage from the NAND flash memory 21 (S3). That is, in the NAND flash memory 21, since the parameter for determining the internal voltage is stored in the parameter register 11, the parameter stored in the parameter register 11 is read or generated by the internal voltage generation circuit 9 by other means. The internal voltage thus read is read out of the memory 21. The memory controller 22 receives the internal voltage, and calculates a parameter for obtaining an appropriate internal voltage based on the difference between the internal voltage suitable for the access area stored inside and the read internal voltage (S4). . Then, an internal voltage change command of the NAND flash memory 21 is input to the NAND flash memory 21 using a test mode command (S5). As a result, the contents of the parameter register 11 are changed inside the NAND flash memory 21, and the internal voltage generated by the internal voltage generation circuit 9 is changed (S6). When the internal voltage reaches the set voltage, this is notified to the memory controller 22 (S7). Subsequently, a read or write command is input to the NAND flash memory 21 (S8), and a read or write operation is executed (S9). When reading or writing is completed, this is notified to the memory controller 22 (S10), and further to an external user (S11).

According to this embodiment, every time a read or write command is input from the outside, the memory controller 22 sets the internal voltage to an optimum value, so there is no need to perform special command input or control on the user side.
[Other Embodiments]
In the above-described embodiment, the operation of reading and adjusting the internal voltage is performed each time a read or write command is input. For example, when the access to the binary data storage area SDA and the access to the multi-value data storage area MDA are switched. Only the reading and adjustment of the internal voltage may be performed.

  Note that the present invention can also be applied to the case of performing LM (Lower Middle Mode) writing as shown in FIG. This LM writing can suppress the influence of the Yupin effect between adjacent cells because the amount of movement of the threshold distribution can be suppressed smaller than the writing of the previous embodiment when writing the upper page. There is an advantage that you can. Even in such writing, it is possible to access the internal voltage appropriately and finely automatically.

  In addition, when storing multi-value data such as 8-value and 16-value, not only four values, an internal voltage suitable for the cell characteristics of the data storage area to be accessed when accessing each data storage area By setting to, the effect of the present invention can be obtained.

  In the above embodiment, the NAND type is used as the flash memory, but a NOR type other type of memory may be used.

1 is a diagram showing a configuration of an LBA-NAND memory system according to an embodiment of the present invention. It is a figure which shows the structure of the NAND flash memory of the same LBA-NAND memory. It is a figure which shows the memory cell array structure of the same LBA-NAND memory. It is a figure which shows the structure of the sense amplifier of the same LBA-NAND memory. It is a figure which shows the data storage area of the LBA-NAND memory. It is a figure which shows the example of the various data storage amount of the LBA-NAND memory. It is a timing chart which shows the setup procedure of the binary data storage area SDA of the LBA-NAND memory. It is a figure which shows the example of a data storage area setting of the LBA-NAND memory. It is a timing chart which shows the binary data storage area confirmation procedure of the LBA-NAND memory. It is a timing chart which shows the multi-value data storage area confirmation procedure of the LBA-NAND memory. It is a figure which shows an example of the threshold value distribution after the lower page write and upper page write of the LBA-NAND memory. It is a flowchart which shows the flow of the internal voltage control at the time of reading of the LBA-NAND memory or a good command input. It is a figure which shows an example of the threshold value distribution after the lower page write of the LBA-NAND memory based on further another embodiment of this invention, and an upper page write.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Row decoder, 3 ... Sense amplifier circuit, 5 ... Internal controller, 6 ... Address register, 7 ... Column decoder, 8 ... I / O buffer, 9 ... Internal voltage generation circuit, 20 ... LBA-NAND Memory, 21 ... NAND flash memory, 22 ... Memory controller, 23 ... NAND flash interface, 24 ... MPU, 25 ... Host interface, 26 ... Buffer RAM, 27 ... Hardware sequencer.

Claims (5)

A memory unit having a plurality of memory cells capable of storing a plurality of types of data, and an internal voltage generating circuit for generating an internal voltage for accessing the memory cells;
A memory controller for controlling reading and writing of data to and from the memory unit,
The non-volatile semiconductor memory device, wherein the memory controller has a function of appropriately reading an internal voltage generated by an internal voltage generation circuit of the memory unit. The nonvolatile semiconductor memory device according to claim 1, wherein the memory controller adjusts the internal voltage based on the read internal voltage. The nonvolatile semiconductor memory device according to claim 2, wherein the memory controller reads the internal voltage and adjusts the internal voltage every time the memory unit is accessed. 4. The nonvolatile semiconductor memory according to claim 2, wherein the memory controller executes reading of an internal voltage from the memory unit and adjustment of the internal voltage by inputting a test mode command to the memory unit. 5. apparatus. The memory unit includes a binary data storage area for storing binary data having a single data identification threshold value and a multi-value data storage area for storing a plurality of multi-value data having a data identification threshold value The nonvolatile semiconductor memory device according to claim 1, wherein:

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