KR20130072517A - Non-volatile memory device and erase method thereof - Google Patents

Abstract

PURPOSE: A non-volatile memory device, and an erasing method thereof are provided to set the test voltage of soft program operation depending on the memory cell group, thereby improving a disturb phenomenon. CONSTITUTION: A memory cell block comprises even memory cells and odd memory cells. A page buffer (120) is connected to an even bit line and an odd bit line, and soft program-tests the even memory cells and odd memory cells. A voltage supply unit (130) selectively applies test voltages to multiple word lines which are connected with the even memory cells and odd memory cells mutually. A controlling unit (140) controls the page buffer and the voltage supply unit to successively progress the soft program operation of even memory cells and odd memory cells. [Reference numerals] (110) Memory cell array; (120) Page buffer unit; (130) Voltage supply unit; (140) Controlling unit; (AA) BL (BLe and BLo)

Description

Non-volatile memory device and erase method thereof

The present invention relates to a nonvolatile memory device and an erase method thereof, and more particularly, to a nonvolatile memory device and an erase method thereof capable of improving an erase distortion phenomenon.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function that rewrites data at regular intervals. In addition, research on high integration technology of memory devices has been actively conducted to develop large capacity memory devices capable of storing a large amount of data.

The memory cell block of the NAND flash memory device, in which a plurality of memory cells are connected in series to form a single string for high integration of the memory device, includes a plurality of string structures. Each string structure includes a source select transistor, a drain select transistor, and a plurality of memory cells connected in series between the source select transistor and the drain select transistor.

Before performing a program operation for storing data in a memory cell of the nonvolatile memory device, data of all memory cells of the corresponding block must be erased. The erase operation floats the drain select line and the source select line, applies 0V to all word lines, and then erases the high voltage on the substrate (e.g., bulk containing at least one of p well and n well). Is applied. When an erase voltage is applied to the substrate, data of all memory cells of the block are erased, and the threshold voltages of the cells also drop below 0V. In this case, if the erase operation is excessively performed according to the characteristics of the memory cells, the threshold voltage is lower than the desired cell threshold voltage. As a result, an excessively erased cell may not be properly programmed in a subsequent program operation. To solve this problem, a soft program is performed on cells that are excessively erased to correct the threshold voltage.

In the nonvolatile memory device described above, a memory cell connected to the even and odd bit lines of a memory cell block may have a threshold voltage shift due to an interference phenomenon during a soft program operation of adjacent memory cells. do. In addition, an erase disturb phenomenon occurs in memory cells according to an arrangement position. The erase disturb phenomenon may occur depending on the location of the memory cells, which causes the FN (Fowler-Nordheim) disturbance phenomenon of the memory cells adjacent to the source select transistor among the memory cells, and the HCI (Hot) memory cell adjacent to the drain select transistor. There is a problem that a carrier injection disturbance phenomenon occurs.

An embodiment of the present invention provides a nonvolatile memory device and an erase method thereof that can improve an erase disturb phenomenon in an erase operation.

A nonvolatile memory device according to an embodiment of the present invention includes a memory cell block including even memory cells connected to an even bit line and odd memory cells connected to an odd bit line, and connected to the even bit line and an odd bit line. A page buffer for soft program verifying the even memory cells and the odd memory cells, a voltage providing unit for selectively applying verify voltages to a plurality of word lines commonly connected to the even memory cells and the odd memory cells, and In the soft program operation after the memory cell block is erased, a controller for controlling the voltage providing unit and the page buffer to sequentially perform the soft program operation of the even memory cells and the soft program operation of the odd memory cell. Include.

According to an embodiment of the present disclosure, an erase method of a nonvolatile memory device may include applying an erase voltage to a memory cell block including even and odd memory cells to erase the even and odd memory cells, the even memory cells, and Performing a first soft program operation to increase the threshold voltages of the odd memory cells by a set voltage, performing a second soft program operation so that the even memory cells have a threshold voltage value lower than a target threshold voltage; And performing a third soft program operation to cause the odd memory cells to have the target threshold voltage value.

A method of erasing a nonvolatile memory device according to another exemplary embodiment of the inventive concept is erased in a memory cell block including memory cells defined by a first memory cell group adjacent to a source select transistor and a second memory cell group adjacent to a drain select line. Applying a voltage to erase the memory cells, and setting a first verify voltage corresponding to the first memory cell group and a second memory cell group, and a second verify voltage having a different voltage level from the first verify voltage. And soft programming a threshold voltage of the even and odd memory cells included in the first memory cell group to be lower than the first verify voltage, and the even and odd included in the second memory cell group. And soft programming a threshold voltage of the memory cells to be lower than the second verify voltage.

According to the present technology, after the erase operation, the even memory cells have a lower threshold voltage than the odd memory cells during the soft program operation, and the threshold voltage of the even memory cells increases during the soft program operation of the odd memory cells. Thus, the threshold voltage distribution of the memory cells is improved.

In addition, the erase disturb phenomenon may be improved by differently setting the verification voltage of the soft program operation for each memory cell group.

1 is a configuration diagram of a nonvolatile memory device according to the present invention.
2 is a circuit diagram illustrating a memory cell block and a page buffer.
3 is a flowchart illustrating a method of erasing a nonvolatile memory device according to a first embodiment of the present invention.
4 is a threshold voltage distribution diagram illustrating a method of erasing a nonvolatile memory device according to an embodiment of the present invention.
5 is a flowchart illustrating a method of erasing a nonvolatile memory device according to a second embodiment of the present invention.
6 is a flowchart illustrating a method of erasing a nonvolatile memory device according to a third embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

1 is a block diagram of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 1, the nonvolatile memory device 100 includes a memory cell block 110, a page buffer unit 120, a voltage providing unit 130, and a controller 160.

The memory cell block 110 includes a plurality of memory cells in which data may be stored. The plurality of memory cells are connected to the plurality of word lines WL <n: 0> and the plurality of bit lines BL. In this case, memory cells connected to the same bit line are defined as one string, and memory cells connected to the same word line are defined as even and odd pages. In this case, an even page defines a memory cell connected to even bit lines among memory cells connected to the same word line, and an odd page defines a memory cell connected to odd bit lines among memory cells connected to the same word line.

The page buffer unit 120 includes a plurality of page buffers connected to the plurality of bit lines BL (BLe and BLo) of the memory cell block 110. Each of the plurality of page buffers performs an erase verify operation and a soft program verify operation in response to the page buffer control signals PB_SIGNALS. Detailed operation of the page buffer during the erase verify operation and the soft program verify operation will be described later.

Each of the plurality of page buffers may perform a program operation in response to the page buffer control signals PB_SIGNALS, but a detailed description thereof will be omitted.

The voltage provider 130 generates operating voltages (eg, erase verify voltage, soft program voltage, soft program verify voltage, pass voltage, etc.) necessary for each operation in response to the voltage provider control signals PM_SIGNALS. The generated operating voltages are selectively applied to the plurality of word lines WL <n: 0> of the memory cell block 110.

The controller 140 controls the voltage provider control signals PM_SIGNALS and the page buffer for controlling the voltage supply unit during the erase operation, the erase verify operation, the soft program operation, and the soft program verify operation in response to an externally input command. Generate page buffer control signals PB_SIGNALS.

Detailed operations of the above-described components will be described in the method of erasing the nonvolatile memory device according to the first to third embodiments described later.

FIG. 2 is a circuit diagram illustrating one page buffer among the memory cell block and the page buffer unit shown in FIG. 1.

Referring to FIG. 2, the memory cell block 110 includes a plurality of memory cells MC0e to MCne and an odd bit line BLo and a source line connected in series between an even bit line BLe and a source line SL. It includes a plurality of memory cells (MCoo to MCno) connected in series between the (SL). Although only one bit line pair BLe and Blo is shown in the drawing, it is preferable that a plurality of bit line pairs are arranged.

One page buffer PB is connected to one bit line pair BLe and Blo. The page buffer PB includes a bit line selector 121, a precharge unit 122, and a sensing unit 123. The bit line selector 121 connects the even or odd bit line with the sensing node SO in response to the sensing signal PBSENSE and the even bit line selection signal SelBLe or the odd bit line selection signal SelBLo. The precharge unit 122 precharges the even or odd bit line selected through the sensing node SO to a predetermined potential. In this case, the potential level that is pre- autonomous may be controlled according to the potential level of the sensing signal PBSENSE. The sensing unit 123 senses a potential of an even or odd bit line connected to the sensing node SO during the erase verification or soft program verification operation, and generates verification data indicating a pass or fail of the verification operation.

The sensing signal PBSENSE, the even bit line selection signal SelBLe, and the odd bit line selection signal SelBLo are signals generated by the control unit of FIG. 1, and although not shown, the precharge unit 122 and the sensing unit 123. Are also generated by the controller of FIG. 1.

3 is a flowchart illustrating a method of erasing a nonvolatile memory device according to a first embodiment of the present invention.

4 is a threshold voltage distribution diagram illustrating a method of erasing a nonvolatile memory device according to an embodiment of the present invention.

1 to 4, a method of erasing a nonvolatile memory device according to a first embodiment of the present invention will be described below.

1) Erase operation (S110)

The drain select line DSL and the source select line SSL of the memory cell block 110 are floated, and an erase voltage is applied to the P-well of the memory cell block 110 to perform an erase operation.

2) erase verification (S120)

An erase verify operation is performed by sensing threshold voltages of the memory cells of the memory cell block 110 using the page buffer PB. The erase verify operation checks whether all memory cells of the memory cell block 110 are erased to have a threshold voltage less than or equal to the erase threshold voltage ev. In an erase verify operation, if a memory cell has a threshold voltage higher than the erase threshold voltage ev, it is determined as a fail, and if all memory cells have a threshold voltage less than the erase threshold voltage ev, a pass is determined.

3) erase voltage increase (S130)

When it is determined that the result of the erase verification (S120) is a fail, the erase voltage is increased by the step voltage and re-executed from the above-described erase operation (S110).

The memory cells are erased so that the memory cells have a threshold voltage distribution as shown in FIG. 4A by the ISPE (Incremental Step Pulse Erase) method which repeats the above-described steps S110 to S130.

4) the first soft program (S140)

A first soft program operation is performed on all memory cells including even memory cells and odd memory cells of the memory cell block 110. Even memory cells are memory cells connected to an even bit line, and odd memory cells are memory cells connected to an odd bit line. The first soft program operation may proceed sequentially in word line order. In this case, the first soft program operation may use an incremental step pulse program (ISPP) method, but the verification operation for the first soft program operation may be skipped. In addition, the first soft program operation is performed by applying a program pulse to the memory cell block 110 by a predetermined number of pulses applied (for example, three times).

The first soft program operation is performed to increase the threshold voltages of the even and odd memory cells to a predetermined level to reduce the execution time of the second soft program and the third soft program operation.

The above-described first soft program operation can be skipped.

5) Second soft program for even memory cell (S150)

The second soft program operation is performed on the even memory cell. The second soft program operation is performed by applying a soft program voltage to a word line connected to the selected memory cell among the memory cells MC0e to MCne connected to the even bit line BLe. The second soft program operation is performed by applying a program prohibition voltage (eg, a power supply voltage) to the odd bit lines, and applying a program allowance voltage (eg, 0V) to the even bit lines.

6) Soft Program Verification (S160)

In the soft program verify operation, the first verify voltage PV1 is applied to a selected word line among the memory cell blocks, and a pass voltage is applied to the remaining word lines, and then the potential of the even bit line BLe is changed through the page buffer PB. This is done by sensing.

The controller 140 controls the potential level of the soft program verify voltage generated by the voltage provider 130 to apply the first verify voltage PV1 to the selected word line.

As a result of the soft program verification, even if one of the even memory cells connected to the selected word line has a threshold voltage higher than the first verify voltage PV1, the memory device determines that the pass is determined as a pass. If it is lower than PV1), it is regarded as a fail.

In this case, the first verification voltage PV1 may be set to be lower than the target threshold voltage to be programmed last.

7) Soft program voltage increase (S170)

If it is determined that the soft program verification (S160) is a result of failing, the soft program voltage is increased by the step voltage, and the second soft program S150 for the even memory cell is repeated.

The even memory cells are soft programmed to have the threshold voltage distribution as shown in B of FIG. 4 by using the ISPP method which repeats the above steps S150 to S170.

8) Third soft program for the odd memory cell (S180)

The third soft program operation is performed on the odd memory cell. The third soft program operation is performed by applying a soft program voltage to a word line connected to the selected memory cell among the memory cells MC0o to MCno connected to the odd bit line BLo. The third soft program operation is performed by applying a program prohibition voltage (eg, a power supply voltage) to the even bit lines, and applying a program allowance voltage (eg, 0V) to the odd bit lines.

In the third soft program operation on the odd memory cells, even memory cells adjacent to the odd memory cells are increased due to the interference effect, so that the threshold voltage distribution of B increases as the threshold voltage distribution of C as shown in FIG. 4. Done.

9) Soft program verification (S190)

In the soft program verify operation, the second verify voltage PV2 is applied to a selected word line among the memory cell blocks and a pass voltage is applied to the remaining word lines, and then the potential of the odd bit line BLo is changed through the page buffer PB. This is done by sensing.

The controller 140 controls the potential level of the verify voltage generated by the voltage provider 130 to apply the second verify voltage PV2 to the selected word line. The second verify voltage PV2 is preferably a target threshold voltage to be programmed last.

As a result of the soft program verification, if any one of the odd memory cells connected to the selected word line has a threshold voltage higher than the second verify voltage PV2, it is determined as a pass, and the threshold voltages of all the memory cells are determined as the second verify voltage ( If it is lower than PV2), it is regarded as a fail. If it is determined that the soft program verifies as a pass, the erase operation of the nonvolatile memory device is terminated.

10) Soft program voltage increase (S200)

When it is determined that the soft program verification (S190) is a result of failing, the soft program voltage is increased by the step voltage and re-executed from the third soft program S180 for the odd memory cell.

The odd memory cells are soft programmed so that the odd memory cells have a threshold voltage distribution equal to C of 4 by using the ISPP method which repeats the above steps S180 to S200.

Although the present invention has described the second and third soft program operations for a selected word line of a memory cell block including a plurality of word lines, the next word after the second and third soft program operations for one word line is completed. It is desirable to perform second and third soft program operations on the line.

According to an embodiment of the present invention, after soft programming the even memory cells to be lower than the target threshold voltage, the even and odd memory cells are uniformly distributed in voltage due to the interference effect during the soft program operation of the odd memory cells. Has

5 is a flowchart illustrating a method of erasing a nonvolatile memory device according to a second embodiment of the present invention.

A method of erasing a nonvolatile memory device according to a second exemplary embodiment of the present invention will now be described with reference to FIGS. 1 to 5.

1) Erase operation (S210)

The drain select line DSL and the source select line SSL of the memory cell block 110 are floated, and an erase voltage is applied to the P-well of the memory cell block 110 to perform an erase operation.

2) erase verification (S220)

An erase verify operation is performed by sensing threshold voltages of the memory cells of the memory cell block 110 using the page buffer PB. The erase verify operation checks whether all memory cells of the memory cell block 110 are erased to have a threshold voltage less than or equal to the erase threshold voltage ev. In an erase verify operation, if a memory cell has a threshold voltage higher than the erase threshold voltage ev, it is determined as a fail. If all memory cells have a threshold voltage less than the erase threshold voltage ev, a pass is determined.

3) erase voltage increase (S230)

When it is determined that the result of the erase verification (S220) is a fail, the erase voltage is increased by the step potential, and the erase operation (S210) is repeated.

The memory cell is erased to have the threshold voltage distribution as shown in FIG. 4A by the ISPE method of repeatedly performing the above-described steps S210 to S230.

4) Memory Cell Grouping (S240)

A plurality of memory cells connected to the plurality of word lines WL <n: 0> of the memory cell block 110 are grouped into a plurality of groups. In this case, J (J is an integer) memory cells adjacent to the drain select transistor DST are defined as a first memory cell group, and K (K is an integer) memory cells adjacent to the source select transistor SST are defined as a second memory cell. The remaining memory cells may be defined as a group and the third memory cell group may be defined.

5) Soft Program Verification Voltage Setting for Each Memory Cell Group (S260)

The target verify voltage setting of the soft program is set for each of the first to third memory cell groups. Since the memory cells included in the first memory cell group are adjacent to the drain select transistor, the HCI erase disturb phenomenon occurs, and the memory cells included in the second memory cell group generate the FN erase erase phenomenon. It is preferable to set the verify voltage applied to the first target verify voltage and the verify voltage applied to the second memory cell group to a second target verify voltage higher than the first target verify voltage. This is to improve the distribution of threshold voltages differently during the erase operation according to the HCI-like erase disturbance and the FN-like erase disturbance.

6) Soft program is sequentially programmed into each memory cell group (S260).

Steps S150 to S200 of FIG. 3 described above are sequentially performed to perform a soft program operation for each memory cell group. In this case, the first to third target verify voltages set for each memory cell group may be used as the soft program verify voltages for the odd memory cells of the first to third memory cell groups.

That is, even memory cells of the memory cells of the first memory cell group perform a soft program verification (S160) by setting a voltage lower than the first target verify voltage to the first verify voltage PV1, and perform the first program. The odd memory cells of the memory cells may set the first target verify voltage to the second verify voltage PV2 to perform a soft program verify (S190). Further, even memory cells of the memory cells of the second memory cell group perform a soft program verification (S160) by setting a voltage lower than the second target verify voltage to the first verify voltage PV1, and perform the second program. The odd memory cells of the memory cells may set the second target verify voltage to the second verify voltage PV2 to perform a soft program verify (S190). Even memory cells among the memory cells of the third memory cell group are set to the first verify voltage PV1 lower than the third target verify voltage to perform the soft program verification (S160), and among the memory cells of the third memory cell group The odd memory cells perform the soft program verification (S190) by setting the third target verify voltage to the second verify voltage PV2.

The controller 140 may control the voltage providing unit 140 to output the verification voltage set for each memory cell group.

According to the second embodiment of the present invention, the threshold voltage distribution between the even and odd memory cells can be uniformly soft programmed, and the erase disturb phenomenon can be improved by controlling the threshold voltage distribution of the memory cells for each memory cell group. have.

6 is a flowchart illustrating a method of erasing a nonvolatile memory device according to a third embodiment of the present invention.

1) Erasing Operation (S310)

The drain select line DSL and the source select line SSL of the memory cell block 110 are floated, and an erase voltage is applied to the P-well of the memory cell block 110 to perform an erase operation.

2) erase verification (S320)

An erase verify operation is performed by sensing threshold voltages of the memory cells of the memory cell block 110 using the page buffer PB. The erase verify operation checks whether all memory cells of the memory cell block 110 are erased to have a threshold voltage less than or equal to the erase threshold voltage ev. In an erase verify operation, if a memory cell has a threshold voltage higher than the erase threshold voltage ev, it is determined as a fail. If all memory cells have a threshold voltage less than the erase threshold voltage ev, a pass is determined.

3) erase voltage increase (S330)

If it is determined that the result of the erase verification (S320) is a fail, the erase voltage is increased by the step potential, and the operation is repeated from the above-described erase operation (S310).

The memory cell is erased so as to have a threshold voltage distribution as shown in FIG. 4A by the ISPE method of repeatedly performing the above steps S110 to S130.

4) First soft program (S340)

The first soft program operation is performed on all the memory cells of the memory cell block 110. The first soft program operation is sequentially performed for each word line. In the first soft program operation, a program allowable voltage (for example, 0 V) is applied to an odd bit line connected to an odd memory cell, and a set voltage higher than the program allowable voltage is applied to an even bit line connected to an even memory cell (for example, 0.2V) is applied. This is to increase the channel potential of the even memory cell by ΔV, and to program the threshold voltage of the even memory cell by ΔV lower than the threshold voltage of the odd memory cell.

The operation of applying a set voltage to an even bit line connected to an even memory cell applies a power supply voltage to the sensing node SO through the precharge unit 122 of the page buffer PB, and applies a potential level of the sensing signal PBSENSE. It can be carried out by adjusting.

In this case, the first soft program operation may use an ISPP method, but the verification operation may be skipped. In addition, the program pulse is applied to the memory cell block 110 by a set number of pulses (for example, two times).

The first soft program operation is to increase the threshold voltages of the even and odd memory cells to a predetermined level to reduce the execution time of the second soft program and the third soft program operation.

The above-described first soft program operation can be skipped.

5) Second Soft Program for Even Memory Cell (S350)

The second soft program operation is performed on the even memory cell. The second soft program operation is performed by applying a soft program voltage to a word line connected to the selected memory cell among the memory cells MC0e to MCne connected to the even bit line BLe. The second soft program operation applies a program inhibit voltage (eg, a power supply voltage) to the odd bit lines, and applies a program allowance voltage (eg, 0V) to the even bit lines.

6) Soft Program Verification (S360)

The soft program verifying operation is performed by applying a verify voltage PV to a selected word line of a memory cell block and applying a pass voltage to the remaining word lines, and then sensing the potential of the even bit line BLe through the page buffer. do.

The controller 140 controls the potential level of the verification voltage generated by the voltage providing unit 130 to control the first verification voltage PV1 to be applied to the selected word line.

As a result of the soft program verification, even if any one of the even memory cells connected to the selected word line has a threshold voltage higher than the first verify voltage PV1, the pass voltage is determined as a pass. If it is lower than PV1), it is considered a failure.

In this case, the first verification voltage PV1 may be set to be lower than the target threshold voltage to be programmed last.

7) Soft program voltage increase (S370)

If it is determined that the soft program verification (S360) is a result of failing, the soft program voltage is increased by the step voltage and re-executed from the second soft program S150 for the even memory cell.

The even memory cells are soft programmed to have the threshold voltage distribution as shown in B of FIG. 4 by using the ISPP method which repeats the above steps S150 to S170.

8) Third soft program for the odd memory cell (S380)

The third soft program operation is performed on the odd memory cell. The third soft program operation is performed by applying a soft program voltage to a word line connected to the selected memory cell among the memory cells MC0o to MCno connected to the odd bit line BLo. The third soft program operation applies a program prohibition voltage (eg, a power supply voltage) to the even bit lines, and applies a program allowance voltage (eg, 0V) to the odd bit lines.

In the third soft program operation with respect to the odd memory cell, the adjacent voltages of the even memory cells increase due to the interference effect, so that the threshold voltage distribution of B increases as the threshold voltage distribution of C as shown in FIG. 4.

9) Soft program verification (S390)

In the soft program verifying operation, a second verifying voltage PV2 is applied to a selected word line of a memory cell block and a pass voltage is applied to the remaining word lines, and then the potential of the odd bit line BLo is sensed through the page buffer. To do it.

The controller 140 controls the potential level of the verify voltage generated by the voltage provider 130 to apply the second verify voltage PV2 to the selected word line. The second verify voltage PV2 is preferably equal to the target threshold voltage to be programmed last.

As a result of the soft program verification, even if any one of the odd memory cells connected to the selected word line has a threshold voltage higher than the second verify voltage PV2, it is determined as a pass, and the threshold voltages of all the memory cells are determined as the second verify voltage ( If it is lower than PV2), it is regarded as a fail. If it is determined that the soft program verifies as a pass, the erase operation of the nonvolatile memory device is terminated.

10) Soft program voltage increase (S400)

When it is determined that the soft program verification (S390) is a result of the fail, the soft program voltage is increased by the step voltage and re-executed from the third soft program S380 for the odd memory cell.

By using the ISPP method which repeats the above-described steps S380 to S400, the odd memory cells are soft programmed to have a threshold voltage distribution equal to 4 in C.

According to an embodiment of the present invention, the first and second soft program operations are performed after programming the threshold voltages of the even memory cells lower than the threshold voltages of the odd memory cells during the first soft program operation. Compared with each other, the threshold voltage difference between the even memory cell and the odd memory cell can be more precisely controlled, and thus the even and odd memory cells have a uniform threshold voltage distribution due to an increase in the interference effect during the soft program operation of the odd memory cells.

Although the present invention has described the second and third soft program operations for a selected word line of a memory cell block including a plurality of word lines, the next word after the second and third soft program operations for one word line is completed. It is desirable to perform second and third soft program operations on the line.

The third embodiment of the present invention is applicable to the step (S260) of sequentially soft program each memory cell group in the second embodiment of the present invention. That is, in operation S260 to which the first embodiment of the second embodiment is applied, the third embodiment may be applied instead of the first embodiment.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention.

110: memory cell block 120: page buffer unit
PB: Page buffer 121: Bit line selector
122: precharge unit 123: sensing unit
130: voltage providing unit 140: control unit

Claims (19)

A memory cell block including even memory cells connected to the even bit line and odd memory cells connected to the odd bit line;
A page buffer coupled to the even bit line and the odd bit line, and configured to soft program verify the even memory cells and the odd memory cells;
A voltage providing unit for selectively applying verification voltages to a plurality of word lines to which the even memory cells and the odd memory cells are commonly connected; And
A control unit for controlling the voltage providing unit and the page buffer to sequentially perform the soft program operation of the even memory cells and the soft program operation of the odd memory cell during the soft program operation after the memory cell block is erased. Nonvolatile memory device comprising a.
The method of claim 1,
The control unit simultaneously soft-programs the even memory cells and the odd memory cells in a section in which a soft program pulse is applied a predetermined number of times during the soft program operation, and sequentially in the subsequent section, the even memory cells and the odd memory cells. And controlling the voltage provider and the page buffer to soft program.
The method of claim 1,
The control unit controls the voltage providing unit such that a level of a first verify voltage applied to the even memory cell and a second verify voltage applied to the odd memory cell are different from each other during a verify operation during the soft program operation. .
The method of claim 1,
And the controller controls the page buffer so that a level of a program permission voltage applied to the even bit line and a program permission voltage applied to the odd bit line is different from each other during the soft program operation.
The method of claim 1,
The control unit may include a verify voltage applied to word lines of a first group adjacent to a drain select line among the plurality of word lines during the soft program operation. And control the voltage controller to be lower.
Erasing the even and odd memory cells by applying an erase voltage to a memory cell block including the even and odd memory cells;
Performing a first soft program operation to increase threshold voltages of the even memory cells and the odd memory cells by a predetermined voltage;
Performing a second soft program operation to cause the even memory cells to have a threshold voltage value lower than a target threshold voltage; And
And performing a third soft program operation to cause the odd memory cells to have the target threshold voltage value.
The method according to claim 6,
And applying a first verify voltage lower than the target threshold voltage to a word line to which the even memory cells are connected during the verify operation of the second soft program operation.
The method according to claim 6,
And applying the second verify voltage equal to the target threshold voltage to the word line to which the odd memory cells are connected during the verify operation of the second soft program operation.
The method according to claim 6,
And the first soft program operation is performed by applying a program pulse gradually rising by a step voltage to the even and odd memory cells for a predetermined number of times.
The method according to claim 6,
And soft programming the threshold voltages of the even memory cells to be lower than the threshold voltages of the odd memory cells during the first soft program operation.
11. The method of claim 10,
And controlling the potential of the even bit line to which the even memory cells are connected to be higher than the potential of the odd bit line to which the odd memory cells are connected during the third soft program operation.
The method according to claim 6,
And if it is determined that the second soft program operation is a fail, increasing the soft program voltage by a step voltage and performing the second soft program operation again from the second soft program operation.
The method according to claim 6,
And resetting the third soft program operation by increasing the soft program voltage by a step voltage when it is determined that the third soft program operation is failed.
The method according to claim 6,
And deleting a threshold voltage of the even memory cells due to an interference effect caused by the odd memory cells during the third soft program operation.
Erasing the memory cells by applying an erase voltage to a memory cell block including memory cells defined as a first memory cell group adjacent to a source select transistor and a second memory cell group adjacent to a drain select line;
Setting a first verify voltage corresponding to each of the first memory cell group and the second memory cell group and a second verify voltage having a different voltage level from the first verify voltage;
Soft programming the threshold voltage of the first memory cell group to be lower than the first verify voltage; And
And soft programming the threshold voltage of the second group of memory cells to be lower than the second verify voltage.
The method of claim 15,
Soft programming the memory cells included in the first memory cell group may include
Even memory cells connected to even bit lines of the first memory cell group include:
Performing a first soft program operation to have a threshold voltage lower than a first voltage lower than the first verify voltage; And
And performing a second soft program operation such that odd memory cells connected to odd bit lines of the first memory cell group have a threshold voltage lower than a second voltage higher than the first voltage.
The method of claim 15,
Soft programming the memory cells included in the second memory cell group may include
Performing a third soft program operation so that even memory cells connected to even bit lines of the second memory cell group have a threshold voltage lower than a third voltage lower than the second verify voltage; And
And performing a fourth soft program operation such that even memory cells connected to even bit lines of the second memory cell group have a threshold voltage lower than a fourth voltage higher than the third voltage.
The method of claim 15,
After setting the first and second verify voltage,
And performing a fifth soft program operation to increase threshold voltages of the memory cells of the first memory cell group and the second memory cell group by a predetermined voltage.
The method of claim 18,
In the fifth soft program operation, threshold voltages of even memory cells connected to even bit lines among the memory cells of the first memory cell group and the second memory cell group may correspond to the first memory cell group and the second memory cell group. And soft programming the lower voltage of the odd memory cells connected to the odd bit lines.

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