CN101071640A - Method for verifying flash memory devices - Google Patents
Method for verifying flash memory devices Download PDFInfo
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- CN101071640A CN101071640A CNA2007100075243A CN200710007524A CN101071640A CN 101071640 A CN101071640 A CN 101071640A CN A2007100075243 A CNA2007100075243 A CN A2007100075243A CN 200710007524 A CN200710007524 A CN 200710007524A CN 101071640 A CN101071640 A CN 101071640A
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- memory cell
- cell strings
- bit lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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Abstract
A method of verifying a flash memory device is provided. According to a method of verifying a flash memory device, memory cell strings connected to an even bit line and an odd bit line are discharged at the same time. A voltage is applied to the memory cell strings connected to the even bit line and the odd bit line at the same time to precharge the memory cell strings. The memory cell strings connected with the even bit line is verified to be erased by sensing the state of the memory cell string connected to the even bit line. The memory cell strings connected with the odd bit line is verified to be erased by sensing the state of the memory cell string connected to the odd bit line.
Description
Technical field
A kind of flush memory device of this patent relate generally to, and more specifically, relate to a kind of method of using page buffer to come verifying flash memory devices, wherein can reduce programming or the proving time of wiping and can shorten total driving time.
Background technology
In recent years, to the increase in demand of this semiconductor storage unit, described semiconductor storage unit can carry out electricity programming and wipe and do not need the refresh function of overwriting data at set intervals.In addition, have the jumbo memory device that to store mass data, developed the height integrated technology of memory cell in order to develop.
In order to improve the integrated level of memory cell, the nand flash memory device can have a plurality of unit, with these units in series to form a string and shared two strings that contact.In the nand flash memory device, the threshold voltage by the control store unit is injected in the floating gate from floating gate ejected electron by the F-N tunnelling with electronics simultaneously and carries out programming and wipe.
Therefore, owing to the electronics of floating gate is emitted from the unit of wiping, so the unit of wiping has negative threshold voltage.Because electronics is injected in the floating gate of programming unit, so programmed cells has positive threshold voltage.But in the situation of nand flash memory device, possibility gains (gain) owing to electric charge or failure appears in loss of charge.Can carry out some checkings relevant with these characteristics.Carry out with wiping whether normally for verification of programming, use page buffer.
Page buffer is used for supplying to the data of memory cell or storage memory cell and exporting the data of being stored then from I/O pad reception lot of data and with the data that received.In the past, page buffer is made of with temporary storaging data single register.Now, page buffer comprises pair register, so that increase the speed of programming when Large Volume Data is programmed in the nand flash memory device.
Carry out erase verification for nand flash memory device, use a kind of column scan method: determine the whether on of all unit to whole word lines by applying 0V voltage to page buffer with pair register structure.In this column scan method,, unit is defined as failure if turn-offing.
In order to carry out erase verification,,, on selected bit line, carry out erase verification by comprising three steps of precharge, estimation and sensing in the mode identical with normal read operation.In above-mentioned column scan method, by bit line being divided into even bitlines and odd bit lines realizes erase verification.Correspondingly, after even bitlines is verified, the checking odd bit lines.Therefore, determine whether that by twice proof procedure executed wipes.This has caused the long erase verification time.
Simultaneously, in multi-level unit, the threshold voltage distribution of erase unit is influential to the threshold voltage of programming unit.Therefore, finish execution rearmounted program (post program) on the unit of wiping.Carry out rearmounted program and after rearmounted program, carry out erase verification by adopting the ISPP method.Therefore, if the erase verification time is elongated, then prolonged total erasing time.
In addition, when programming, to have prolonged the program verification time with top identical mode.Therefore, time of always programming is elongated.
Summary of the invention
Therefore, this patent has solved the problems referred to above, and discloses a kind of method of verifying flash memory devices, wherein can shorten the proving time and shorten total driving time.
This patent also discloses a kind of method of verifying flash memory devices, and wherein dual numbers bit line and odd bit lines are carried out precharge and estimation simultaneously, and sequentially carries out sensing subsequently, has therefore reduced the proving time.
This patent also discloses a kind of method of verifying flash memory devices, wherein carry out precharge and estimation simultaneously and sequentially dual numbers bit line and odd bit lines are carried out sensing subsequently by dual numbers bit line and odd bit lines, compared with prior art this method can reduce half with the proving time, and therefore compared with prior art total driving time can be reduced 2/3.
According to an aspect of the present invention, provide a kind of method of verifying flash memory devices, may further comprise the steps: will be connected respectively to the memory cell strings discharge of even bitlines and odd bit lines; Voltage is applied to each memory cell strings that is connected respectively to even bitlines and odd bit lines, thereby memory cell strings is carried out precharge; Carry out sensing by state and verify whether the memory cell strings that is connected to this even bitlines is wiped free of the memory cell strings that is connected to even bitlines; And carry out sensing by state and verify whether the memory cell strings that is connected to this odd bit lines is wiped free of the memory cell strings that is connected to odd bit lines.
In this patent, also describe a kind of method of verifying flash memory devices, having comprised: will be connected respectively to the memory cell strings discharge of even bitlines and odd bit lines; Voltage is applied to the memory cell strings that is connected respectively to even bitlines and odd bit lines, thereby memory cell strings is carried out precharge; Carry out sensing by state and verify whether the memory cell strings that is connected to even bitlines is programmed, and carry out sensing by state and verify whether the memory cell strings that is connected to odd bit lines is programmed the memory cell strings that is connected to odd bit lines to the memory cell strings that is connected to even bitlines.
This patent has also been described a kind of method of verifying flash memory devices, and wherein this flush memory device comprises: the first transistor is used for by even bitlines and odd bit lines validation signal being supplied to memory cell array in response to first control signal; Transistor seconds is used for coming connected storage cell array and first node in response to second control signal by even bitlines and odd bit lines; The 3rd transistor is used to respond the 3rd control signal current supply is arrived first node; Latch is used to store the output data from the selected unit of memory cell array; The 4th transistor is used for the state that comes the control lock storage according to the voltage level and the 4th control signal of first node.This method comprises: respond first control signal memory cell strings that is connected respectively to even bitlines and odd bit lines is discharged, and simultaneously, respond the 3rd control signal voltage is supplied to first node, and simultaneously, second control signal that responds first voltage level supplies to the memory cell strings that is connected respectively to even bitlines and odd bit lines with the voltage of first node, thereby to memory cell strings precharge; Second control signal that responds second voltage level verifies by the state that storage is connected to the memory cell strings of even bitlines whether the memory cell strings that is connected to even bitlines is wiped free of; And second control signal of response tertiary voltage level verifies by the state that storage is connected to the memory cell strings of odd bit lines whether the memory cell strings that is connected to odd bit lines is wiped free of.
First control signal can remain 1.6 to 5.5V voltage level or power source voltage Vcc.
Second control signal of first voltage level can remain 1.0 to 5.5V voltage level or power source voltage Vcc, second control signal of second voltage level and tertiary voltage level can remain 1.0 to 2.2V voltage level, and second voltage level can remain the voltage level identical or higher with first voltage level.
The application time of second control signal that can second voltage level is set to longer than the application time of second control signal of tertiary voltage level.
Description of drawings
Fig. 1 is a circuit diagram of verifying the page buffer that uses in the method for nand flash memory device according to an embodiment of the invention; And
Fig. 2 is the operation waveform of page buffer, is used to illustrate the method for verifying the nand flash memory device according to an embodiment of the invention.
Embodiment
Now with reference to accompanying drawing description each embodiment according to this patent.Because these embodiment provide in order to allow those skilled in the art understand this patent, so they can be made amendment in every way and the scope of this patent is not limited by each embodiment that describes later.
Fig. 1 is a circuit diagram of verifying the page buffer that uses in the method for nand flash memory device according to an embodiment of the invention.Figure 1 illustrates the circuit diagram of the master register in the page buffer of pair register structure with master register and cache register.
Referring to Fig. 1, bit line selected cell 120 comprises a plurality of transistors.Drive first and second nmos pass transistor N101 and the N102 in response to even number and odd number discharge signal DISCHe and DISCHo respectively, and correspondingly verifying voltage VIRPWR is applied to the memory cell strings of the memory cell array 110 that is connected to even bitlines BLe or odd bit lines BLo.Select signal BSLe and BSLo to drive third and fourth nmos pass transistor N103 and the N104 in response to even number and odd bit lines respectively, and the correspondingly bit line and the sense node SO of connected storage cell array 110.
Drive PMOS transistor P101 in response to precharging signal PRECHb, thereby voltage is applied to sense node SO.
When returning program of file copy, the 5th nmos pass transistor 105 responds back the output node QAb that copies signal COPYBACK and connect sense node SO and latch 130.Latch 130 interim storages are from the output data and the outside data of supplying with of memory cell array 110 outputs.Voltage level according to sense node SO drives the 6th nmos pass transistor N106.Response is read signal READ_L and is driven the 7th nmos pass transistor N107, and has therefore connected the output node QAb and the ground terminal Vss of latch 130.
Drive the 8th nmos pass transistor N108 in response to signal DI_L, and therefore connected the output node QAb of I/O terminal YA and latch 130.Response signal nDI_L drives the 9th nmos pass transistor N109, and has therefore connected the input node QA of I/O terminal YA and latch 130.Response reset signal RESET_L drives the tenth nmos pass transistor N110 and the latch 130 of therefore resetting.Response signal PROGRAM_L drives the 11 nmos pass transistor N111 when programming operation, and therefore information to be programmed is sent to selected bit line.
Response signal PBDO_L drives the tenth bi-NMOS transistor N112 and therefore exports the voltage level of programming node NA.In addition, reverser I101 is anti-phase with the voltage level of the output node QAb of latch 130, and anti-phase voltage level is sent to programming node NA.
Fig. 2 is the operation waveform of page buffer, is used to illustrate the method according to the checking nand flash memory device of the embodiment of the invention.Below with reference to Fig. 1 and 2 erase verification method according to the nand flash memory device of the embodiment of the invention is described.
1) period A: discharge
Section is applied for 1.6V simultaneously to the high level of 5.5V or even number and the odd number discharge signal DISCHe and the DISCHo of power source voltage Vcc, thereby connects first and second nmos pass transistor N101 and the N102 at one time.Therefore, the voltage level of validation signal VIRPWR supplies to bit line BLe and BLo by the first and second nmos pass transistor N101 and N102.Validation signal VIRPWR keeps the voltage level of 0V when erase verification.Therefore, even number and odd bit lines BLe and BLo are applied in the voltage with 0V.In addition, reset signal RESET_L is applied to the pulse of high level, thereby connects the tenth nmos pass transistor N110.Therefore, node QA becomes low level and node QAb maintenance high level.As a result, the replacement latch 130.At this moment, all word line WL0 are applied in voltage with 0 to 1V to WL31, and drain selection wire DSL and drain selection line SSL also are applied in the voltage with 0V.
2) period B: precharge
When even number and odd number discharge signal DISCHe and DISCHo were applied to low level, the first and second nmos pass transistor N101 and N102 turn-offed.In addition, because precharging signal PRECHb is applied for low level, a PMOS transistor P101 connects.Therefore, power source voltage Vcc is applied to sense node SO, makes sense node SO keep high level.In addition, select signal BSLe and BSLo to be applied for 1.0 to 5.5V voltage level even number and odd bit lines or be about the first voltage V1 of power source voltage Vcc.Therefore, even number and odd bit lines BLe and BLo are applied respectively with the first voltage V1 and voltage (V1-Vt) (wherein deducting the threshold voltage vt of the 3rd or the 4th nmos pass transistor N103 or N104 from the first voltage V1).In this case, drain electrode selection wire DSL has been applied voltage.
3) period C: estimation
Because even number and odd bit lines select signal BSLe and BSLo to be applied to low level, the third and fourth nmos pass transistor N103 and N104 turn-off.Therefore, stop the power supply of dual numbers and odd bit lines BLe and BLo, and controlled the voltage level of even number and odd bit lines BLe and BLo according to the state of the memory cell that is connected to even number and odd bit lines BLe and BLo respectively.That is, if memory cell is not in erase status, then the voltage level of even number or odd bit lines BLe or BLo remains the voltage level of V1-Vt.But if memory cell is in erase status, then the voltage level of even number or odd bit lines BLe and BLo reduces gradually and remains low level subsequently from V1-Vt.At this moment, because a PMOS transistor P101 keeps connection by low level precharging signal PRECHb, so sense node SO keeps high level.Simultaneously, apply the signal of high level by drain electrode selection wire DSL and drain selection line SSL.The unit estimation period is set to keep 10 μ s or less time.
4) period D: even location sensing
Because precharging signal PRECHb is applied for high level, a PMOS transistor P201 turn-offs.Keep about 1.0 the second voltage V2 owing to select signal BSLe to be applied for even bitlines, so the 3rd nmos pass transistor N103 connects to the 2.2V voltage level.If memory cell is not an erase unit, then the voltage level of even bitlines BLe is remained the voltage level of V1-Vt, and the voltage level of sense node SO is remained high level.If memory cell is not an erase unit, then the voltage level of even bitlines Ble remains the voltage level of V1-Vt and the voltage level of sense node SO remains high level.If memory cell is in erase status, then the voltage level of even bitlines Ble reduces gradually and remains low level then.In this state, if read the high level pulse that signal READ_L is applied to 1.0 to 10 μ s, then sense node SO remains high level when memory cell is not erase unit.Therefore, the response high impulse read signal READ_L, the 6th nmos pass transistor N106 connects and the 7th nmos pass transistor N107 connects.As a result, node QAb remains low level and node QA remains high level.On the contrary, if memory cell is an erase unit, then sense node SO remains low level and the 7th nmos pass transistor N107 shutoff.Therefore, node QAb is retained as high level and node QA remains low level.Therefore, the voltage level to node QA detects so that the state of sensing even location.
5) period E: odd location sensing
Owing to select signal BSLe to be applied for low level even bitlines, the 3rd nmos pass transistor N103 turn-offs.Remain to about 1.0 tertiary voltage V3 owing to select signal BSLo to be applied for odd bit lines, so the 4th nmos pass transistor N104 connects to the 2.2V voltage level.The application time that requires tertiary voltage V3 to be less than or equal to the second voltage V2 and tertiary voltage V3 is shorter than the application time of the second voltage V2.If memory cell is not an erase unit, then the voltage level of odd bit lines BLo is retained as the voltage level of V1-Vt, and the voltage level of sense node SO remains high level.
But if memory cell is to be in erase status, then the voltage level of odd bit lines BLo reduces gradually and remains low level subsequently, and the voltage level of sense node SO remains low level.In this state, will read signal READ_L and be applied for 1.0 to 10 μ s high level pulses.If memory cell is not in erase unit, then sense node SO remains high level.Therefore, the response high impulse read signal READ_L, the 6th nmos pass transistor N106 connects and the 7th nmos pass transistor N107 connects.Because node QAb remains low level, so node QA remains high level.On the contrary, if memory cell is an erase unit, then sense node SO remains low level, and the 7th nmos pass transistor N107 turn-offs.Therefore, node QAb remains high level and node QA remains low level.Therefore, the voltage level to node QA detects so that the state of sensing odd location.
The erase verification method of nand flash memory device according to the embodiment of the invention described above.But this method can be applied to the program verification method in the same manner.Therefore, omit the detailed description of this method.
As mentioned above, with the precharge simultaneously of even bitlines and odd bit lines and estimation and sequentially carry out sensing subsequently.Therefore, the erase verification time compared with prior art can reduce half at most, and total erasing time compared with prior art can reduce 2/3.Therefore can improve the operating speed of device.In addition, the present invention can be applied to program verification in the same manner.Therefore also can reduce the programming time.
Although make the description of front, should be appreciated that those of ordinary skills can change and revise this patent under the situation of the spirit and scope that do not break away from this patent and claims about each embodiment.
The main element symbol description
110 memory cell arrays
120 bit line selected cells
130 latchs
The Ble even bitlines
Blo odd bit lines BLo
The BSLe even bitlines is selected signal
The BSLo odd bit lines is selected signal
COPYBACK returns the copy signal
The DI_L signal
DISChe even number discharge signal
DISCHo odd number discharge signal
The DSL selection wire that drains
The I101 reverser
N101 first nmos pass transistor
N102 second nmos pass transistor
N103 the 3rd nmos pass transistor
N104 the 4th nmos pass transistor
N105 the 5th nmos pass transistor
N106 the 6th nmos pass transistor
N107 the 7th nmos pass transistor
N108 the 8th nmos pass transistor
N109 the 9th nmos pass transistor
N110 the tenth nmos pass transistor
N111 the 11 nmos pass transistor
N112 the tenth nmos pass transistor
The NA programming node
The nDI_L signal
P101 PMOS transistor
P201 the one PMOS transistor
The PRECHb precharging signal
The PROGRAM_L signal
QA imports node
The QAb output node
READ_L reads signal
The RESET_L reset signal
The SO sense node
SSL drain selection line
V1 first voltage
V2 second voltage
The V3 tertiary voltage
The Vcc supply voltage
The VIRPWR validation signal
The Vss ground terminal
The Vt threshold voltage
The WL0-WL31 word line
The YAI/O terminal
Claims (9)
1. the method for a verifying flash memory devices comprises:
The memory cell strings discharge of even bitlines and odd bit lines will be connected respectively to;
Voltage is applied to the described memory cell strings that is connected respectively to described even bitlines and described odd bit lines, thereby to described memory cell strings precharge;
Carry out sensing by state and verify whether each memory cell strings that is connected to described even bitlines is wiped free of the described memory cell strings that is connected to described even bitlines;
Carry out sensing by state and verify whether each memory cell strings that is connected to described odd bit lines is wiped free of the described memory cell strings that is connected to described odd bit lines.
2. the method for a verifying flash memory devices, described flush memory device comprises:
The first transistor is used for by even bitlines and odd bit lines validation signal being supplied to memory cell array in response to first control signal;
Transistor seconds is used for being connected described memory cell array and first node in response to second control signal with odd bit lines by described even bitlines;
The 3rd transistor is used to respond the 3rd control signal current supply is arrived described first node;
Latch is used to store the output data from the selected unit of described memory cell array;
The 4th transistor is used for the state of controlling described latch according to the voltage level and the 4th control signal of described first node,
Described method comprises:
In response to described first control signal memory cell strings that is connected respectively to described even bitlines and described odd bit lines is discharged;
In response to described the 3rd control signal voltage is supplied to described first node, and simultaneously the voltage of described first node is supplied to the described memory cell strings that is connected respectively to described even bitlines and described odd bit lines, thereby described memory cell strings is carried out precharge in response to described second control signal of first voltage level;
Described second control signal in response to second voltage level verifies by the state that storage is connected to each memory cell strings of described even bitlines whether each memory cell strings that is connected to described even bitlines is wiped free of; And
Described second control signal of response tertiary voltage level verifies by the state that storage is connected to each memory cell strings of described odd bit lines whether each memory cell strings that is connected to described odd bit lines is wiped free of.
3. method as claimed in claim 2, wherein said first control signal remain 1.6 voltage levels to 5.5V or power source voltage Vcc.
4. method as claimed in claim 2, described second control signal of wherein said first voltage level remain 1.0 to 5.5V voltage level or power source voltage Vcc.
5. method as claimed in claim 2, described second control signal of wherein said second voltage level remain 1.0 to 2.2V voltage level.
6. method as claimed in claim 2, described second control signal of wherein said tertiary voltage level remain 1.0 to 2.2V voltage level.
7. method as claimed in claim 2, wherein said second voltage level remains the voltage level more than or equal to described first voltage level.
8. method as claimed in claim 2, the application time of described second control signal of wherein said second voltage level is set to longer than the application time of described second control signal of described tertiary voltage level.
9. the method for a verifying flash memory devices comprises:
The memory cell strings discharge of even bitlines and odd bit lines will be connected respectively to;
Voltage is applied to each memory cell strings that is connected respectively to described even bitlines and described odd bit lines, thereby described memory cell strings is carried out precharge;
Carry out sensing by state and verify whether each memory cell strings that is connected to described even bitlines is programmed each memory cell strings of being connected to described even bitlines; And
Carry out sensing by state and verify whether each memory cell strings that is connected to described odd bit lines is programmed each memory cell strings of being connected to described odd bit lines.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2006-0041768 | 2006-05-10 | ||
| KR1020060041768A KR100763114B1 (en) | 2006-05-10 | 2006-05-10 | Method of verifying a flash memory device |
| KR1020060041768 | 2006-05-10 |
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| Publication Number | Publication Date |
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| CN101071640A true CN101071640A (en) | 2007-11-14 |
| CN101071640B CN101071640B (en) | 2010-04-14 |
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| JP (1) | JP5063086B2 (en) |
| KR (1) | KR100763114B1 (en) |
| CN (1) | CN101071640B (en) |
| TW (1) | TWI310561B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103700400A (en) * | 2012-09-28 | 2014-04-02 | 上海华虹集成电路有限责任公司 | Data latching circuits for Flash EEPROM |
| CN110838323A (en) * | 2018-08-17 | 2020-02-25 | 北京兆易创新科技股份有限公司 | Programming method and system of memory |
| TWI753607B (en) * | 2019-11-11 | 2022-01-21 | 華邦電子股份有限公司 | Memory device and multi physical cells error correction method thereof |
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| KR100954946B1 (en) * | 2008-05-20 | 2010-04-27 | 주식회사 하이닉스반도체 | Method of erasing a non volatile memory device |
| KR101068494B1 (en) | 2009-06-29 | 2011-09-29 | 주식회사 하이닉스반도체 | Method of erasing a non volatile memory device |
| KR101371516B1 (en) | 2009-10-21 | 2014-03-10 | 삼성전자주식회사 | The operation method of flash memory device and memory system including the same |
| KR102153017B1 (en) * | 2012-12-07 | 2020-09-07 | 에스케이하이닉스 주식회사 | Semiconductor memory device and operation method thereof |
| KR102701556B1 (en) * | 2019-04-08 | 2024-09-04 | 에스케이하이닉스 주식회사 | Page buffer, memory device having the page buffer and operating method thereof |
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- 2006-05-10 KR KR1020060041768A patent/KR100763114B1/en active IP Right Grant
- 2006-11-10 TW TW095141661A patent/TWI310561B/en active
- 2006-11-10 JP JP2006305559A patent/JP5063086B2/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103700400A (en) * | 2012-09-28 | 2014-04-02 | 上海华虹集成电路有限责任公司 | Data latching circuits for Flash EEPROM |
| CN103700400B (en) * | 2012-09-28 | 2017-10-31 | 上海华虹集成电路有限责任公司 | Data-latching circuit for Flash EEPROM |
| CN110838323A (en) * | 2018-08-17 | 2020-02-25 | 北京兆易创新科技股份有限公司 | Programming method and system of memory |
| TWI753607B (en) * | 2019-11-11 | 2022-01-21 | 華邦電子股份有限公司 | Memory device and multi physical cells error correction method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100763114B1 (en) | 2007-10-04 |
| JP5063086B2 (en) | 2012-10-31 |
| TWI310561B (en) | 2009-06-01 |
| TW200743112A (en) | 2007-11-16 |
| CN101071640B (en) | 2010-04-14 |
| JP2007305282A (en) | 2007-11-22 |
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