TWI303491B - Semiconductor relay apparatus and wiring board fabrication method - Google Patents

Semiconductor relay apparatus and wiring board fabrication method Download PDF

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Publication number
TWI303491B
TWI303491B TW094104350A TW94104350A TWI303491B TW I303491 B TWI303491 B TW I303491B TW 094104350 A TW094104350 A TW 094104350A TW 94104350 A TW94104350 A TW 94104350A TW I303491 B TWI303491 B TW I303491B
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TW
Taiwan
Prior art keywords
light
substrate
electrode
wafer
led
Prior art date
Application number
TW094104350A
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English (en)
Other versions
TW200541090A (en
Inventor
Taizo Tomioka
Original Assignee
Toshiba Kk
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Publication date
Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of TW200541090A publication Critical patent/TW200541090A/zh
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Publication of TWI303491B publication Critical patent/TWI303491B/zh

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Classifications

    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F04—POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
    • F04B—POSITIVE-DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS
    • F04B49/00—Control, e.g. of pump delivery, or pump pressure of, or safety measures for, machines, pumps, or pumping installations, not otherwise provided for, or of interest apart from, groups F04B1/00 - F04B47/00
    • F04B49/06—Control using electricity
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P31/00—Arrangements for regulating or controlling electric motors not provided for in groups H02P1/00 - H02P5/00, H02P7/00 or H02P21/00 - H02P29/00
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Mechanical Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Led Device Packages (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

1303491 九、發明說明： 【發明所屬之技術領域】 本發明有關於半導體繼電器裝置極小化，及一種製造一 接線板結構的方法。 【先前技術】 最近為了提高可靠度及減少測量儀表如半導體測試器的 大小，而時常使用非接觸繼電器如半導體繼電器裝置以取 代習知接觸繼電器。
以下將參考圖4以說明此半導體繼電器裝置的操作原 理。一發光二極體（LED)55與光電IC56相對，及光電IC56 接到金屬氧化半導體場效電晶體（MOS-FET)57。光電IC56 將LED55發出的光作光電轉換。產生的電壓則用以驅動 MOS-FET57，及開啟/中止MOS-FET57中在八與8 (圖4)之間 流動的電流。LED55及光電IC56必須分離某一距離，以便 用LED55發出的光將整個光二極體陣列照射在光電π%表 面上。 -半導體測試器使賴千個繼電器，而且裝設這些繼電 器的基板是極昂貴的。藉由使半導體繼電器裝置極小化， 即能使半導體測試器極小化及減少併人該測試器的基板成 本二因此’市場需要將半導體繼電器裝置極小化。 藉由此市場需求作為背景，p表 Μ I月出各種半導體繼電器 裝置。以下將參考圖5以說明一種 不里长日本專利申請公開案 1 1-1 63705號中揭示的習知半導 卞守餒齄電裔裝置。此半導體 電器裝置具有接線板37。接線 〃有一大體上形成在中 99478.doc 1303491 央的凹處36，及一接線圖案（未顯示）。作為發光元件的 LED3 8裝在凹處36的底面。由金屬線3 9連接LED前電極及基 板電極（未顯示）。作為光接收元件的光電IC40覆蓋凹處36 的開口，而且與LED38相對。藉由覆晶接合經由凸起41而 使光電IC40接合接線板37。 在裝設光電IC40的接線板37表面上，作為輸出元件的 MOS-FET42藉由覆晶接合經由凸起43而接合。藉由接線板 37上的接線圖案（未顯示）而電氣連接光電IC40及 ® MOS-FET42。透光樹脂44填充在LED38與光電IC40之間。 由遮光樹脂45封閉在接線板37側邊上的部分光電IC40及 MOS-FET42 〇 在此半導體繼電器裝置中，光電IC40及MOS-FET42而覆 晶接合而裝在接線板37上。這使得該封裝尺寸小於習知線 接合所得到的。注意此半導體繼電器裝置中使用的 MOS_FET42必須是橫向雙擴散MOS-FET (以下將稱為橫向 • MOS-FET)，其具有閘極，源極，及沒極，都形成在晶片的 同一面上。 如圖6所示，一習知MOS-FET，具有形成在晶片下表面的 汲極，藉由形成一孔46 (用以收納LED)及二孔47，48 (用以 收納MOS-FET)而裝設在接線板上。在此結構中，藉由線接 合而裝設MOS-FET。這需要容納晶片的空間及容納線接合 微管的空間，所以封裝尺寸大幅增加。 以下將參考圖7A至7F以說明習知矽基板製造方法的例 子。首先，從矽晶圓49的上表面形成孔50(圖7A)。藉由熱 99478.doc 1303491 氧化而在基板上表面形成作為絕緣模的氧化矽層51(圖 7B)。藉由濺擊而在孔50中形成作為鈦膜的接觸臈52，及藉 由電鍍而以銅53填充該等孔50(圖7〇：)。接著機械研磨基板 的二表面以開啟各孔的二端（圖7D)。藉由化學蒸氣沈積 (CVD)而在基板的上及下表面形成絕緣模M(圖7e)。藉由反 應離子蝕刻（RIE)而開啟必要部分（圖7F)。接著依需要而在 基板上表面形成互連。 上述習知半導體繼電器裝置有以下問題。 在圖5所示半導體繼電器裝置中，位於基板底面的外部連 接端與MOS-FET端之間的連接路徑太長。這使得它不能得 到足夠的高頻信號通過特徵。 當使用圖6所示基板時，因接線的佈局而過度增加半導體 繼電器裝置的尺寸，或是加長外部連接端與M〇s_FET端之 間的連接路徑。 而且，以電極位置準確度及平坦的眼光來看，使用習知 陶磁基板或樹脂基板很難製造出具有此形狀的小半導體繼 電器裝置基板。若選擇具高尺寸準確度的矽基板，很難製 造出一基板，它在其上表面上有大的凸出部，及其中藉由 貫牙電極而連接在其上及下表面的電極。例如在習知方法 中，從晶圓的上表面形成凸出部及貫穿電極。然而該晶圓 很難在將貫穿電極曝露在下表面的研磨步驟中支樓。 在考慮以上情況下產生本發明，而其目的是提供一種半 導體、％電器裝置結構’其適於在不劣化其性能下使一半導 體繼電器裝置極小化，及一種製造基板之方法。 99478.doc 1303491 【發明内容】 本專利申請案基於及主張以下曰本專利申請案（申請曰 2004/02/20,中請號2004_044233)的優先權，其内容以引用 的方式併入本文中。 為瞭解決上述問題，本發明包括一種基板，具有··至少 二個凸出部，在其一表面，至少H極，形成在各凸 出部之一凸出末端部分及一電極，形成在一表面藉由一互 連而電氣連接，該互連包括一部分形成在該凸出部之側 面，及一電極，形成在一表面，及一第二電極，形成在其 他表面藉由一貫穿電極而電氣連接，一發光元件，置於該 等凸出部之間，一光接收元件，其設置成俾一光接收部分 相對於該發光元件，及接合成俾一電極連接該凸出末端部 刀 輸出元件，接合该基板，一透光樹脂，其填充在該 發光7G件與該光接收元件之間，及將該發光元件發出之光 透射，及一遮光樹脂，其覆蓋該透光樹脂，該發光元件， 及該光接收元件。 在此繼電器裝置中，該基板凸出部之至少一側面最好是 -斜面，其傾斜至該基板之另—部分形成之—表面，及該 互連最好形成在該至少一斜面上。 人 而且’該凸出部側面形成之斜面之一斜角，與該斜面中 間之-斜角相比，在接近該凸出末端部分處最好較小及在 接近該基板一表面處最好較小。 該凸出部侧面形成之該斜面最好是由一曲面形成，該曲 面在其一剖面具有具一轉折點之一曲線。 99478.doc 1303491 該第二電極最好形成在一矩形渠溝中，該渠溝形成在該 基板之其他表面。 該基板最好主要是由一材料製造，該材料選自由矽及一 矽複合物組成之群，及該等互連最好由絕緣層製造，及最 好以一絕緣層覆蓋該等互連及該基板之電極。 本發明也是一種製造接線板之方法，該接線板在其一表 面具有一凸出部，該方法包括以下步驟：在一晶圓之一下 纟面中形成一非穿孔’在該晶圓之下表面及在該非穿孔中 攀π成-絕緣層，將-導體填充在該非穿孔中，藉由飯刻該 晶圓之-上表面而形成二個凸出部，從該基板之上表面開 啟該非穿孔之-底面，在該晶圓之上表面上形成一絕緣 層，在該絕緣層之一部分中形成一對應該穿孔之孔，該絕 緣層形成在該晶圓之上表面上，及在該晶圓之上表面上形 成多個電極墊及形成一傳導圖案，其連接該等電極墊。 在此方法中’最好使用一含金屬粒子之硬化膏作為填充 籲在该非穿孔中之該導體，該粒子具有不超過之直徑。 ,最好藉由塗上一含金屬粒子之膏而在該晶圓之上表面上 形成該傳導圖案，該粒子具有不超過2〇 nm之直徑。 上述結構及製造方法可在不減少生產力或劣化品質之 下’使半導體繼電器裝置顯著地極小化。 ' 本發明的額外目的及優點將於以下說明中敘述，由該說 明可部分地瞭解本發明，或由實施本發明而明白本發明“。 藉由以下特別提及的手段及組合可實施及得到本發明的目 的及優點。 99478.doc 1303491 【實施方式】 以下將參考圖1，2以說明本發明的實例。 圖1的視圖顯示根據本發明第一實例的半導體繼電器裝 置的剖面結構。此半導體繼電器裝置的外部尺寸是 2·〇χ2·〇χ1·2 (mm3)。LED3，光電 IC4，及 MOS-FET5 裝設在 石夕基板2上，其具有大體上互相平行配置的二個凸出部。亦 即，裝有三個晶片。 _ LED3 的尺寸是〇·2χ〇·2χ〇·2 (mm3)。光電 IC4 與 MOS_FET5 的外部尺寸相同，即〇·6χ1.2χ〇·2 (mm3)。矽基板2及底板6 的凸出部1都是由單一塊製造。 底板ό尺寸是2·〇χ2·〇χ〇·2 (mm3)，而各凸出部1尺寸是 〇·35χ〇·95χ〇·45 (mm3)。各凸出部1在一側面有一斜面7。斜 面7的斜角約為45度。 互連8形成在斜面7上。注意，側面是由包括一曲線的斜 面形成，該曲線具有一轉折點，以便互連8不會在斜面7與 φ 一平面之間的邊界切斷。因此，斜面7的上端（作為凸出部i 的凸出端）及斜面7的下端（作為凸出部1的近端），相對於一 平坦部分形成的表面，以稍微傾斜的角度連接，該平坦部 分不是矽基板2的凸出部1。 藉由貫穿電極16而連接矽基板2與後侧電極17的上表面 電極。各後側電極17功能為外部連接端。LED3裝設在二個 凸出部1之間形成的LED裝設電極9上，且藉由金線u而接 到形成在該等凸出部i之間的LED連接電極1〇。光電IC4置 於凸出的上表面15以便與LED3相對，且經由金凸起12而連 99478.doc -10- 1303491 接。在光電IC4的表層形成光二極體陣列及m〇S-FET驅動 器。 MOS-FET5的位置大體上平行於光電IC4在二個凸出部i 之間的開口方向。類似於光電IC4，MOS-FET5經由金凸起 而連接基板電極。大體上透明的矽橡膠丨3注入LED3與光電 IC4之間。以黑色環氧樹脂14將底板6的上表面完全覆蓋。 圖2是從封裝上方顯示矽基板2與晶片之間的關係。在凸 出的上表面15形成4個電極，及在底板6上形成6個電極。4 ® 個凸出上表面電極中的2個接到底板6上的電極。而且，6 個底板電極中的4個藉由貫穿電極16(其延伸通過基板）而接 到4個後側電極17。各電極有一包括鈦/銅/鎳/金的四層配 置。此實例中使用的MOS-FET5是橫向MOS-FET ,其具有 二個没極18，一源極19，及一閘極20。没極18藉由貫穿電 極16而接到下表面電極17。源極19接到光電IC4的陰極21。 閘極20接到光電IC4的陽極22。光電IC4有二個電極，即陰 φ 極21及陽極22，而二個剩餘電極是偽電極用以增加晶片與 基板之間的接合強度。 此半導體繼電器裝置的操作如以下所述。輸入信號電流 流過LED3，而LED3發光。光電IC4的光二極體陣列從LED3 接收此光，且將產生的電壓施加到MOS-FET5的閘極20。此 施加的電壓使在MOS-FET5的二個汲極18之間流動的電流 流過及中止。 圖3 A至3M敘述本發明半導體繼電器裝置的製造步驟。使 用石夕晶圓23 (其具有0.65 mm的厚度及150 mm的直徑）在每 99478.doc -11 - 1303491 一晶圓中約可製造出3000個基板。注意，圖2僅顯示對應一 繼電器裝置的部分。 首先’藉由深RIE而在矽晶圓23的後側表面24形成孔25 (具有200 μηι的深度及1〇〇 μηι的直徑）及孔26 (具有200 μιη 的深度及200 μηι的直徑）（圖3Α)。在此RIE中使用一種稱為 保希（Bosch)製程的方法。藉由此方法而蝕刻矽，而形成在 其上的CF沈積則保護側壁。 接著在包括孔25及26的整個下表面形成約1 μιη厚的熱氧 _ 化膜27 (圖3Β)。藉由濺擊而在整個下表面形成1〇〇 nm厚的 鈦層，及在鈦層上形成300 nm厚的銅層。亦即，在整個下 表面形成由鈦及銅製造的400 nm厚的金屬膜28(圖3C)。接 著執行電鍍以便將銅29填充在孔25及26，及在整個下表面 形成10 μηι厚的銅膜（圖3D)。除了孔25，26及下表面電極以 外的不必要部分則藉由濕蝕刻而移除，以形成下表面電極 30(圖 3Ε) 〇 φ 在該下表面作為一表面而執行完該等製程後（圖3 Α至 3 E) ’即藉由深rie而在晶圓的上表面執行石夕以留下2個凸出 部1(圖3F)。藉由電漿化學蒸氣沈積（P-CvD)而在處理過的 表面上形成約1 μιη厚的氧化矽膜31(圖3G)。 接著，使用RIE而在對應孔25, 26的上表面的部分32形成 孔（圖3Η)。藉由濺擊而在整個上表面形成1〇11111厚的鈦層， 及在鈦層上形成3〇〇 nm厚的銅層。亦即，在整個上表面形 成由鈦及銅製造的310nm厚的金屬膜33)。藉由濕蝕刻而移 除金屬膜33的不必要部分（圖31)。在此蝕刻令，藉由噴塗而 99478.doc -12- 1303491 執行光阻塗敷。 在晶圓的上及下表面形成1 μπι厚的鍍鎳膜34及0.5 μηι厚 的鍍金膜35(圖3J)。注意，鎳膜及金膜都是由非電式鍍而形 成。 矽基板2上的2個凸出部1之間的電極塗有一傳導銀膏，而 LED3裝設在此電極上。LED3在晶片的上及下表面具有電 極。如此裝設LED3後，在150°C之下加熱5分鐘而使傳導銀 膏硬化。藉由線揍合而連接LED 3上表面的電極與2個凸出 _ 部1之間的電極。 在正甲線接合中’線從晶片電極接到基板電極。然而在 此方法中，金線與光電1C之間的距離較短，因而劣化繼電 器特性。因此，在LED3的上表面電極形成金球凸起，而線 從基板電極接到晶片電極。在LED3的上表面電極形成凸起 以防止電極破裂。使用的金線直徑是28 μχη，且在線的遠端 形成直徑75 μπι的金球。接合溫度是2〇〇°C。 φ 接著藉由一接合工具（未顯示）以6N的負載壓在先前形成 於電極上具有金球凸起的光電1C，且藉由施以超音波振動 200 ms而接合。超音波振動的振幅約為L5 μιη。接合溫度 是200 C，即與線接合相同。在上述條件下，每一凸起可得 到約6Ν的剪力強度。接著，藉由覆晶接合而類似地接合先 前形成在其電極具有金球凸起的MOS-FET (圖3Κ)。 為了使LED3發出光的光學路徑一定，使用施布器（未顯 示）而將矽橡膠13注入LED3與光電IC4之間，及硬化（圖 31) °接著以黑色環氧樹脂丨4塗在基板的整個上表面，硬化 99478.doc -13· 1303491 該環氧樹脂14，且使用鑽石刀而將產生的基板切成個別封 裝（圖3M)。 雖然已說明本發明的實例，但本發明也可作各種改良。 以下將說明這些改良。在上述實例，藉由線接合由金線^ ^ 將LED3作電氣連接。然而若LED3是僅在晶片一面具有電極 的發光元件，則LED3也可藉由覆晶接合而裝設。在上述實 例，在作出孔之後才在表面上作出凸出部。然而此製程順 序也可相反。 而且，在晶片電極上形成凸起後，藉由覆晶接合而在基 板上裝设光電1C及MOS-FET。然而這些凸起也可形成在基 板上。 此外，使用金球凸起藉由超音波熱壓接合而執行覆晶接 合。然而藉由焊接或是使用傳導樹脂的接合也可得到相同 效果。雖然矽橡膠13填充在LED3與光電IC4之間，但是矽 橡膠13也可填充在光電IC4的背面。 • 此外，為了使LED3與光電IC4之間的間距加寬，部分的 基板23(其中將裝設LED3)也可向其他表面延伸。 而且，下表面電極30是由以下步驟形成：在整個下表面 :成由鈦及銅製造的金屬膜28,用銅29填充孔25, 26，在 正個下表面形成銅膜，及藉由濕蝕刻而移除孔h，％及下 2面電極以外的不必要部分。然而在形成由鈦及銅製造的 二屬膜28之後，也能藉由濕蝕刻而移除孔25，26及下表面 電才 11 X外的不必要部分，及接著冑由電鑛以銅Μ填充孔 2 5 ’ 2 6 〇 99478.doc -14- 1303491 熟習此項技藝者將可瞭解額外優點及改良。因此本發明 的最廣特徵*僅限於本文心及所述的特定細節及代^實 例。因此，在不違反後附申請專利範圍及其同等者定義的 一般新穎概念的精神及範圍下，可以作各種改良。 【圖式簡單說明】 併入且作為部分本說明書的附圖，其目的在敘述本發明 的較佳實例，配合以上-般說明及以上較佳實例的詳細說 明’即可解釋本發明的原理。 圖1的視圖顯示根據本發明第一實例的半導體繼電器裝 置的剖面結構； 圖2的視圖顯示根據本發明第一實例的半導體繼電5|裝 置中’基板電極配置與晶片位置間的關係； 圖3A至3M的視圖顯示根據本發明第一實例的半導體繼 電器裝置的製造步驟； 圖4的視圖顯示半導體繼電器裝置的操作原理； 圖5的視圖顯示習知半導體繼電器裝置結構的第一例； 圖6的視圖顯示習知半導體繼電器裝置結構的第二例；及 圖7 A至7F的視圖顯示習知石夕基板的製造步驟。
【主要元件符號說明】 1 凸出部 2 矽基板 3 〜38 ' 55 LED 4、40、 56 光電1C 5、42、 57 MOS-FET 99478.doc -15- 1303491
6 底板 7 表面 8 互連 9 LED裝設 電極 10 LED連接 電極 11 金線 12 金凸起 13 碎橡膠 14 黑色環氧樹脂 15 凸出上表 面 16 貫穿電極 17 背側電極 18 汲極 19 源極 20 閘極 21 陰極 22 陽極 23 基板 24 後側表面 25、 26 、 46 、 47、 48、50 27 熱氧化膜 28 金屬膜 29、 53 銅 99478.doc -16- 1303491 30 31 32 33 34 35 36
37 39 41、43 44、45 49 51 52 下表面電極 氧化矽膜 部分上表面 金屬膜 鍍鎳膜 鍍金膜 凹處 接線板 金屬線 凸起 透光樹脂 矽晶圓 氧化矽層 接觸膜
99478.doc -17-

Claims (1)

1303491 十、申請專利範圍： 一種半導體繼電器裝置，包括： 一基板’具有：至少二個凸出部，在其-表面，至少 -第-電極’形成在各凸出部之一凸出末端部分及一電 極’形成在—表面藉由—互連而電氣連接，該互連包括 一部分形成在該凸出部之側面，及-電極，形成在一表 面，及-第二電極，形成在其它表面藉由一貫穿電極而 電氣連接；
一發光元件，置於該等凸出部之間； :光接收元件，其設置成俾一光接收部分相對於該發 光兀件’及接合成俾一電極連接該凸出末端部分； 一輸出元件，接合該基板； 透光树脂，其填充在該發光元件與該光接收元件之 間’及將該發光元件發出之光透射；及 一遮光樹脂，其覆蓋該透光樹脂，該發光元件，及該 光接收元件。 2·如請求項1之裝置，其中該基板凸出部之至少一側面係一 斜面，其傾斜至該基板之另一部分形成之一表面，及該 互連形成在該至少一斜面上。 •如睛求項2之裝置，其中該凸出部側面形成之該斜面之一 斜角’與該斜面中間之一斜角相比，在接近該凸出末端 部分處較小及在接近該基板一表面處較小。 4·如明求項2之裝置，其中該凸出部側面形成之該斜面係由 一曲面形成，該曲面在其一剖面具有具一轉折點之一曲 99478.doc 1303491 線。 如明求項1之裝置’其中該第二電極形成在一矩形渠溝 中，該渠溝形成在該基板之其它表面。 6·如凊求項1之裝置，其中該基板主要是由一材料製造，該 材料選自㈣及-何合物組成之群，及以一絕緣層覆 蓋該等互連及該基板之電極。 7· 一種製造接線板之方法，該接線板在其一表面具有一凸 出部，該方法包括以下步驟： 在一晶圓之一下表面中形成一非穿孔； 在該晶圓之下表面及在該非穿孔中形成一絕緣層； 將一導體填充在該非穿孔中； 藉由蝕刻該晶圓之一上表面而形成二個凸出部； 從該基板之上表面開啟該非穿孔之一底面； 在該晶圓之上表面上形成一絕緣層； 在該絕緣層之-部分中形成一對應該穿孔之孔，該絕 緣層形成在該晶圓之上表面上；及 在該晶圓之上表面上形成多個電極墊及形成一傳導圖 案’其連接該等電極墊。 8·如明求項7之方法，其中使用一含金屬粒子之硬化膏作為 填充在該非穿孔中之該導體，該粒子具有不超過2〇細之 直徑。 9.如。月求項7之方法’纟中藉由塗上—含金屬粒子之膏而在 該晶圓之上表面上形成該傳導圖案，該粒子具有不超過 20 nm之直徑。 99478.doc _ 2 -
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US9202961B2 (en) 2009-02-02 2015-12-01 Redlen Technologies Imaging devices with solid-state radiation detector with improved sensitivity
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