TWI277194B - Vertically oriented nano-circuit and method to form thereof - Google Patents

Vertically oriented nano-circuit and method to form thereof Download PDF

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Publication number
TWI277194B
TWI277194B TW091117917A TW91117917A TWI277194B TW I277194 B TWI277194 B TW I277194B TW 091117917 A TW091117917 A TW 091117917A TW 91117917 A TW91117917 A TW 91117917A TW I277194 B TWI277194 B TW I277194B
Authority
TW
Taiwan
Prior art keywords
vertically positioned
conductive spacer
conductor
nanocircuit
insulator
Prior art date
Application number
TW091117917A
Other languages
English (en)
Chinese (zh)
Inventor
Thomas C Anthony
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Application granted granted Critical
Publication of TWI277194B publication Critical patent/TWI277194B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H10W20/491—Antifuses, i.e. interconnections changeable from non-conductive to conductive
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H10W20/0636—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material the conductive members being on sidewalls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H10W20/493—Fuses, i.e. interconnections changeable from conductive to non-conductive
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Fuses (AREA)
TW091117917A 2001-09-28 2002-08-08 Vertically oriented nano-circuit and method to form thereof TWI277194B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/964,770 US6611039B2 (en) 2001-09-28 2001-09-28 Vertically oriented nano-fuse and nano-resistor circuit elements

Publications (1)

Publication Number Publication Date
TWI277194B true TWI277194B (en) 2007-03-21

Family

ID=25508970

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091117917A TWI277194B (en) 2001-09-28 2002-08-08 Vertically oriented nano-circuit and method to form thereof

Country Status (6)

Country Link
US (1) US6611039B2 (https=)
EP (1) EP1298727A3 (https=)
JP (1) JP4185338B2 (https=)
KR (1) KR100918161B1 (https=)
CN (1) CN100414705C (https=)
TW (1) TWI277194B (https=)

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US6703652B2 (en) * 2002-01-16 2004-03-09 Hewlett-Packard Development Company, L.P. Memory structure and method making
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Also Published As

Publication number Publication date
EP1298727A3 (en) 2004-10-13
KR20030027823A (ko) 2003-04-07
KR100918161B1 (ko) 2009-09-17
EP1298727A2 (en) 2003-04-02
JP4185338B2 (ja) 2008-11-26
CN100414705C (zh) 2008-08-27
US20030062590A1 (en) 2003-04-03
JP2003162954A (ja) 2003-06-06
US6611039B2 (en) 2003-08-26
CN1409396A (zh) 2003-04-09

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