TWI277170B - Method for fabricating capacitor in semiconductor device - Google Patents
Method for fabricating capacitor in semiconductor device Download PDFInfo
- Publication number
- TWI277170B TWI277170B TW092118307A TW92118307A TWI277170B TW I277170 B TWI277170 B TW I277170B TW 092118307 A TW092118307 A TW 092118307A TW 92118307 A TW92118307 A TW 92118307A TW I277170 B TWI277170 B TW I277170B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- capacitor
- forming
- dielectric
- torr
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000003990 capacitor Substances 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 230000001590 oxidative effect Effects 0.000 claims abstract description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 229910052732 germanium Inorganic materials 0.000 claims description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 claims description 4
- 238000005121 nitriding Methods 0.000 claims description 4
- 229910052726 zirconium Inorganic materials 0.000 claims description 3
- 229910052745 lead Inorganic materials 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 230000002708 enhancing effect Effects 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 3
- 229910052710 silicon Inorganic materials 0.000 abstract 3
- 239000010703 silicon Substances 0.000 abstract 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 99
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 7
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 5
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 5
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 5
- 229910000449 hafnium oxide Inorganic materials 0.000 description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 4
- 239000004576 sand Substances 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000005201 scrubbing Methods 0.000 description 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 235000011114 ammonium hydroxide Nutrition 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052770 Uranium Inorganic materials 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- AJXBBNUQVRZRCZ-UHFFFAOYSA-N azanylidyneyttrium Chemical compound [Y]#N AJXBBNUQVRZRCZ-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- XYFCBTPGUUZFHI-UHFFFAOYSA-O phosphonium Chemical compound [PH4+] XYFCBTPGUUZFHI-UHFFFAOYSA-O 0.000 description 1
- XNGIFLGASWRNHJ-UHFFFAOYSA-N phthalic acid Chemical compound OC(=O)C1=CC=CC=C1C(O)=O XNGIFLGASWRNHJ-UHFFFAOYSA-N 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- JFALSRSLKYAFGM-UHFFFAOYSA-N uranium(0) Chemical compound [U] JFALSRSLKYAFGM-UHFFFAOYSA-N 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
- H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32105—Oxidation of silicon-containing layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3211—Nitridation of silicon-containing layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
Description
1277170 玖、發明說明: (一) 發明所屬之技術領域 本發明係關於一種半導體裝置的製造方法;尤其是半 導體裝置之電容器的製造方法。 (二) 先前技術 由於半導體裝置的大型積體性,例如動態隨機存取記 億體(DRAM),所以用以儲存資訊之記憶體單胞的總面積已 快速減少。 尤其,記憶體單胞面積的減少會使得記憶體單胞中電 容器的面積減少。但是,記憶體單胞面積的減少反而會使 感測界限和感測速度降低。此外,此種記憶體單胞面積的 減少也會降低對α粒子所產生的軟錯誤之容許度。 電容器之電容値由下式定義: C= ε x As/d 第 1 式 在此,ε是介電質常數;As爲電極的有效面積;d是 電極間的距離。 根據第1式,增加電容器之電容値的方法有三:第一 種方法是使電極的有效表面積變寬;第二種方法是減少介 電物質的厚度;及第三種方法是增加介電質常數。 在這三種方法當中,第一種方法是最先被考慮用以增 加電容器之電容値。如上所述,在第一種方法當中,使電 極的有效表面積變寬。因此,電容器應該由特殊的三維結 構所形成,如凹窪結構,柱狀結構’多重層針狀結構等等。 但是,由於半導體裝置的超大型積體性,所以此種方法已 一5 一 1277170 變得有所限制。 另一種減少介電物質的厚度,以縮減電極間的距離d 之方法’也面臨由於介電物質的厚度減少之事實,造成漏 電流增加的限制。 因此’目前的硏究和發展都集中在如何藉由增加介電 質常數,增加電容器之電容値。典型上,大部分的電容器 都具有用以當作介電質層之氧化矽層和氮化矽層之所謂的 氮化物-氧化物(NO)結構。但是,用於電容器之介電質層 係由具有高介電質常數之材料,如Ta205,(Ba,Sr)Ti03(BST), 和類似的材料,或鐵電材料,如(Pb,Zr)Ti03(PZT),(Pb5 La)(Zr,Ti)03(PLZT),SrBi2Ta2I9(SBT),Bi4-XLaXTi3012(BLT) 和類似的材料所製成的。 第1 A圖到第1 C圖爲具有圓柱形結構之電容器的傳統 製造方法橫截面圖。 如第1 A圖所示,在基板丨〇之中形成活性區〗丨。在基 板1 〇之上形成層間絕緣層1 2之後,形成貫穿層間絕緣層 1 2,用以接觸基板1 〇的活性區丨1之接觸孔洞。用導電金 屬埋藏接觸孔明,以形成接觸栓1 3。然後,形成高度和電 容器相同之絕緣層1 4。 選擇性蝕刻絕緣層1 4,以曝露接觸栓1 3而形成溝渠。 用導電矽層形成下電極1 5,而且其係沿著包含溝渠之縱深 沉積。然後,移除絕緣層1 4。 如第1B圖所示,使用氨氣(NH3)電漿,在下電極15上 形成厚度範圍約5人到50A之氮化矽層16。 1277170 參考第1C圖,在氮化矽層16上形成介電質層17,然 後用導電層在其上形成上電極。 在此,形成氮化矽層1 6係用以防止在後續的高溫製程 期間形成氧化矽層。若具有低介電質常數之氧化矽層形成 在介電質層之上和之下,則電容器的介電質特性會退化。 因爲下電極1 5爲圓柱狀結構,所以氮化矽層1 6並非 很均勻地形成在下電極1 5的表面上。因此,氧化矽層會過 多地形成在部分在其上沒有氮化物層1 6形成之下電極1 5 上。結果,由於形成過多無意的氧化物,所以會在下電極1 5 的某些部分上發生電容値退化的問題。 此外,用以防止電容値減少之氮化物層會產生一個問 題,就是電容器的漏電流會增加,而崩潰電壓會降低。 (三) 發明內容 因此’本發明之目的係要提供一種半導體裝置之電容 器的製造方法’以改善電容値並同時增強漏電流特性和崩 潰電壓特性。 根據本發明之方向,提供半導體裝置之電容器的製造 方法’包含下列步驟:(a)在基板上形成當作下電極之導電 砂層;(b)氮化處理該導電矽層;(c)氧化處理該已氮化之導 電砍層,(d)在該氧化層的表面上形成氮化砂層;(e)在該氮 化砂層上形成介電質層;及(f)在該介電質層上形成上電極。 (四) 實施方式 下面’將參考附圖詳細說明根據本發明製造之半導體 裝置的電容器。 一 Ί 一 1277170 第2A圖到第2E圖爲根據本發明優選實例,半導體裝> 置之電容器的製造方法橫截面圖。 如第2A圖所示,在基板20之中形成活性區21。在基 板2 0之上形成層間絕緣層2 2之後,形成貫穿層間絕緣層2 2 之接觸孔洞,使得栓23可以接觸基板20之活性區2 1。用 導電金屬塡埋接觸孔洞,以形成栓23。下面’將此栓23稱 爲接觸栓。以氧化物層或熱氧化物層形成層間絕緣層2 2 ° 該氧化物層係由選擇自由未摻雜矽酸玻璃(USG),磷矽酸玻 璃(PSG),硼磷矽酸玻璃(BPSG),高密度電漿(HDP),施佈鲁 玻璃(SOG)和四乙基原矽酸(TEOS)所組成之群組的材料所製 成的。該熱氧化物層係在約從600 °C到1 l〇〇°C之溫度範圍 下,將矽基板氧化所形成的。 形成和電容器的高度相同之絕緣層24。該絕緣層24係 使用厚度範圍約從3 000A到5 000A之氧化物層或熱氧化物 層所形成的。此處,該氧化物層和熱氧化物層係以和上述 相同之方法形成。 其次,選擇性蝕刻絕緣層24,直到曝露出接觸栓23, · 使得可以形成溝渠。沿著包含溝渠之縱深,形成下電極2 5。 此時,下電極2 5係由多晶矽所製成的。 在更詳細地說明下電極25的形成方面,先沉積厚度範 圍約從50人到30 0A之雜質摻雜多晶矽層。接著再沉積厚 度範圍約從50人到3 00A之雜質未摻雜多晶矽層,然後在 氮氣(N2)的環境中,在其上摻雜氫化磷(PH3)。 參考第2B圖,移除用於電容器之絕緣層24,然後執 - 8 - 1277170 行sc-1淸洗製程。此時,在sc-1淸洗製程中,使用氫氟 酸(HF)或氧化物緩衝鈾刻液(BOE)移除絕緣層24。SC-1淸 洗製程也可以採用氫氧化銨(NH4OH),雙氧水(H202)和 H20。SC-1淸洗製程的結果,形成厚度範圍約從5A到10A 之第一氧化矽層26,其多少可以圍繞下電極25。該第一氧 化物層26係當執行SC-1淸洗製程時,會在SC-1淸洗製程 期間,形成厚度範圍約從5 A到1 0 A之薄的自然氧化物層。 之後,在N2的環境中,將形成當作下電極2 5之多晶 矽層摻雜PH3。此時,摻雜係在約從5 00°C到80(TC的溫度 範圍下,和在約從0.1 Torr到100 Torr的壓力範圍下執行。 此摻雜係要最小化在電容器操作時所發生之空乏現象。 然後,執行熱處理製程。在介電質層沉積製程之後, 使用N20環境之爐管執行熱處理製程時,此製程多少可以 密化第一氧化矽層2 6,及使下電極2 5有最小的氧化。 如第2C圖所示,藉由使用壓力範圍約從1〇 T〇rr到100 Toh之爐管所完成之熱處理製程,均勻地形成第一氮化矽 層27。 參考第2D圖,藉由將基板20曝露在大氣中,在第一 氮化矽層27之上形成第二氧化矽層28。此時,第二氧化矽 層2 8的厚度範圍約從1 A到5 A。第二氧化矽層2 8係基板 20曝露在大氣中所產生之自然氧化物層。 然後使用二氯矽烷(DCS)源,在壓力範圍約從1 Torr到 10 Torr之NH3環境中,沉積第二氮化矽層SiN4 2 9。在此, 第一和第二氮化矽層2 7和2 9所形成之厚度範圍約從5 A到 -9 一 1277170 2 o A 〇 λ 如第2E圖所示,在第二氮化矽層之上,形成厚度範圍 約從30Α到100Α之介電質靥30。此時,形成介電質層30 之溫度範圍約從300 °C到5 00 °C,此外,形成介電質層30之 壓力範圍約從〇·1 Torr到1.0 T0rr。爲了改善元件特性和介 電質層30的結晶,使用N2〇或〇2環境之爐管,執行熱處 理製程。此時,執行熱處理製程之溫度範圍約從5 0 0 °C到 8 00〇C。 在使用下Ta205形成介電質層30之情形中,介電質層馨 係使用Ta(C2H50)5和02當作材料源和反應氣體所形成的。 此時,介電質層3 0的形成係在約從3 0 0 °C到5 0 0 °C的溫度範 圍下,及約從〇· 1 Torr到1 ·〇 Torr的壓力範圍下完成。此 外,介電質層30的厚度範圍約從20A到100A。介電質層 30係由選擇自由具有高介電質常數之物質,如a12〇3, Hf02, BST等之群組,或鐵電物質,如PZT,PLZT,BLT等之群組 的材料所製成的。 其次,使用導電層,在介電質層30上形成上電極31。 ® 上電極31係藉由使用化學氣相沉積法(CVD)沉積TiN層所 形成的,然後在上電極3 1之上形成多晶矽層。 使用上述之製程,在介電質層30和下電極29之間, 形成第一氮化矽層2 7,第二氧化矽層2 8和第二氮化矽層 29 °此製程稱爲第一次有效爐管氮化(EF2N)製程。在此, 第一和第二氮化矽層2 7和2 9係要防止產生過多的氧化物 層,以確保預定的電容値,而第二氧化矽層2 8係用以改善 一 1 0 - 1277170 漏電流特性和崩潰電壓特性。 第3A圖到第3C圖爲根據本發明所製造之電容器的有 效建構特性圖。 尤其,圖示在用以抑制介電質層間的介面上之氧化物 層形成的傳統NH3電漿製程下,和在用以抑制下電極和介 電質層間的介面上之氧化物層形成的上述EF2N製程下,所 獲得之電容器的電容値Cs,漏電流和崩潰電壓特性。 參考第3 A圖和第3B圖,相較於藉由傳統NH3電漿製 程(NH3 PLT)所製造之電容器的電容値,電容値Cs可以使 用EF2N製程改善。此外,漏電流和崩潰電壓特性則保持不 變 〇 本發明已參考特殊實施例說明,但是明顯地,熟悉此 項技術之人士所做的各種變化例和修正例,.可能不會脫離 本發明在後面之申請專利範圍所定義的精神和範圍。 (五)圖式簡單說明 根據下面參考附圖之優選實施例的說明,本發明前面 的和其他的目的和特徵將會變得很明顯,其中: 第1 A圖到第1 c圖爲具有圓柱形結構之電容器的傳統 製造方法橫截面圖; 第2 A圖到第2 E圖爲根據本發明優選實施例,半導 體裝置之電容器的製造方法橫截面圖;及 第3A圖到第3C圖爲根據本發明所製造之電容器的有 效建構特性圖。 元件符號說明 _ 1 1 - 基板 活性區 層間絕緣層 接觸栓 絕緣層 下電極 氮化5夕層 介電質層 上電極 基板 活性區 層間絕緣層 接觸栓 絕緣層 下電極 第一氧化砂層 第一氮化矽層 第二氧化矽層 第二氮化矽層 介電質層 上電極 -12-
Claims (1)
1277170 拾、申請專利範圍: 1· 一種半導體裝置中之電容器的製造方法,包含下列步"驟 (a) 在基板上形成當作下電極之導電矽層; (b) 氮化處理該導電矽層; (c )氧化處理該已氮化之導電矽層; (d) 在該氧化層的表面上形成氮化矽層; (e) 在該氮化矽層上形成介電質層;及 (f) 在該介電質層上形成上電極。 2 ·如申請專利範圍第1項之方法,其中在步驟(c ),使用自 然氧化物層。 3 ·如申請專利範圍第2項之方法,其中所形成之自然氧化 物層,厚度範圍約從1A到5人。 4 ·如申請專利範圍第3項之方法,其中在步驟(b),熱處理 製程係在壓力範圍約從1 0 Torr到1 00 Torr之NH3氣體 的環境中完成。 5 ·如申請專利範圍第4項之方法,其中氮化矽層係使用二 氯矽烷(DCS)源,在壓力範圍約從1 Torr到1 0 Torr之NH3 氣體的環境中所形成的。 6 .如申請專利範圍第3項之方法,其中該介電質層係由選 擇自由具有高介電質常數之物質,如Ta2 05, A1203, Hf02, (3^3〇1^03(88丁)等所組成之群組,或鐵電物質,如(?13,2:〇 Ti03(PZT),(Pb,La)(Zr,Ti)03(PLZT),Bi4-XLaXTi3〇12 (BLT)等所組成之群組的材料所製成的。
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US7170736B2 (en) * | 2003-08-28 | 2007-01-30 | Tessera, Inc. | Capacitor having low resistance electrode including a thin silicon layer |
US9373675B2 (en) * | 2012-02-06 | 2016-06-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Capacitor structure and method of forming the same |
US11251261B2 (en) * | 2019-05-17 | 2022-02-15 | Micron Technology, Inc. | Forming a barrier material on an electrode |
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US5677867A (en) * | 1991-06-12 | 1997-10-14 | Hazani; Emanuel | Memory with isolatable expandable bit lines |
US5760767A (en) * | 1995-10-26 | 1998-06-02 | Sony Corporation | Method and apparatus for displaying in and out points during video editing |
US5670431A (en) * | 1996-06-13 | 1997-09-23 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of forming an ultra thin dielectric film for a capacitor |
US6052508A (en) * | 1997-04-04 | 2000-04-18 | Avid Technology, Inc. | User interface for managing track assignment for portable digital moving picture recording and editing system |
FR2766211B1 (fr) * | 1997-07-15 | 1999-10-15 | France Telecom | PROCEDE DE DEPOT D'UNE COUCHE DIELECTRIQUE DE Ta2O5 |
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US20020197790A1 (en) * | 1997-12-22 | 2002-12-26 | Kizilyalli Isik C. | Method of making a compound, high-K, gate and capacitor insulator layer |
JP2000307084A (ja) * | 1999-04-23 | 2000-11-02 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
US6350707B1 (en) * | 1999-09-03 | 2002-02-26 | United Microelectronics Corp. | Method of fabricating capacitor dielectric |
JP3693875B2 (ja) * | 2000-01-26 | 2005-09-14 | Necエレクトロニクス株式会社 | 回路製造方法 |
US7129128B2 (en) * | 2001-08-29 | 2006-10-31 | Micron Technology, Inc. | Method of improved high K dielectric-polysilicon interface for CMOS devices |
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