TWI272700B - Semiconductor device having a coil with large value of Q - Google Patents

Semiconductor device having a coil with large value of Q Download PDF

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Publication number
TWI272700B
TWI272700B TW091114616A TW91114616A TWI272700B TW I272700 B TWI272700 B TW I272700B TW 091114616 A TW091114616 A TW 091114616A TW 91114616 A TW91114616 A TW 91114616A TW I272700 B TWI272700 B TW I272700B
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Taiwan
Prior art keywords
semiconductor device
semiconductor substrate
coil
bonding wire
pad
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TW091114616A
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English (en)
Inventor
Hiroshi Miyagi
Akira Okamoto
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Niigata Seimitsu Co Ltd
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Publication of TWI272700B publication Critical patent/TWI272700B/zh

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Description

1272700 五、發明説明 [技術領域] 本發明係有關於一種半導， 但干令體裝置，其係於半導體基板 形成有線圈與天線者。 [習知背景] 已么有半導體電路係於半導體基板上利用薄膜成形技 術形成-螺旋形狀圖案，利用該圖案作為線圈者。 第斤圖係”、、員不形成於該半導體基板上之線圈的具體例 第圖所不，在该半導體基板100表面上藉金屬圖 案（例如銅或金的薄膜圖案）而形成螺旋形狀之線圈110。藉 將該線圈110形成於前述半導體基板100的表面，可將含 4圈在内而構成之振動為等之所有零件一體形成於該半導 體基板110上’且不要外部零件，因此可減低零件件數或 將程序簡化，並可大幅減少成本。 但，如上述於該半導體基板100形成前述線圈110時， 由於無法將該線圈110的直徑拉大，因而有無法確保高感 應係數的問題。又，因為該線圈11〇正下方有半導體基板 在所以於该半導體基板之表面產生渴流，而有無法取 得高Q值的問題。 [發明之揭示] 本發明係有鑑於此點而創作者，其目的在於提供一種 半導體裝置’其可於前述半導體基板形成一具有前述高感 應係數及高Q值的線圈者。 為解決上述之課題，本發明之半導體裝置係具有：第 1塾’係形成於具有矩形形狀之半導體基板的角部附近； ,,,,,..........%ί: (請先閲讀背面之注意事項再填寫本頁) •訂丨
A4規格（210X297公釐） -4- 2 1272700 五、發明説明（ 及接σ線侍、至少一端與該塾相連接者。藉利用形成於 該半導體基板之角部附近之第1塾，可使線圈用之接合線 增長，並可取得極大之感應係數。又，-般說來，半導體 基板之角部係成為未形成有塾之空領域，因此在該領域形 成第1塾，則可謀求半導體基板表面之有效利用。又，一 般而言，接合線係形成於間隔半導體基板表面有些距離之 位置上’因而可在將該接合線當作線圈用時，減少於該半 導體基板表面所產生之渴流，並可得到高q值。 又月述半導體基板係宜於前述角部外之周邊領域 上，具有作為内部電路配線之用的第2塾。將上述第i整 配置於該半導體基板之角部，且將内部電路配線用之第2 塾=置在除此以外之周邊領域上，因此可在不減少用以形 成爾述第2墊之領域的狀態下，形成前述線圈形成用之第 1墊及與該第1墊相連接之接合線。 又，上述接合線係宜形成為與相鄰接之角部相對應之 兩：刖述第1墊間連續連成一環狀者。藉將形成於各角部 之第1墊間連成環狀，即可取得對於前述半導體基板相當 有限之表面積而極大之感應係數。 又，對應於一個前述角部而形成多個前述第丨墊時， 料接合線係宜形成為與相鄰接之角部相對應之兩^述 第1塾間連續且多重連成環狀者。藉此，進而可形成感應 係數更大之線圈。 特別是對應於-個前述角部而形成之多個前述第工塾 係以對於鄰接在該角部之邊呈斜向配置者為佳。藉將一個 :本紙張尺度適财⑽
嘬…： (請先閲讀背面之注意事項再填寫本頁) 訂丨ί 1272700 五、發明說明 i角销形成之多個第i墊呈斜向配 鄰的接合線互相接觸。 避開相 (請先閲讀背面之注意事項再填寫本頁) 又，上述接合線係宜形成在與位在前述矩形形狀之對 角線上之角部所對應之兩個前述第ι塾間者。利用形成於 忒對角線上之接合線’與利用沿外圍形成之接合線相比 較，可形成電感係數不同之線圈。 义又i用以連接前述第1墊之接合線係宜俟其於用以連 接月J逃第2墊之接合線形成結束後再形成者。藉此，口兩 在最後追加前述第1墊所對應之接合線的形成步驟， 進行線圈之形成，因此可將程序之變更抑制到最小限度。 又，利用業已連接前述第i塾之前述接合線以形成天 、本用之線圈，並將該天線用線圈與形成在前述半導體基板 上之電路相連接者為佳。藉此，可將前述天線用線圈及與 此相連接之電路全體形成於前述半導體基板上，與使用外 部零件之天線時相比較，將能因零件件數減少，而使得零 件成本、製造成本等跟著降低。 ^ 又，利用前述第1墊所連接之接合線以形成電感器用 之線圈，並將該電感器用線圈與形成在前述半導體基板上 之電路相連接者為佳。藉此，可將前述電感器用線圈及與 此相連接之電路全體形成於前述半導體基板上，與使用外 部零件之電感器用線圈時相比較，將能因零件件數減少， 而使得零件成本、製造成本等跟著降低。 [發明之實施形態] 以下，針對適用本發明之一實施型態的半導體裝置，
1272700
邊參照圖示加以具體說明。 (請先閲讀背面之注意事項再填寫本頁) 第1圖係顯不本實施型態之半導體裝置的平面圖。 又，第2圖係第1圖所示之該半導體裝置的部分透視圖。 如這些圖所示，本實施型態之半導體裝置1〇係由包含有矩 形形狀之半導體基板12、於該半導體基板12之四個角部 附近形成之多數墊20、沿角部以外之各邊之周邊領域形成 之多數墊30，及，用以連接相鄰接之墊2〇間之接合線如 所構成。 丽述接合線40係將形成於相鄰接角部之兩墊2〇間連 續相連。具體而言，墊2Ga與墊20b各別形成於一個角部 及與該角部相鄰接之角部上，而後接合線4〇a如同連接該 兩墊20a、20b間一般地形成。又，在與墊2〇b形成之角部 相鄰接之角部上形成墊2〇c，而後接合線4〇b如同連接該 兩墊20b、20c間一般地形成。同樣地，在與墊2〇c形成之 角部相鄰接之角部上形成墊20d，而後接合線4〇c如同連 接該兩墊20c、20d間一般地形成。進而，在墊2〇a與墊 20d間靠近墊20a附近形成墊32 ,而後接合線4〇d如同連 接墊20d、32間一般地形成。如此，藉墊2〇&、32將接合 線40a、40d之各一端作為末端，並藉墊2补、2〇c、2〇d 分別中繼接合線40a、40b、40c、40d，因此就全體而言形 成一約沿前述半導體基板12外圍繞一圈之線圈。 第3圖係用以顯示本實施型態之半導體裝置丨〇中接合 線之形成順序者。本實施型態之半導體裝置1〇 一旦固定在 配線基板（無圖示）的規定位置上，首先，如圖所示， 雜本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） !27270〇 五、發明説明（5 藉使用接口線50之引線接合’對形成於該角部以外之周邊 員或上之塾30進行配線。此步驟係與至今所進行之引線接 合程序相同者。接著，如第！圖及第2圖所示’藉連接設 於该角部或該角部附近之墊2〇間或塾2〇、^間之接合線 進仃配線。此日以接合線4G之形成係如同越過相鄰接之塾 %間或越過墊2G與墊32之間而形成般，因此可與形成於 二下側之墊3G及連接该塾3G之接合線5G維持—隔離狀 態。 ^旦，丽述接合線40所形成之線圈可想為做天線用之線 圈。藉此，可將該天線用線圈及與此相連接之發送電路斑 $收電路等全體形成於前述半導體基板12上，與使用外部 令件之天線時相比較，將能因零件件數減少，而使得零件 成本與製造成本跟著降低。 或，前述接合線40所形成之線圈可想為作電感器用之 線圈。藉此，可將該電感器用線圈及與此相連接之振動器 與同調電路等全體形成於前述半導體基板12上，與使用外 部零件之電感器用線圈天線時相比較，將能因零件件數減 少’而使得零件成本與製造成本跟著降低。 如此，利用形成於前述半導體基板12之四個角部附近 之墊20 ’而形成線圈用之接合線4〇，因而對於前述半導體 基板12相當有限之表面積，可將該接合線之長度拉長， 並取得極大之感應係數。 又，一般說來，前述半導體基板12之角部係成為未形 成有内部電路配線用之墊30之空領域’因此利用該領域而 (請先閲讀背面之注意事項再填寫本頁)
、可I
6 6 五 12727〇〇 Λ發明説明 圯成墊20,以之用以形成作線圈用之接合 爾述半導體基板12表面之有效利用。 #進而刖述接合線4〇係形成於間隔該半導體基板12 衣面有些距離之位置上， 田 口而可在該接合線40作為線圈之 用日Τ，減少於該半導體某妨 板1 2表面所產生之渦流，並可得 到面Q值。 且，本發明不只限定在前述實施型態，亦可在本發明 2旨之範圍内進行種種的變形實施。例如，於前述實施型
怨，雖然』述接合線4G之形成如同沿前述半導體基板U 之周圍繞-圈般’但亦可將該圍繞次數設定於不滿一圈或 兩圈以上。 第4圖係顯示半導體裝置—之平面圖，其係將前述 接合線40之圍繞次數設定於2次者。如第4圖所示，墊 2〇、24、32係形成於前述半導體基板12之_個角部附近。 兩墊20、32 一邊係對應於線圈之前端，另—邊則對應於末 端。墊24係連接構成外側線圈之接合線4〇及構成内側線 圈之接合線42，並加以中繼連接此線圈。 又，塾20、22係形成於除此以外之角部附近。這兩墊 20、22係配置於該對角角部相鄰接之邊所相對之斜向位 置。一邊的墊20係連接構成外側線圈之兩條接合線4〇， 且中繼而成該線圈。另一邊的墊22係連接構成内侧線圈之 兩條接合線42，且中繼而成該線圈。 如此’將該接合線之圍繞次數設定在兩次或兩次以 上，將可形成具有高感應係數之線圈。又，如第4圖所示， 本紙張尺度適用中國國家標準（CNS) Α4規格（210X297公釐） •……-----------------------------------MW. (請先閲讀背面之注意事項再填寫本頁) -9- 1272700 五、發明説明（ =位於"亥角部附近之墊20、22斜向配置，將可防止用以中 繼忒墊20、22而形成之外側線圈與内側線圈重疊，且可避 開相鄰接之接合線40、42互相接觸。 又，於前述實施型態，雖然接合線4()係沿前述半導體 基板12之周邊而形成者，但亦可用接合線連接前述墊20， 忒墊20係形成於位在前述具有矩形形狀之半導體基板p 對角線上之角部者。 第5圖係半導體裝置1〇B之概略平面圖，該半導體裝 置10B具有藉接合線4〇B連接位於前述半導體基板12對 角線上的兩墊2 〇間而成之線圈。如第5圖所示，利用沿對 角、.良業已形成之接合線，或加以搭配該接合線與第1圖等 所示之接合線40等，因此可形成有不同於單純沿前述半導 體基板12之周圍環繞該接合線4〇型態之感應係數之線 圈’並可按其用途加以靈活運用。 又，於前述實施型態，雖已說明在前述半導體基板12 上形成—個線圈之情形，但亦可劃分該半導體基板12之表 面’以形成兩種或兩種以上之線圈。 、，第6圖係顯示於前述半導體基板12上形成有兩種線圈 之半：體裝置10C概略結構之平面圖。如第6圖所示，假 想將前述半導體基板12之表面分割為兩個領域，而後沿夂 分割領域之周圍分別形成接合線，則可形成㈣線圈 些線圈的用途係可考慮將其中一種作為天線用之線圈，另 一種則用作電感器用線圈，或者將其中一種作為發送用之 天線用線圈，另一種則用作接收用之電感線圈等。 1本紙張尺度適用中國國家標準（CNS) A4規格（2K)X297公釐） ----------•裝…-- (請先閲讀背面之注意事項再填寫本頁) 訂！ 着， -10- 1272700 A7 ___________B7_ 五、發明説明（8 ) 一 --~^ [產業可利用性] 如上述之詳細說明，按本發明，藉使用形成於前述半導 體土板角#附近之第i墊，可使作為線圈用之接合線增 二可取得極大之感應係數。又，一般說來，半導體美 ^反之角部係成為未形成有墊之空領域’因此在該領域形成 第1塾，則可謀求半導體基板表面之有效利用。又，—般 而曰，接合線係形成於間隔半導體基板表面有些距離之位 置上因而可在將該接合線當作線圈用時，減少半導體基 板表面所產生之渦流，並可得到高Q值。 土 [圖式之簡單說明] 第1圖係顯示一實施型態之半導體裝置之平面圖。 第2圖係顯示第1圖中所示之半導體裝置之部分透視 圖。 第3圖係用以顯示半導體裝置中接合線之形成順序 者。 第4圖係顯示將接合線的圍繞數設定為2次之半導體 裝置的平面圖。 第5圖係半導體裝置的概略平面圖，該半導體裝置具 有’藉接合線連接位於半導體基板對角線上的兩墊之間而 成之線圈。 第6圖係顯示於半導體基板上形成有兩種線圈之半導 體裝置概略結構之平面圖。 第7圖係顯示形成於半導體基板上之線圈的具體例 圖0 、本紙張尺度適用中國國家標準（CNS) A4規格（210X297公嫠） ..........%…： (請先閲讀背面之注意事項再填寫本頁} 、^τ— 1272700 A7 B7 五、發明説明（9 ) [圖中標號說明] 10... 半導體裝置 32... .墊 10A ...半導體裝置 34... .接合線 10B ...半導體裝置 40... .接合線 10C ...半導體裝置 40B ...接合線 12... 半導體基板 4 0 a · · · 4妾 、線 20... 墊 40b. ..接合線 20a. .•墊 40c. ..接合線 20b. • •墊 4 0 d…接合線 20c. ..墊 42··, .接合線 20d. •.墊 50 ·· .接合線 22... 墊 100. ...半導體基板 24... 墊 110. ..線圈 30... 墊 (請先閲讀背面之注意事項再填寫本頁) ，本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） -12-

Claims (1)

  1. 'f,? 1272700 申請專利範圍 第91114616號專利申請案申請專利範圍修正本92年10月3曰 1 · 一種半導體裝置，係具有·· 多數第1墊’係分別形成於具有矩形形狀之半導體 基板上多數相異的角部附近；及 接合線，其兩端連結於前述多數第1墊。 2.如申請專利第Μ之半導體裝置，其中該半導體基 板係於前述角部外的周邊領域上，具有用於内部電路配 線之第2墊。 3·如申請專利範圍第μ之半導體裝置，其中該接合線係 將相鄰接之角部對應之兩個前述第ι塾間連續連成一環 狀者。 4.如申請專利範圍第】項之半導體裝置，其中該第i塾係 對應於-個前述角部而形成多個，而前述接合線則將對 應於相鄰接之角部之兩個前述第β 環狀者。 又里逆风 5·如申請專利範圍第]項之半導體裝置，其中該對應於一 角 個則述角部而形成之多個前述第！塾係對於鄰接在該 部之邊呈斜向配置。 係 應 m專利範圍第1項之半導體裝置，其中該接合線 形成在與位在前述矩形形狀之對角線上之角部所對 之兩個前述第1墊之間者。 7·=^專利範圍第1項之半導體裝置，其中該用以連接 1墊之接合線係俟其於用以連接前述第之塾之接 &線形成結束後再形成者。 ^氏張尺度適(CNS) A4規格（2ι〇χ297公楚厂 -13- ^72700 A8
    如2請專利範圍第1項之半導體裝置，其係利用業已連 ，、述第1墊之則述接合線以形成天線用之線圈，並將 °亥天線用線圈與形成在前述半導體基板上之電路相連 接。 .如=請專利範圍第1項之半導體裝置，其係利用業已連 =則述第1墊之前述接合線以形成一電感器用之線圈， 亚將該電感器用線圈與形成在前述半導體基板上之電 路相連接。 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） -14-
TW091114616A 2001-07-25 2002-07-02 Semiconductor device having a coil with large value of Q TWI272700B (en)

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US3795845A (en) * 1972-12-26 1974-03-05 Ibm Semiconductor chip having connecting pads arranged in a non-orthogonal array
JPS62145764A (ja) * 1985-12-19 1987-06-29 Mitsubishi Electric Corp 半導体集積回路
JP2594541B2 (ja) * 1986-03-31 1997-03-26 日本電気株式会社 半導体集積回路
JP2560805B2 (ja) * 1988-10-06 1996-12-04 三菱電機株式会社 半導体装置
JPH03263366A (ja) * 1990-03-13 1991-11-22 Fujitsu Ltd 半導体装置及びその製造方法
JPH04299565A (ja) * 1991-03-27 1992-10-22 Mitsubishi Electric Corp Ｉｃチップ
IT1252136B (it) * 1991-11-29 1995-06-05 St Microelectronics Srl Struttura di dispositivo a semiconduttore con dissipatore metallico e corpo in plastica, con mezzi per una connessione elettrica al dissipatore di alta affidabilita'
JPH1074625A (ja) * 1996-08-30 1998-03-17 Ikeda Takeshi インダクタ素子
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US6858946B2 (en) 2005-02-22

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